Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDYLOWF : DC-DC Converter Ready Low Flag.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The output voltage (VDC) is below the threshold set in the RDYLOWTH threshold field (RDYLOWTH).
1 : SET
The output voltage (VDC) is above the threshold set in the RDYLOWTH threshold field (RDYLOWTH).
End of enumeration elements list.
RDYHIGHF : DC-DC Converter Ready High Flag.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The output voltage (VDC) has not exceeded 105% of the programmed output value.
1 : SET
The output voltage (VDC) has exceeded 105% of the programmed output value.
End of enumeration elements list.
DROPOUTF : DC-DC Converter Dropout Flag.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The input voltage (VBATDC) is more than 0.4 V above the output voltage (VDC). The DC-DC converter is not in dropout.
1 : SET
The input voltage (VBATDC) is less than 0.4 V above the output voltage (VDC). The DC-DC converter is in dropout, and firmware should enable the bypass switch (BEN=1).
End of enumeration elements list.
BGRDYF : Bandgap Ready Flag.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
1 : SET
The bandgap voltage is above the threshold.
End of enumeration elements list.
OSCDIS : Oscillator Disable.
bits : 8 - 8 (1 bit)
Enumeration:
0 : INACTIVE
Enable the DC-DC local oscillator.
1 : ACTIVE
Disable the DC-DC local oscillator.
End of enumeration elements list.
CLKSEL : Clock Source Select.
bits : 9 - 9 (1 bit)
Enumeration:
0 : DCDCOSC
Select the local DC-DC oscillator as the clock source.
1 : AHB
Select the AHB clock as the clock source.
End of enumeration elements list.
CLKDIV : Clock Divider.
bits : 10 - 12 (3 bit)
Enumeration:
0 : DIV1
Use the AHB clock divided by 1 as the converter switching frequency.
1 : DIV2
Use the AHB clock divided by 2 as the converter switching frequency.
2 : DIV4
Use the AHB clock divided by 4 as the converter switching frequency.
3 : DIV8
Use the AHB clock divided by 8 as the converter switching frequency.
4 : DIV16
Use the AHB clock divided by 16 as the converter switching frequency.
End of enumeration elements list.
ADCSYNCEN : ADC Synchronization Enable.
bits : 13 - 13 (1 bit)
Enumeration:
0 : DISABLED
Do not synchronize the ADC to the DC-DC converter.
1 : ENABLED
Synchronize the ADC to the DC-DC converter.
End of enumeration elements list.
CLKINVEN : Clock Inversion Enable.
bits : 14 - 14 (1 bit)
Enumeration:
0 : DISABLED
Do not invert the AHB clock input.
1 : ENABLED
Invert the AHB clock input.
End of enumeration elements list.
ADCCLKINVEN : ADC Clock Inversion Enable.
bits : 15 - 15 (1 bit)
Enumeration:
0 : DISABLED
Do not invert the ADC clock derived from the DC-DC switching frequency.
1 : ENABLED
Invert the ADC clock derived from the DC-DC switching frequency.
End of enumeration elements list.
OUTVSEL : Output Voltage Select.
bits : 16 - 20 (5 bit)
MIEN : Module Interrupt Enable.
bits : 22 - 22 (1 bit)
Enumeration:
0 : DISABLED
Disable DC-DC module interrupts.
1 : ENABLED
Enable DC-DC module interrupts.
End of enumeration elements list.
MINPWSEL : Minimum Pulse Width Select.
bits : 24 - 25 (2 bit)
Enumeration:
0 : DISABLED
Disable pulse skipping.
1 : 10_NS
Set the minimum pulse width to 10 ns.
2 : 20_NS
Set the minimum pulse width to 20 ns.
3 : 40_NS
Set the minimum pulse width to 40 ns.
End of enumeration elements list.
PSMD : Power Switch Mode.
bits : 26 - 27 (2 bit)
Enumeration:
0 : SWSEL0
Mode 0. Set the M1 and M2 power switches to each use one MOSFET only.
1 : SWSEL1
Mode 1. Set the M1 and M2 power switches to each use 2 MOSFETS in parallel.
2 : SWSEL2
Mode 2. Set the M1 and M2 power switches to each use 3 MOSFETS in parallel.
3 : SWSEL3
Mode 3. Set the M1 and M2 power switches to each use 4 MOSFETS in parallel.
End of enumeration elements list.
ASYNCEN : Asynchronous Mode Enable.
bits : 28 - 28 (1 bit)
Enumeration:
0 : DISABLED
Enable DC-DC synchronous mode.
1 : ENABLED
Enable DC-DC asynchronous mode. This mode is more efficient for very light output loads.
End of enumeration elements list.
ABEN : Automatic Bypass Enable.
bits : 29 - 29 (1 bit)
Enumeration:
0 : DISABLED
Disable automatic bypass.
1 : ENABLED
Enable automatic bypass.
End of enumeration elements list.
BEN : Bypass Enable.
bits : 30 - 30 (1 bit)
Enumeration:
0 : DISABLED
Disable the MBYP bypass switch.
1 : ENABLED
Enable the MBYP bypass switch.
End of enumeration elements list.
DCDCEN : DC-DC Converter Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable the DC-DC converter.
1 : ENABLED
Enable the DC-DC converter.
End of enumeration elements list.
Module Configuration
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ILIMIT : Inductor Peak Current Limit.
bits : 4 - 6 (3 bit)
Enumeration:
1 : LIMIT1
Limit the peak inductor current to 200 mA.
2 : LIMIT2
Limit the peak inductor current to 300 mA.
3 : LIMIT3
Limit the peak inductor current to 400 mA.
4 : LIMIT4
Limit the peak inductor current to 500 mA.
5 : LIMIT5
Limit the peak inductor current to 600 mA.
6 : LIMIT6
Limit the peak inductor current to 700 mA.
7 : LIMIT7
Limit the peak inductor current to 800 mA.
End of enumeration elements list.
INTMD : Interrupt Mode.
bits : 16 - 17 (2 bit)
Enumeration:
0 : OUTPUT_TOO_LOW
Generate an interrupt when the regulated converter output voltage is too low.
1 : OUTPUT_NOT_TOO_LOW
Generate an interrupt when the regulated converter output voltage is not too low.
2 : OUT_OF_REG
Generate an interrupt when the output voltage is out of regulation. The converter output can be either too high or too low.
3 : IN_REG
Generate an interrupt when the output voltage is in regulation.
End of enumeration elements list.
RDYLOWTH : Converter Ready Low Threshold.
bits : 20 - 21 (2 bit)
Enumeration:
0 : 95_PERCENT
Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 95% of the programmed output voltage.
1 : 90_PERCENT
Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 90% of the programmed output voltage.
2 : 85_PERCENT
Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 85% of the programmed output voltage.
3 : 80_PERCENT
Hardware sets the RDYLOWF flag if the regulated output voltage is greater than 80% of the programmed output voltage.
End of enumeration elements list.
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