Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected
Module Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCOUNT : Active State Counter.
bits : 0 - 7 (8 bit)
ST : Active State.
bits : 8 - 11 (4 bit)
LASTST : Last State.
bits : 12 - 15 (4 bit)
access : read-only
INHSSEL : Inhibit Signal Select.
bits : 16 - 19 (4 bit)
Enumeration:
0 : DTMNINH0
Select inhibit signal source DTMnINH.0.
1 : DTMNINH1
Select inhibit signal source DTMnINH.1.
2 : DTMNINH2
Select inhibit signal source DTMnINH.2.
3 : DTMNINH3
Select inhibit signal source DTMnINH.3.
4 : DTMNINH4
Select inhibit signal source DTMnINH.4.
5 : DTMNINH5
Select inhibit signal source DTMnINH.5.
6 : DTMNINH6
Select inhibit signal source DTMnINH.6.
7 : DTMNINH7
Select inhibit signal source DTMnINH.7.
8 : DTMNINH8
Select inhibit signal source DTMnINH.8.
9 : DTMNINH9
Select inhibit signal source DTMnINH.9.
10 : DTMNINH10
Select inhibit signal source DTMnINH.10.
11 : DTMNINH11
Select inhibit signal source DTMnINH.11.
12 : DTMNINH12
Select inhibit signal source DTMnINH.12.
13 : DTMNINH13
Select inhibit signal source DTMnINH.13.
14 : DTMNINH14
Select inhibit signal source DTMnINH.14.
15 : DTMNINH15
Select inhibit signal source DTMnINH.15.
End of enumeration elements list.
DBGMD : Debug Mode.
bits : 23 - 23 (1 bit)
Enumeration:
0 : RUN
The DTM module will continue to operate while the core is halted in debug mode.
1 : HALT
A debug breakpoint will cause the DTM module to halt.
End of enumeration elements list.
INHF : Inhibit Status Flag.
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The inhibit signal is inactive.
1 : SET
The inhibit signal is active.
End of enumeration elements list.
DSTREQF : Destination Peripheral DMA Request Status Flag.
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The destination peripheral did not request a DMA transfer.
1 : SET
The destination peripheral requested a DMA transfer.
End of enumeration elements list.
SRCREQF : Source Peripheral DMA Request Status Flag.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : NOT_SET
The source peripheral did not request a DMA transfer.
1 : SET
The source peripheral requested a DMA transfer.
End of enumeration elements list.
DTMINH : DTM Module Inhibit.
bits : 27 - 27 (1 bit)
Enumeration:
0 : INACTIVE
The DTM module does not ignore DMA requests.
1 : ACTIVE
The DTM module ignores DMA requests until this bit is cleared.
End of enumeration elements list.
TOERRI : Timeout Error Interrupt Flag.
bits : 28 - 28 (1 bit)
Enumeration:
0 : NOT_SET
A timeout error has not occurred.
1 : SET
A timeout error occurred.
End of enumeration elements list.
DMAERRI : DMA Error Interrupt Flag.
bits : 29 - 29 (1 bit)
Enumeration:
0 : NOT_SET
A DMA error has not occurred.
1 : SET
A DMA error occurred.
End of enumeration elements list.
DTMI : Module Interrupt Flag.
bits : 30 - 30 (1 bit)
Enumeration:
0 : NOT_SET
A state transition or timeout has not occurred.
1 : SET
A state transition (SECSTIEN or PRISTIEN set to 1) or timeout (TOERRIEN = 1) occurred.
End of enumeration elements list.
DTMEN : Module Enable.
bits : 31 - 31 (1 bit)
Enumeration:
0 : DISABLED
Disable the DTM module.
1 : ENABLED
Enable the DTM module.
End of enumeration elements list.
Module Timeout
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TORELOAD : Timeout Counter Reload.
bits : 0 - 15 (16 bit)
TOCOUNT : Timeout Counter.
bits : 16 - 31 (16 bit)
Master Counter
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MSTCOUNT : Master Counter.
bits : 0 - 15 (16 bit)
State Address
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATEADDR : State Address.
bits : 2 - 31 (30 bit)
Active DTM State
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STRELOAD : Active State Counter Reload.
bits : 0 - 7 (8 bit)
access : read-only
SECST : Secondary State.
bits : 8 - 11 (4 bit)
access : read-only
PRIST : Primary State.
bits : 12 - 15 (4 bit)
access : read-only
DSTMOD : Destination Module.
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : DTMNDST0
Select destination module DTMnDST.0.
1 : DTMNDST1
Select destination module DTMnDST.1.
2 : DTMNDST2
Select destination module DTMnDST.2.
3 : DTMNDST3
Select destination module DTMnDST.3.
4 : DTMNDST4
Select destination module DTMnDST.4.
5 : DTMNDST5
Select destination module DTMnDST.5.
6 : DTMNDST6
Select destination module DTMnDST.6.
7 : DTMNDST7
Select destination module DTMnDST.7.
8 : DTMNDST8
Select destination module DTMnDST.8.
9 : DTMNDST9
Select destination module DTMnDST.9.
10 : DTMNDST10
Select destination module DTMnDST.10.
11 : DTMNDST11
Select destination module DTMnDST.11.
12 : DTMNDST12
Select destination module DTMnDST.12.
13 : DTMNDST13
Select destination module DTMnDST.13.
14 : DTMNDST14
Select destination module DTMnDST.14.
15 : DTMNDST15
Select no destination module (DTMnDST.15).
End of enumeration elements list.
SRCMOD : Source Module.
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : DTMNSRC0
Select source module DTMnSRC.0.
1 : DTMNSRC1
Select source module DTMnSRC.1.
2 : DTMNSRC2
Select source module DTMnSRC.2.
3 : DTMNSRC3
Select source module DTMnSRC.3.
4 : DTMNSRC4
Select source module DTMnSRC.4.
5 : DTMNSRC5
Select source module DTMnSRC.5.
6 : DTMNSRC6
Select source module DTMnSRC.6.
7 : DTMNSRC7
Select source module DTMnSRC.7.
8 : DTMNSRC8
Select source module DTMnSRC.8.
9 : DTMNSRC9
Select source module DTMnSRC.9.
10 : DTMNSRC10
Select source module DTMnSRC.10.
11 : DTMNSRC11
Select source module DTMnSRC.11.
12 : DTMNSRC12
Select source module DTMnSRC.12.
13 : DTMNSRC13
Select source module DTMnSRC.13.
14 : DTMNSRC14
Select source module DTMnSRC.14.
15 : DTMNSRC15
Select no source module (DTMnSRC.15).
End of enumeration elements list.
DTMCHSEL : DTM Channel Select.
bits : 24 - 25 (2 bit)
access : read-only
Enumeration:
0 : CH_A
Select DTMn channel A for this state.
1 : CH_B
Select DTMn channel B for this state.
2 : CH_C
Select DTMn channel C for this state.
3 : CH_D
Select DTMn channel D for this state.
End of enumeration elements list.
INHSPOL : Inhibit Signal Polarity.
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : ACTIVE_LOW
A logic low on the pin selected by INHSEL will allow the DTM to proceed.
1 : ACTIVE_HIGH
A logic high on the pin selected by INHSEL will allow the DTM to proceed.
End of enumeration elements list.
DTMINH : Module Inhibit Enable.
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : INACTIVE
The DTM module does not ignore any DMA requests.
1 : ACTIVE
The DTM module ignores all DMA requests until the inhibit signal selected by INHSSEL matches the polarity polarity set by INHSPOL.
End of enumeration elements list.
MSTDECEN : Master Decrement Enable.
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : DISABLED
Disable master counter decrements.
1 : ENABLED
Enable master counter decrements.
End of enumeration elements list.
TOERRIEN : Timeout Enable.
bits : 29 - 29 (1 bit)
access : read-only
Enumeration:
0 : DISABLED
Disable timeouts and timeout interrupts.
1 : ENABLED
Enable timeouts and timeout interrupts.
End of enumeration elements list.
SECSTIEN : Secondary State Transition Interrupt Enable.
bits : 30 - 30 (1 bit)
access : read-only
Enumeration:
0 : DISABLED
Disable secondary state transition interrupts.
1 : ENABLED
Enable secondary state transition interrupts.
End of enumeration elements list.
PRISTIEN : Primary State Transition Interrupt Enable.
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : DISABLED
Disable primary state transition interrupts.
1 : ENABLED
Enable primary state transition interrupts.
End of enumeration elements list.
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