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USB_0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xFFC byte (0x0)
mem_usage : registers
protection : not protected

Registers

FADDR

POWER

IOINT

TCONTROL

CMINT

CLKSEL

OSCCONTROL

AFADJUST

FADJUST

IOINTE

DMAFIFO

DMACONTROL

CMINTEPE

CRCONTROL

FRAME

EP0CONTROL

EP0COUNT

EP0FIFO

EPMPSIZE_1

EPCONTROL_1

EPCOUNT_1

EPFIFO_1

EPMPSIZE_2

EPCONTROL_2

EPCOUNT_2

EPFIFO_2

EPMPSIZE_3

EPCONTROL_3

EPCOUNT_3

EPFIFO_3

EPMPSIZE_4

EPCONTROL_4

EPCOUNT_4

EPFIFO_4


FADDR

Function Address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FADDR FADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADDR FADDRUPD

FADDR : Function Address.
bits : 0 - 6 (7 bit)

FADDRUPD : Function Address Update.
bits : 7 - 7 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The last address written to FADDR is in effect.

1 : SET

The last address written to FADDR is not yet in effect.

End of enumeration elements list.


POWER

Power Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER POWER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSDEN SUSMDF RESUME RSTDETF USBINH DITHEN ISOUPDMD

SUSDEN : Suspend Detection Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable suspend detection. The USB module will ignore suspend signaling on the bus.

1 : ENABLED

Enable suspend detection. The USB module will enter suspend mode if it detects suspend signalling on the bus.

End of enumeration elements list.

SUSMDF : Suspend Mode Flag.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The USB module is not in suspend mode.

1 : SET

The USB module is in suspend mode.

End of enumeration elements list.

RESUME : Force Resume.
bits : 2 - 2 (1 bit)

Enumeration:

0 : STOP

None

1 : GENERATE

None

End of enumeration elements list.

RSTDETF : Reset Detect Flag.
bits : 3 - 3 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

Reset signaling is not present on the bus.

1 : SET

Reset signaling detected on the bus.

End of enumeration elements list.

USBINH : USB Inhibit.
bits : 4 - 4 (1 bit)

Enumeration:

0 : INACTIVE

Enable the USB module.

1 : ACTIVE

USB module inhibited. All USB traffic is ignored.

End of enumeration elements list.

DITHEN : USB Dither Enable.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

Disable automatic USB dithering.

1 : ENABLED

Enable automatic USB dithering.

End of enumeration elements list.

ISOUPDMD : ISO Update Mode.
bits : 7 - 7 (1 bit)

Enumeration:

0 : SEND_ON_IN

When software writes IPRDYI = 1, USB will send the packet when the next IN token is received.

1 : SEND_ON_SOF

When software writes IPRDYI = 1, USB will wait for a SOF token before sending the packet. If an IN token is received before a SOF token, USB will send a zero-length data packet.

End of enumeration elements list.


IOINT

IN/OUT Endpoint Interrupt Flags
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOINT IOINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0I IN1I IN2I IN3I IN4I OUT1I OUT2I OUT3I OUT4I

EP0I : Endpoint 0 Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

Read: Endpoint 0 interrupt has not occurred. Write: No effect.

1 : SET

Read: Endpoint 0 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

IN1I : IN Endpoint 1 Interrupt Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

Read: IN Endpoint 1 interrupt has not occurred. Write: No effect.

1 : SET

Read: IN Endpoint 1 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

IN2I : IN Endpoint 2 Interrupt Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Read: IN Endpoint 2 interrupt has not occurred. Write: No effect.

1 : SET

Read: IN Endpoint 2 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

IN3I : IN Endpoint 3 Interrupt Flag.
bits : 3 - 3 (1 bit)

Enumeration:

0 : NOT_SET

Read: IN Endpoint 3 interrupt has not occurred. Write: No effect.

1 : SET

Read: IN Endpoint 3 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

IN4I : IN Endpoint 4 Interrupt Flag.
bits : 4 - 4 (1 bit)

Enumeration:

0 : NOT_SET

Read: IN Endpoint 4 interrupt has not occurred. Write: No effect.

1 : SET

Read: IN Endpoint 4 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

OUT1I : OUT Endpoint 1 Interrupt Flag.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NOT_SET

Read: OUT Endpoint 1 interrupt has not occurred. Write: No effect.

1 : SET

Read: OUT Endpoint 1 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

OUT2I : OUT Endpoint 2 Interrupt Flag.
bits : 18 - 18 (1 bit)

Enumeration:

0 : NOT_SET

Read: OUT Endpoint 2 interrupt has not occurred. Write: No effect.

1 : SET

Read: OUT Endpoint 2 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

OUT3I : OUT Endpoint 3 Interrupt Flag.
bits : 19 - 19 (1 bit)

Enumeration:

0 : NOT_SET

Read: OUT Endpoint 3 interrupt has not occurred. Write: No effect.

1 : SET

Read: OUT Endpoint 3 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

OUT4I : OUT Endpoint 4 Interrupt Flag.
bits : 20 - 20 (1 bit)

Enumeration:

0 : NOT_SET

Read: OUT Endpoint 4 interrupt has not occurred. Write: No effect.

1 : SET

Read: OUT Endpoint 4 interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.


TCONTROL

Transceiver Control
address_offset : 0x200 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCONTROL TCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DN DP DFREC PHYTST SSEL PHYEN PUEN

DN : D- Signal State.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : LOGIC_0

D- signal currently at logic 0.

1 : LOGIC_1

D- signal currently at logic 1.

End of enumeration elements list.

DP : D+ Signal State.
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

0 : LOGIC_0

D+ signal currently at logic 0.

1 : LOGIC_1

D+ signal currently at logic 1.

End of enumeration elements list.

DFREC : Differential Receiver State.
bits : 2 - 2 (1 bit)
access : read-only

Enumeration:

0 : DIFF_0

Differential 0 signalling is present on the bus.

1 : DIFF_1

Differential 1 signalling is present on the bus.

End of enumeration elements list.

PHYTST : Physical Layer Test.
bits : 3 - 4 (2 bit)

Enumeration:

0 : MODE0

Mode 0: Normal (non-test mode) (D+ = X, D- = X).

1 : MODE1

Mode 1: Differential 1 Forced (D+ = 1, D- = 0).

2 : MODE2

Mode 2: Differential 0 Forced (D+ = 0, D- = 1).

3 : MODE3

Mode 3: Single-Ended 0 Forced (D+ = 0, D- = 0).

End of enumeration elements list.

SSEL : USB Speed Select.
bits : 5 - 5 (1 bit)

Enumeration:

0 : LOW_SPEED

USB operates as a Low Speed device. If enabled, the internal pull-up resistor appears on the D- line.

1 : FULL_SPEED

USB operates as a Full Speed device. If enabled, the internal pull-up resistor appears on the D+ line.

End of enumeration elements list.

PHYEN : Physical Layer Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable the USB physical layer Transceiver (suspend).

1 : ENABLED

Enable the USB physical layer Transceiver (normal).

End of enumeration elements list.

PUEN : Internal Pull-up Resistor Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable the internal pull-up resistor (device effectively detached from the USB network).

1 : ENABLED

Enable the internal pull-up resistor when VBUS is present (device is attached to the USB network).

End of enumeration elements list.


CMINT

Common Interrupt Flags
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMINT CMINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSI RESI RSTI SOFI

SUSI : Suspend Interrupt Flag.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

Read: Suspend interrupt has not occurred. Write: No effect.

1 : SET

Read: Suspend interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

RESI : Resume Interrupt Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

Read: Resume interrupt has not occurred. Write: No effect.

1 : SET

Read: Resume interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

RSTI : Reset Interrupt Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Read: Reset interrupt has not occurred. Write: No effect.

1 : SET

Read: Reset interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.

SOFI : Start of Frame Interrupt Flag.
bits : 3 - 3 (1 bit)

Enumeration:

0 : NOT_SET

Read: SOF interrupt has not occurred. Write: No effect.

1 : SET

Read: SOF interrupt occurred. Write: Clear the interrupt.

End of enumeration elements list.


CLKSEL

Module Clock Select
address_offset : 0x300 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSEL CLKSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL CLKDIV RESET

CLKSEL : USB Clock Select.
bits : 0 - 1 (2 bit)

Enumeration:

0 : USBNOSC

Select the USB Oscillator as the USB clock.

1 : PLLNOSC

Select the PLL output as the USB clock.

2 : EXTOSCN

Select the External Oscillator output (EXTOSCn) as the USB clock.

End of enumeration elements list.

CLKDIV : USB Clock Divider.
bits : 4 - 5 (2 bit)

Enumeration:

0 : DIV1

The USB module uses the selected input clock divided by 1.

1 : DIV2

The USB module uses the selected input clock divided by 2.

2 : DIV4

The USB module uses the selected input clock divided by 4.

3 : DIV8

The USB module uses the selected input clock divided by 8.

End of enumeration elements list.

RESET : USB Reset.
bits : 6 - 6 (1 bit)
access : write-only

Enumeration:

0 : NOT_SET

Do not reset the USB module.

1 : SET

Reset the USB module.

End of enumeration elements list.


OSCCONTROL

Oscillator Control
address_offset : 0x310 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OSCCONTROL OSCCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEND OSCEN

SUSPEND : USB Oscillator Suspend.
bits : 5 - 5 (1 bit)

Enumeration:

0 : DISABLED

The USB oscillator is not suspended.

1 : ENABLED

Suspend the USB oscillator.

End of enumeration elements list.

OSCEN : USB Oscillator Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable the USB oscillator.

1 : ENABLED

Enable the USB oscillator.

End of enumeration elements list.


AFADJUST

Oscillator Additional Frequency Adjust
address_offset : 0x320 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFADJUST AFADJUST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FINEFADJ DITHEN

FINEFADJ : USB Oscillator Fine Output Frequency Adjust.
bits : 0 - 5 (6 bit)

DITHEN : USB Oscillator Dithering Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Disable USB oscillator dithering.

1 : ENABLED

Enable USB oscillator dithering.

End of enumeration elements list.


FADJUST

Oscillator Frequency Adjust
address_offset : 0x330 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FADJUST FADJUST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FADJ

FADJ : Oscillator Output Frequency Adjust.
bits : 0 - 6 (7 bit)


IOINTE

IN/OUT Endpoint Interrupt Control
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOINTE IOINTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0IEN IN1IEN IN2IEN IN3IEN IN4IEN OUT1IEN OUT2IEN OUT3IEN OUT4IEN

EP0IEN : Endpoint 0 Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable the Endpoint 0 interrupt.

1 : ENABLED

Enable the Endpoint 0 interrupt.

End of enumeration elements list.

IN1IEN : IN Endpoint 1 Interrupt Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Disable the IN Endpoint 1 interrupt.

1 : ENABLED

Enable the IN Endpoint 1 interrupt.

End of enumeration elements list.

IN2IEN : IN Endpoint 2 Interrupt Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable the IN Endpoint 2 interrupt.

1 : ENABLED

Enable the IN Endpoint 2 interrupt.

End of enumeration elements list.

IN3IEN : IN Endpoint 3 Interrupt Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : DISABLED

Disable the IN Endpoint 3 interrupt.

1 : ENABLED

Enable the IN Endpoint 3 interrupt.

End of enumeration elements list.

IN4IEN : IN Endpoint 4 Interrupt Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

Disable the IN Endpoint 4 interrupt.

1 : ENABLED

Enable the IN Endpoint 4 interrupt.

End of enumeration elements list.

OUT1IEN : OUT Endpoint 1 Interrupt Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DISABLED

Disable the OUT Endpoint 1 interrupt.

1 : ENABLED

Enable the OUT Endpoint 1 interrupt.

End of enumeration elements list.

OUT2IEN : OUT Endpoint 2 Interrupt Enable.
bits : 18 - 18 (1 bit)

Enumeration:

0 : DISABLED

Disable the OUT Endpoint 2 interrupt.

1 : ENABLED

Enable the OUT Endpoint 2 interrupt.

End of enumeration elements list.

OUT3IEN : OUT Endpoint 3 Interrupt Enable.
bits : 19 - 19 (1 bit)

Enumeration:

0 : DISABLED

Disable the OUT Endpoint 3 interrupt.

1 : ENABLED

Enable the OUT Endpoint 3 interrupt.

End of enumeration elements list.

OUT4IEN : OUT Endpoint 4 Interrupt Enable.
bits : 20 - 20 (1 bit)

Enumeration:

0 : DISABLED

Disable the OUT Endpoint 4 interrupt.

1 : ENABLED

Enable the OUT Endpoint 4 interrupt.

End of enumeration elements list.


DMAFIFO

DMA Data FIFO Access
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAFIFO DMAFIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAFIFO

DMAFIFO : DMA Data FIFO Access.
bits : 0 - 31 (32 bit)


DMACONTROL

DMA Control
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACONTROL DMACONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGMD TERRF DBUSYF DFIFOFL

DBGMD : USB DMA Debug Mode.
bits : 4 - 4 (1 bit)

Enumeration:

0 : RUN

The USB module will continue to operate while the core is halted in debug mode.

1 : HALT

A debug breakpoint will prevent the USB DMA buffer from transferring data to and from the USB FIFOs when the core is halted.

End of enumeration elements list.

TERRF : Timeout Error Flag.
bits : 5 - 5 (1 bit)

Enumeration:

0 : NOT_SET

A timeout error has not occurred.

1 : SET

A timeout error occurred.

End of enumeration elements list.

DBUSYF : USB DMA Busy Flag.
bits : 6 - 6 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The DMA buffer is not busy.

1 : SET

The DMA buffer is busy reading or writing an 8-word packet.

End of enumeration elements list.

DFIFOFL : USB DMA Buffer Flush Control.
bits : 7 - 7 (1 bit)

Enumeration:

1 : SET

Flush the USB DMA buffer.

End of enumeration elements list.


CMINTEPE

Common Interrupt and Endpoint Control
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMINTEPE CMINTEPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSIEN RESIEN RSTIEN SOFIEN EP0EN EP1EN EP2EN EP3EN EP4EN

SUSIEN : Suspend Interrupt Enable.
bits : 0 - 0 (1 bit)

Enumeration:

0 : DISABLED

Disable the Suspend interrupt.

1 : ENABLED

Enable the Suspend interrupt.

End of enumeration elements list.

RESIEN : Resume Interrupt Enable.
bits : 1 - 1 (1 bit)

Enumeration:

0 : DISABLED

Disable the Resume interrupt.

1 : ENABLED

Enable the Resume interrupt.

End of enumeration elements list.

RSTIEN : Reset Interrupt Enable.
bits : 2 - 2 (1 bit)

Enumeration:

0 : DISABLED

Disable the Reset interrupt.

1 : ENABLED

Enable the Reset interrupt.

End of enumeration elements list.

SOFIEN : Start of Frame Interrupt Enable.
bits : 3 - 3 (1 bit)

Enumeration:

0 : DISABLED

Disable the SOF interrupt.

1 : ENABLED

Enable the SOF interrupt.

End of enumeration elements list.

EP0EN : Endpoint 0 Enable.
bits : 16 - 16 (1 bit)

Enumeration:

0 : DISABLED

Disable Endpoint 0 (no NACK, ACK, or STALL on the USB network).

1 : ENABLED

Enable Endpoint 0 (normal).

End of enumeration elements list.

EP1EN : Endpoint 1 Enable.
bits : 17 - 17 (1 bit)

Enumeration:

0 : DISABLED

Disable Endpoint 1 (no NACK, ACK, or STALL on the USB network).

1 : ENABLED

Enable Endpoint 1 (normal).

End of enumeration elements list.

EP2EN : Endpoint 2 Enable.
bits : 18 - 18 (1 bit)

Enumeration:

0 : DISABLED

Disable Endpoint 2 (no NACK, ACK, or STALL on the USB network).

1 : ENABLED

Enable Endpoint 2 (normal).

End of enumeration elements list.

EP3EN : Endpoint 3 Enable.
bits : 19 - 19 (1 bit)

Enumeration:

0 : DISABLED

Disable Endpoint 3 (no NACK, ACK, or STALL on the USB network).

1 : ENABLED

Enable Endpoint 3 (normal).

End of enumeration elements list.

EP4EN : Endpoint 4 Enable.
bits : 20 - 20 (1 bit)

Enumeration:

0 : DISABLED

Disable Endpoint 4 (no NACK, ACK, or STALL on the USB network).

1 : ENABLED

Enable Endpoint 4 (normal).

End of enumeration elements list.


CRCONTROL

Clock Recovery Control
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCONTROL CRCONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OLEN LSCRMD CRSSEN CREN

OLEN : Oscillator Open-Loop Mode Enable.
bits : 4 - 4 (1 bit)

Enumeration:

0 : DISABLED

Do not freeze the USB oscillator output frequency (closed loop mode).

1 : ENABLED

Freeze the USB oscillator output frequency (open loop mode).

End of enumeration elements list.

LSCRMD : Low Speed Clock Recovery Mode.
bits : 5 - 5 (1 bit)

Enumeration:

0 : FULL_SPEED

Full Speed Mode.

1 : LOW_SPEED

Low Speed Mode.

End of enumeration elements list.

CRSSEN : Clock Recovery Single Step Enable.
bits : 6 - 6 (1 bit)

Enumeration:

0 : DISABLED

Normal calibration mode.

1 : ENABLED

Single step mode.

End of enumeration elements list.

CREN : Clock Recovery Enable.
bits : 7 - 7 (1 bit)

Enumeration:

0 : DISABLED

Disable clock recovery.

1 : ENABLED

Enable clock recovery.

End of enumeration elements list.


FRAME

Frame Number
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAME FRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAMENUM

FRAMENUM : Frame Number.
bits : 0 - 10 (11 bit)
access : read-only


EP0CONTROL

Endpoint 0 Control
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0CONTROL EP0CONTROL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPRDYI IPRDYI STSTLI DEND SUENDI SDSTL OPRDYIS SUENDIS

OPRDYI : OUT Packet Ready Interrupt Flag.
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

A packet is not available.

1 : SET

A packet is available.

End of enumeration elements list.

IPRDYI : IN Packet Ready Indicator.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

A packet is not ready for transmission to host.

1 : SET

A packet is ready for transmission to host.

End of enumeration elements list.

STSTLI : Sent Stall Interrupt Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Read: A STALL handshake has not been sent or is cleared. Write: Clear the interrupt.

1 : SET

Read: STALL handshake sent. Write: No effect.

End of enumeration elements list.

DEND : Data End.
bits : 3 - 3 (1 bit)

Enumeration:

0 : NOT_SET

The current packet is not the last packet of the transfer.

1 : SET

The current packet is the last packet of the transfer.

End of enumeration elements list.

SUENDI : Setup End Interrupt Flag.
bits : 4 - 4 (1 bit)
access : read-only

Enumeration:

0 : NOT_SET

The current packet is not the last packet of setup.

1 : SET

The current packet is the last packet of setup.

End of enumeration elements list.

SDSTL : Send Stall.
bits : 5 - 5 (1 bit)

Enumeration:

0 : NOT_SET

The STALL handshake has been transmitted or not triggered.

1 : SET

Initiate a STALL condition.

End of enumeration elements list.

OPRDYIS : Serviced Out Packet Ready Interrupt Flag.
bits : 6 - 6 (1 bit)

Enumeration:

0 : NOT_SET

The out packet has not been processed.

1 : SET

The out packet has been received and accepted.

End of enumeration elements list.

SUENDIS : Serviced Setup End Interrupt Flag.
bits : 7 - 7 (1 bit)

Enumeration:

0 : NOT_SET

Setup end has not been serviced.

1 : SET

Setup end has been serviced.

End of enumeration elements list.


EP0COUNT

Endpoint 0 Data Count
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0COUNT EP0COUNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Endpoint 0 OUT Data Count.
bits : 0 - 6 (7 bit)
access : read-only


EP0FIFO

Endpoint 0 Data FIFO Access
address_offset : 0x830 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP0FIFO EP0FIFO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO

FIFO : Endpoint 0 Data FIFO.
bits : 0 - 31 (32 bit)


EPMPSIZE_1

Endpoint Maximum Packet Size
address_offset : 0x880 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPMPSIZE_1 EPMPSIZE_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMAXP OMAXP

IMAXP : IN Maximum Packet Size.
bits : 0 - 7 (8 bit)

OMAXP : OUT Maximum Packet Size.
bits : 16 - 23 (8 bit)


EPCONTROL_1

Endpoint Control
address_offset : 0x890 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCONTROL_1 EPCONTROL_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPRDYI IFIFONEF IURF IFIFOFL ISDSTL ISTSTLI ICLRDT SPLITEN FDTEN IDMAEN DIRSEL IISOEN AUTOSETEN OPRDYI OFIFOFF OORF ODERRF OFIFOFL OSDSTL OSTSTLI OCLRDT ODMAMD ODMAEN OISOEN AUTOCLREN

IPRDYI : IN Packet Ready Indicator.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

The packet has been sent or there is an open FIFO slot.

1 : SET

A packet is loaded in the FIFO.

End of enumeration elements list.

IFIFONEF : IN FIFO Not Empty Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

The IN Endpoint FIFO is empty.

1 : SET

The IN Endpoint FIFO contains one or more packets.

End of enumeration elements list.

IURF : IN FIFO Underrun Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Underrun has not occurred.

1 : SET

Underrun occurred.

End of enumeration elements list.

IFIFOFL : IN FIFO Flush.
bits : 3 - 3 (1 bit)

Enumeration:

1 : SET

Flush the IN FIFO.

End of enumeration elements list.

ISDSTL : IN Send Stall.
bits : 4 - 4 (1 bit)

Enumeration:

0 : NOT_SET

Stop sending a stall.

1 : SET

Generate a stall.

End of enumeration elements list.

ISTSTLI : IN Sent Stall Interrupt Flag.
bits : 5 - 5 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

ICLRDT : IN Clear Data Toggle.
bits : 6 - 6 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the IN data toggle.

1 : RESET

Reset the IN data toggle.

End of enumeration elements list.

SPLITEN : FIFO Split Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Do not split the endpoint FIFO.

1 : ENABLED

Split the endpoint FIFO.

End of enumeration elements list.

FDTEN : Force Data Toggle Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

The endpoint data toggle switches only when an ACK is received following a data packet transmission.

1 : ENABLED

The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.

End of enumeration elements list.

IDMAEN : IN Endpoint DMA Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the IN endpoint.

1 : ENABLED

Enable the DMA request for the IN endpoint.

End of enumeration elements list.

DIRSEL : Endpoint Direction Select.
bits : 13 - 13 (1 bit)

Enumeration:

0 : OUT

Select the endpoint direction as OUT.

1 : IN

Select the endpoint direction as IN.

End of enumeration elements list.

IISOEN : IN Isochronous Transfer Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOSETEN : IN Endpoint IPRDYI Automatic Set Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

The IPRDYI bit is not automatically set by hardware.

1 : ENABLED

The IPRDYI bit is automatically set by hardware.

End of enumeration elements list.

OPRDYI : OUT Packet Ready.
bits : 16 - 16 (1 bit)

Enumeration:

0 : NOT_SET

A data packet is not available.

1 : SET

A data packet is available.

End of enumeration elements list.

OFIFOFF : OUT FIFO Full.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NOT_SET

The OUT endpoint FIFO is not full.

1 : SET

The OUT endpoint FIFO is full.

End of enumeration elements list.

OORF : OUT FIFO Overrun Flag.
bits : 18 - 18 (1 bit)

Enumeration:

0 : NOT_SET

No data overrun.

1 : SET

A data packet was lost because of a full FIFO since this flag was last cleared.

End of enumeration elements list.

ODERRF : OUT Data Error Flag.
bits : 19 - 19 (1 bit)

Enumeration:

0 : NOT_SET

A CRC or bit-stuff error has not occurred.

1 : SET

A CRC or bit-stuff error occurred.

End of enumeration elements list.

OFIFOFL : OUT FIFO Flush.
bits : 20 - 20 (1 bit)

Enumeration:

1 : SET

Flush the OUT FIFO.

End of enumeration elements list.

OSDSTL : OUT Send Stall.
bits : 21 - 21 (1 bit)

Enumeration:

0 : STOP

Stop sending a stall.

1 : SEND

Generate a stall.

End of enumeration elements list.

OSTSTLI : OUT Sent Stall Interrupt Flag.
bits : 22 - 22 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

OCLRDT : OUT Clear Data Toggle.
bits : 23 - 23 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the OUT data toggle.

1 : RESET

Reset the OUT data toggle.

End of enumeration elements list.

ODMAMD : OUT Endpoint DMA Mode.
bits : 28 - 28 (1 bit)

Enumeration:

0 : AUTO_DMA

Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.

1 : NO_DMA

No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.

End of enumeration elements list.

ODMAEN : OUT Endpoint DMA Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the OUT endpoint.

1 : ENABLED

Enable the DMA request for the OUT endpoint.

End of enumeration elements list.

OISOEN : OUT Isochronous Transfer Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOCLREN : OUT Endpoint OPRDYI Auto-Clear Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

The OPRDYI bit is not automatically cleared by hardware.

1 : ENABLED

The OPRDYI bit is automatically cleared by hardware.

End of enumeration elements list.


EPCOUNT_1

Endpoint Data Count
address_offset : 0x8A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCOUNT_1 EPCOUNT_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Endpoint OUT Data Count.
bits : 0 - 9 (10 bit)
access : read-only


EPFIFO_1

Endpoint Data FIFO Access
address_offset : 0x8B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFIFO_1 EPFIFO_1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO

FIFO : Endpoint Data FIFO.
bits : 0 - 31 (32 bit)


EPMPSIZE_2

Endpoint Maximum Packet Size
address_offset : 0x900 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPMPSIZE_2 EPMPSIZE_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMAXP OMAXP

IMAXP : IN Maximum Packet Size.
bits : 0 - 7 (8 bit)

OMAXP : OUT Maximum Packet Size.
bits : 16 - 23 (8 bit)


EPCONTROL_2

Endpoint Control
address_offset : 0x910 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCONTROL_2 EPCONTROL_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPRDYI IFIFONEF IURF IFIFOFL ISDSTL ISTSTLI ICLRDT SPLITEN FDTEN IDMAEN DIRSEL IISOEN AUTOSETEN OPRDYI OFIFOFF OORF ODERRF OFIFOFL OSDSTL OSTSTLI OCLRDT ODMAMD ODMAEN OISOEN AUTOCLREN

IPRDYI : IN Packet Ready Indicator.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

The packet has been sent or there is an open FIFO slot.

1 : SET

A packet is loaded in the FIFO.

End of enumeration elements list.

IFIFONEF : IN FIFO Not Empty Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

The IN Endpoint FIFO is empty.

1 : SET

The IN Endpoint FIFO contains one or more packets.

End of enumeration elements list.

IURF : IN FIFO Underrun Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Underrun has not occurred.

1 : SET

Underrun occurred.

End of enumeration elements list.

IFIFOFL : IN FIFO Flush.
bits : 3 - 3 (1 bit)

Enumeration:

1 : SET

Flush the IN FIFO.

End of enumeration elements list.

ISDSTL : IN Send Stall.
bits : 4 - 4 (1 bit)

Enumeration:

0 : NOT_SET

Stop sending a stall.

1 : SET

Generate a stall.

End of enumeration elements list.

ISTSTLI : IN Sent Stall Interrupt Flag.
bits : 5 - 5 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

ICLRDT : IN Clear Data Toggle.
bits : 6 - 6 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the IN data toggle.

1 : RESET

Reset the IN data toggle.

End of enumeration elements list.

SPLITEN : FIFO Split Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Do not split the endpoint FIFO.

1 : ENABLED

Split the endpoint FIFO.

End of enumeration elements list.

FDTEN : Force Data Toggle Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

The endpoint data toggle switches only when an ACK is received following a data packet transmission.

1 : ENABLED

The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.

End of enumeration elements list.

IDMAEN : IN Endpoint DMA Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the IN endpoint.

1 : ENABLED

Enable the DMA request for the IN endpoint.

End of enumeration elements list.

DIRSEL : Endpoint Direction Select.
bits : 13 - 13 (1 bit)

Enumeration:

0 : OUT

Select the endpoint direction as OUT.

1 : IN

Select the endpoint direction as IN.

End of enumeration elements list.

IISOEN : IN Isochronous Transfer Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOSETEN : IN Endpoint IPRDYI Automatic Set Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

The IPRDYI bit is not automatically set by hardware.

1 : ENABLED

The IPRDYI bit is automatically set by hardware.

End of enumeration elements list.

OPRDYI : OUT Packet Ready.
bits : 16 - 16 (1 bit)

Enumeration:

0 : NOT_SET

A data packet is not available.

1 : SET

A data packet is available.

End of enumeration elements list.

OFIFOFF : OUT FIFO Full.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NOT_SET

The OUT endpoint FIFO is not full.

1 : SET

The OUT endpoint FIFO is full.

End of enumeration elements list.

OORF : OUT FIFO Overrun Flag.
bits : 18 - 18 (1 bit)

Enumeration:

0 : NOT_SET

No data overrun.

1 : SET

A data packet was lost because of a full FIFO since this flag was last cleared.

End of enumeration elements list.

ODERRF : OUT Data Error Flag.
bits : 19 - 19 (1 bit)

Enumeration:

0 : NOT_SET

A CRC or bit-stuff error has not occurred.

1 : SET

A CRC or bit-stuff error occurred.

End of enumeration elements list.

OFIFOFL : OUT FIFO Flush.
bits : 20 - 20 (1 bit)

Enumeration:

1 : SET

Flush the OUT FIFO.

End of enumeration elements list.

OSDSTL : OUT Send Stall.
bits : 21 - 21 (1 bit)

Enumeration:

0 : STOP

Stop sending a stall.

1 : SEND

Generate a stall.

End of enumeration elements list.

OSTSTLI : OUT Sent Stall Interrupt Flag.
bits : 22 - 22 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

OCLRDT : OUT Clear Data Toggle.
bits : 23 - 23 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the OUT data toggle.

1 : RESET

Reset the OUT data toggle.

End of enumeration elements list.

ODMAMD : OUT Endpoint DMA Mode.
bits : 28 - 28 (1 bit)

Enumeration:

0 : AUTO_DMA

Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.

1 : NO_DMA

No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.

End of enumeration elements list.

ODMAEN : OUT Endpoint DMA Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the OUT endpoint.

1 : ENABLED

Enable the DMA request for the OUT endpoint.

End of enumeration elements list.

OISOEN : OUT Isochronous Transfer Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOCLREN : OUT Endpoint OPRDYI Auto-Clear Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

The OPRDYI bit is not automatically cleared by hardware.

1 : ENABLED

The OPRDYI bit is automatically cleared by hardware.

End of enumeration elements list.


EPCOUNT_2

Endpoint Data Count
address_offset : 0x920 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCOUNT_2 EPCOUNT_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Endpoint OUT Data Count.
bits : 0 - 9 (10 bit)
access : read-only


EPFIFO_2

Endpoint Data FIFO Access
address_offset : 0x930 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFIFO_2 EPFIFO_2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO

FIFO : Endpoint Data FIFO.
bits : 0 - 31 (32 bit)


EPMPSIZE_3

Endpoint Maximum Packet Size
address_offset : 0x980 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPMPSIZE_3 EPMPSIZE_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMAXP OMAXP

IMAXP : IN Maximum Packet Size.
bits : 0 - 7 (8 bit)

OMAXP : OUT Maximum Packet Size.
bits : 16 - 23 (8 bit)


EPCONTROL_3

Endpoint Control
address_offset : 0x990 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCONTROL_3 EPCONTROL_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPRDYI IFIFONEF IURF IFIFOFL ISDSTL ISTSTLI ICLRDT SPLITEN FDTEN IDMAEN DIRSEL IISOEN AUTOSETEN OPRDYI OFIFOFF OORF ODERRF OFIFOFL OSDSTL OSTSTLI OCLRDT ODMAMD ODMAEN OISOEN AUTOCLREN

IPRDYI : IN Packet Ready Indicator.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

The packet has been sent or there is an open FIFO slot.

1 : SET

A packet is loaded in the FIFO.

End of enumeration elements list.

IFIFONEF : IN FIFO Not Empty Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

The IN Endpoint FIFO is empty.

1 : SET

The IN Endpoint FIFO contains one or more packets.

End of enumeration elements list.

IURF : IN FIFO Underrun Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Underrun has not occurred.

1 : SET

Underrun occurred.

End of enumeration elements list.

IFIFOFL : IN FIFO Flush.
bits : 3 - 3 (1 bit)

Enumeration:

1 : SET

Flush the IN FIFO.

End of enumeration elements list.

ISDSTL : IN Send Stall.
bits : 4 - 4 (1 bit)

Enumeration:

0 : NOT_SET

Stop sending a stall.

1 : SET

Generate a stall.

End of enumeration elements list.

ISTSTLI : IN Sent Stall Interrupt Flag.
bits : 5 - 5 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

ICLRDT : IN Clear Data Toggle.
bits : 6 - 6 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the IN data toggle.

1 : RESET

Reset the IN data toggle.

End of enumeration elements list.

SPLITEN : FIFO Split Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Do not split the endpoint FIFO.

1 : ENABLED

Split the endpoint FIFO.

End of enumeration elements list.

FDTEN : Force Data Toggle Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

The endpoint data toggle switches only when an ACK is received following a data packet transmission.

1 : ENABLED

The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.

End of enumeration elements list.

IDMAEN : IN Endpoint DMA Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the IN endpoint.

1 : ENABLED

Enable the DMA request for the IN endpoint.

End of enumeration elements list.

DIRSEL : Endpoint Direction Select.
bits : 13 - 13 (1 bit)

Enumeration:

0 : OUT

Select the endpoint direction as OUT.

1 : IN

Select the endpoint direction as IN.

End of enumeration elements list.

IISOEN : IN Isochronous Transfer Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOSETEN : IN Endpoint IPRDYI Automatic Set Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

The IPRDYI bit is not automatically set by hardware.

1 : ENABLED

The IPRDYI bit is automatically set by hardware.

End of enumeration elements list.

OPRDYI : OUT Packet Ready.
bits : 16 - 16 (1 bit)

Enumeration:

0 : NOT_SET

A data packet is not available.

1 : SET

A data packet is available.

End of enumeration elements list.

OFIFOFF : OUT FIFO Full.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NOT_SET

The OUT endpoint FIFO is not full.

1 : SET

The OUT endpoint FIFO is full.

End of enumeration elements list.

OORF : OUT FIFO Overrun Flag.
bits : 18 - 18 (1 bit)

Enumeration:

0 : NOT_SET

No data overrun.

1 : SET

A data packet was lost because of a full FIFO since this flag was last cleared.

End of enumeration elements list.

ODERRF : OUT Data Error Flag.
bits : 19 - 19 (1 bit)

Enumeration:

0 : NOT_SET

A CRC or bit-stuff error has not occurred.

1 : SET

A CRC or bit-stuff error occurred.

End of enumeration elements list.

OFIFOFL : OUT FIFO Flush.
bits : 20 - 20 (1 bit)

Enumeration:

1 : SET

Flush the OUT FIFO.

End of enumeration elements list.

OSDSTL : OUT Send Stall.
bits : 21 - 21 (1 bit)

Enumeration:

0 : STOP

Stop sending a stall.

1 : SEND

Generate a stall.

End of enumeration elements list.

OSTSTLI : OUT Sent Stall Interrupt Flag.
bits : 22 - 22 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

OCLRDT : OUT Clear Data Toggle.
bits : 23 - 23 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the OUT data toggle.

1 : RESET

Reset the OUT data toggle.

End of enumeration elements list.

ODMAMD : OUT Endpoint DMA Mode.
bits : 28 - 28 (1 bit)

Enumeration:

0 : AUTO_DMA

Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.

1 : NO_DMA

No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.

End of enumeration elements list.

ODMAEN : OUT Endpoint DMA Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the OUT endpoint.

1 : ENABLED

Enable the DMA request for the OUT endpoint.

End of enumeration elements list.

OISOEN : OUT Isochronous Transfer Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOCLREN : OUT Endpoint OPRDYI Auto-Clear Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

The OPRDYI bit is not automatically cleared by hardware.

1 : ENABLED

The OPRDYI bit is automatically cleared by hardware.

End of enumeration elements list.


EPCOUNT_3

Endpoint Data Count
address_offset : 0x9A0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCOUNT_3 EPCOUNT_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Endpoint OUT Data Count.
bits : 0 - 9 (10 bit)
access : read-only


EPFIFO_3

Endpoint Data FIFO Access
address_offset : 0x9B0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFIFO_3 EPFIFO_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO

FIFO : Endpoint Data FIFO.
bits : 0 - 31 (32 bit)


EPMPSIZE_4

Endpoint Maximum Packet Size
address_offset : 0xA00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPMPSIZE_4 EPMPSIZE_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMAXP OMAXP

IMAXP : IN Maximum Packet Size.
bits : 0 - 7 (8 bit)

OMAXP : OUT Maximum Packet Size.
bits : 16 - 23 (8 bit)


EPCONTROL_4

Endpoint Control
address_offset : 0xA10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCONTROL_4 EPCONTROL_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IPRDYI IFIFONEF IURF IFIFOFL ISDSTL ISTSTLI ICLRDT SPLITEN FDTEN IDMAEN DIRSEL IISOEN AUTOSETEN OPRDYI OFIFOFF OORF ODERRF OFIFOFL OSDSTL OSTSTLI OCLRDT ODMAMD ODMAEN OISOEN AUTOCLREN

IPRDYI : IN Packet Ready Indicator.
bits : 0 - 0 (1 bit)

Enumeration:

0 : NOT_SET

The packet has been sent or there is an open FIFO slot.

1 : SET

A packet is loaded in the FIFO.

End of enumeration elements list.

IFIFONEF : IN FIFO Not Empty Flag.
bits : 1 - 1 (1 bit)

Enumeration:

0 : NOT_SET

The IN Endpoint FIFO is empty.

1 : SET

The IN Endpoint FIFO contains one or more packets.

End of enumeration elements list.

IURF : IN FIFO Underrun Flag.
bits : 2 - 2 (1 bit)

Enumeration:

0 : NOT_SET

Underrun has not occurred.

1 : SET

Underrun occurred.

End of enumeration elements list.

IFIFOFL : IN FIFO Flush.
bits : 3 - 3 (1 bit)

Enumeration:

1 : SET

Flush the IN FIFO.

End of enumeration elements list.

ISDSTL : IN Send Stall.
bits : 4 - 4 (1 bit)

Enumeration:

0 : NOT_SET

Stop sending a stall.

1 : SET

Generate a stall.

End of enumeration elements list.

ISTSTLI : IN Sent Stall Interrupt Flag.
bits : 5 - 5 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

ICLRDT : IN Clear Data Toggle.
bits : 6 - 6 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the IN data toggle.

1 : RESET

Reset the IN data toggle.

End of enumeration elements list.

SPLITEN : FIFO Split Enable.
bits : 10 - 10 (1 bit)

Enumeration:

0 : DISABLED

Do not split the endpoint FIFO.

1 : ENABLED

Split the endpoint FIFO.

End of enumeration elements list.

FDTEN : Force Data Toggle Enable.
bits : 11 - 11 (1 bit)

Enumeration:

0 : DISABLED

The endpoint data toggle switches only when an ACK is received following a data packet transmission.

1 : ENABLED

The endpoint data toggle is forced to switch after every data packet is transmitted, regardless of ACK reception.

End of enumeration elements list.

IDMAEN : IN Endpoint DMA Enable.
bits : 12 - 12 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the IN endpoint.

1 : ENABLED

Enable the DMA request for the IN endpoint.

End of enumeration elements list.

DIRSEL : Endpoint Direction Select.
bits : 13 - 13 (1 bit)

Enumeration:

0 : OUT

Select the endpoint direction as OUT.

1 : IN

Select the endpoint direction as IN.

End of enumeration elements list.

IISOEN : IN Isochronous Transfer Enable.
bits : 14 - 14 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOSETEN : IN Endpoint IPRDYI Automatic Set Enable.
bits : 15 - 15 (1 bit)

Enumeration:

0 : DISABLED

The IPRDYI bit is not automatically set by hardware.

1 : ENABLED

The IPRDYI bit is automatically set by hardware.

End of enumeration elements list.

OPRDYI : OUT Packet Ready.
bits : 16 - 16 (1 bit)

Enumeration:

0 : NOT_SET

A data packet is not available.

1 : SET

A data packet is available.

End of enumeration elements list.

OFIFOFF : OUT FIFO Full.
bits : 17 - 17 (1 bit)

Enumeration:

0 : NOT_SET

The OUT endpoint FIFO is not full.

1 : SET

The OUT endpoint FIFO is full.

End of enumeration elements list.

OORF : OUT FIFO Overrun Flag.
bits : 18 - 18 (1 bit)

Enumeration:

0 : NOT_SET

No data overrun.

1 : SET

A data packet was lost because of a full FIFO since this flag was last cleared.

End of enumeration elements list.

ODERRF : OUT Data Error Flag.
bits : 19 - 19 (1 bit)

Enumeration:

0 : NOT_SET

A CRC or bit-stuff error has not occurred.

1 : SET

A CRC or bit-stuff error occurred.

End of enumeration elements list.

OFIFOFL : OUT FIFO Flush.
bits : 20 - 20 (1 bit)

Enumeration:

1 : SET

Flush the OUT FIFO.

End of enumeration elements list.

OSDSTL : OUT Send Stall.
bits : 21 - 21 (1 bit)

Enumeration:

0 : STOP

Stop sending a stall.

1 : SEND

Generate a stall.

End of enumeration elements list.

OSTSTLI : OUT Sent Stall Interrupt Flag.
bits : 22 - 22 (1 bit)

Enumeration:

0 : NOT_SET

Read: A stall condition has not been sent since this bit was last cleared. Write: Clear the interrupt.

1 : SET

Read: A stall condition has been sent since this bit was last cleared. Write: No effect.

End of enumeration elements list.

OCLRDT : OUT Clear Data Toggle.
bits : 23 - 23 (1 bit)

Enumeration:

0 : NO_RESET

Do not reset the OUT data toggle.

1 : RESET

Reset the OUT data toggle.

End of enumeration elements list.

ODMAMD : OUT Endpoint DMA Mode.
bits : 28 - 28 (1 bit)

Enumeration:

0 : AUTO_DMA

Automatic DMA service is requested on the last packet of the transfer until less than four bytes remain in the packet. At this time, an interrupt is generated. The firmware must read or write the last few bytes of the packet, if any remain.

1 : NO_DMA

No DMA service is requested on the last packet of the transfer. When the DMA recognizes the last packet, an interrupt is generated. The firmware must handle the entirety of the last packet.

End of enumeration elements list.

ODMAEN : OUT Endpoint DMA Enable.
bits : 29 - 29 (1 bit)

Enumeration:

0 : DISABLED

Disable the DMA request for the OUT endpoint.

1 : ENABLED

Enable the DMA request for the OUT endpoint.

End of enumeration elements list.

OISOEN : OUT Isochronous Transfer Enable.
bits : 30 - 30 (1 bit)

Enumeration:

0 : BULK_INT

Configure the endpoint for Bulk/Interrupt transfers.

1 : ISO

Configure the endpoint for Isochronous transfers.

End of enumeration elements list.

AUTOCLREN : OUT Endpoint OPRDYI Auto-Clear Enable.
bits : 31 - 31 (1 bit)

Enumeration:

0 : DISABLED

The OPRDYI bit is not automatically cleared by hardware.

1 : ENABLED

The OPRDYI bit is automatically cleared by hardware.

End of enumeration elements list.


EPCOUNT_4

Endpoint Data Count
address_offset : 0xA20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCOUNT_4 EPCOUNT_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT : Endpoint OUT Data Count.
bits : 0 - 9 (10 bit)
access : read-only


EPFIFO_4

Endpoint Data FIFO Access
address_offset : 0xA30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPFIFO_4 EPFIFO_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO

FIFO : Endpoint Data FIFO.
bits : 0 - 31 (32 bit)



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