\n

I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

I2C0MSA

MSA

I2C0MIMR

MIMR

I2C0MRIS

MRIS

I2C0MMIS

MMIS

I2C0MICR

MICR

I2C0MCR

MCR

I2C0MCLKOCNT

MCLKOCNT

I2C0MBMON

MBMON

I2C0MBLEN

MBLEN

I2C0MBCNT

MBCNT

I2C0MCS

MCS

I2C0MDR

MDR

I2C0SOAR

SOAR

I2C0SCSR

SCSR

I2C0SDR

SDR

I2C0SIMR

SIMR

I2C0SRIS

SRIS

I2C0SMIS

SMIS

I2C0SICR

SICR

I2C0SOAR2

SOAR2

I2C0SACKCTL

SACKCTL

I2C0MTPR

MTPR

I2C0FIFODATA

FIFODATA

I2C0FIFOCTL

FIFOCTL

I2C0FIFOSTATUS

FIFOSTATUS

I2C0PP

PP

I2C0PC

PC


I2C0MSA

I2C Master Slave Address
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MSA I2C0MSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MSA_RS I2C_MSA_SA

I2C_MSA_RS : Receive not send
bits : 0 - 0 (1 bit)

I2C_MSA_SA : I2C Slave Address
bits : 1 - 8 (8 bit)


MSA

I2C Master Slave Address
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MSA MSA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MSA_RS I2C_MSA_SA

I2C_MSA_RS : Receive not send
bits : 0 - 0 (1 bit)

I2C_MSA_SA : I2C Slave Address
bits : 1 - 8 (8 bit)


I2C0MIMR

I2C Master Interrupt Mask
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MIMR I2C0MIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MIMR_IM I2C_MIMR_CLKIM I2C_MIMR_DMARXIM I2C_MIMR_DMATXIM I2C_MIMR_NACKIM I2C_MIMR_STARTIM I2C_MIMR_STOPIM I2C_MIMR_ARBLOSTIM I2C_MIMR_TXIM I2C_MIMR_RXIM I2C_MIMR_TXFEIM I2C_MIMR_RXFFIM

I2C_MIMR_IM : Master Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_MIMR_CLKIM : Clock Timeout Interrupt Mask
bits : 1 - 2 (2 bit)

I2C_MIMR_DMARXIM : Receive DMA Interrupt Mask
bits : 2 - 4 (3 bit)

I2C_MIMR_DMATXIM : Transmit DMA Interrupt Mask
bits : 3 - 6 (4 bit)

I2C_MIMR_NACKIM : Address/Data NACK Interrupt Mask
bits : 4 - 8 (5 bit)

I2C_MIMR_STARTIM : START Detection Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_MIMR_STOPIM : STOP Detection Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_MIMR_ARBLOSTIM : Arbitration Lost Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_MIMR_TXIM : Transmit FIFO Request Interrupt Mask
bits : 8 - 16 (9 bit)

I2C_MIMR_RXIM : Receive FIFO Request Interrupt Mask
bits : 9 - 18 (10 bit)

I2C_MIMR_TXFEIM : Transmit FIFO Empty Interrupt Mask
bits : 10 - 20 (11 bit)

I2C_MIMR_RXFFIM : Receive FIFO Full Interrupt Mask
bits : 11 - 22 (12 bit)


MIMR

I2C Master Interrupt Mask
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIMR MIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MIMR_IM I2C_MIMR_CLKIM I2C_MIMR_DMARXIM I2C_MIMR_DMATXIM I2C_MIMR_NACKIM I2C_MIMR_STARTIM I2C_MIMR_STOPIM I2C_MIMR_ARBLOSTIM I2C_MIMR_TXIM I2C_MIMR_RXIM I2C_MIMR_TXFEIM I2C_MIMR_RXFFIM

I2C_MIMR_IM : Master Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_MIMR_CLKIM : Clock Timeout Interrupt Mask
bits : 1 - 2 (2 bit)

I2C_MIMR_DMARXIM : Receive DMA Interrupt Mask
bits : 2 - 4 (3 bit)

I2C_MIMR_DMATXIM : Transmit DMA Interrupt Mask
bits : 3 - 6 (4 bit)

I2C_MIMR_NACKIM : Address/Data NACK Interrupt Mask
bits : 4 - 8 (5 bit)

I2C_MIMR_STARTIM : START Detection Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_MIMR_STOPIM : STOP Detection Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_MIMR_ARBLOSTIM : Arbitration Lost Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_MIMR_TXIM : Transmit FIFO Request Interrupt Mask
bits : 8 - 16 (9 bit)

I2C_MIMR_RXIM : Receive FIFO Request Interrupt Mask
bits : 9 - 18 (10 bit)

I2C_MIMR_TXFEIM : Transmit FIFO Empty Interrupt Mask
bits : 10 - 20 (11 bit)

I2C_MIMR_RXFFIM : Receive FIFO Full Interrupt Mask
bits : 11 - 22 (12 bit)


I2C0MRIS

I2C Master Raw Interrupt Status
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MRIS I2C0MRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MRIS_RIS I2C_MRIS_CLKRIS I2C_MRIS_DMARXRIS I2C_MRIS_DMATXRIS I2C_MRIS_NACKRIS I2C_MRIS_STARTRIS I2C_MRIS_STOPRIS I2C_MRIS_ARBLOSTRIS I2C_MRIS_TXRIS I2C_MRIS_RXRIS I2C_MRIS_TXFERIS I2C_MRIS_RXFFRIS

I2C_MRIS_RIS : Master Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MRIS_CLKRIS : Clock Timeout Raw Interrupt Status
bits : 1 - 2 (2 bit)

I2C_MRIS_DMARXRIS : Receive DMA Raw Interrupt Status
bits : 2 - 4 (3 bit)

I2C_MRIS_DMATXRIS : Transmit DMA Raw Interrupt Status
bits : 3 - 6 (4 bit)

I2C_MRIS_NACKRIS : Address/Data NACK Raw Interrupt Status
bits : 4 - 8 (5 bit)

I2C_MRIS_STARTRIS : START Detection Raw Interrupt Status
bits : 5 - 10 (6 bit)

I2C_MRIS_STOPRIS : STOP Detection Raw Interrupt Status
bits : 6 - 12 (7 bit)

I2C_MRIS_ARBLOSTRIS : Arbitration Lost Raw Interrupt Status
bits : 7 - 14 (8 bit)

I2C_MRIS_TXRIS : Transmit Request Raw Interrupt Status
bits : 8 - 16 (9 bit)

I2C_MRIS_RXRIS : Receive FIFO Request Raw Interrupt Status
bits : 9 - 18 (10 bit)

I2C_MRIS_TXFERIS : Transmit FIFO Empty Raw Interrupt Status
bits : 10 - 20 (11 bit)

I2C_MRIS_RXFFRIS : Receive FIFO Full Raw Interrupt Status
bits : 11 - 22 (12 bit)


MRIS

I2C Master Raw Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MRIS MRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MRIS_RIS I2C_MRIS_CLKRIS I2C_MRIS_DMARXRIS I2C_MRIS_DMATXRIS I2C_MRIS_NACKRIS I2C_MRIS_STARTRIS I2C_MRIS_STOPRIS I2C_MRIS_ARBLOSTRIS I2C_MRIS_TXRIS I2C_MRIS_RXRIS I2C_MRIS_TXFERIS I2C_MRIS_RXFFRIS

I2C_MRIS_RIS : Master Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MRIS_CLKRIS : Clock Timeout Raw Interrupt Status
bits : 1 - 2 (2 bit)

I2C_MRIS_DMARXRIS : Receive DMA Raw Interrupt Status
bits : 2 - 4 (3 bit)

I2C_MRIS_DMATXRIS : Transmit DMA Raw Interrupt Status
bits : 3 - 6 (4 bit)

I2C_MRIS_NACKRIS : Address/Data NACK Raw Interrupt Status
bits : 4 - 8 (5 bit)

I2C_MRIS_STARTRIS : START Detection Raw Interrupt Status
bits : 5 - 10 (6 bit)

I2C_MRIS_STOPRIS : STOP Detection Raw Interrupt Status
bits : 6 - 12 (7 bit)

I2C_MRIS_ARBLOSTRIS : Arbitration Lost Raw Interrupt Status
bits : 7 - 14 (8 bit)

I2C_MRIS_TXRIS : Transmit Request Raw Interrupt Status
bits : 8 - 16 (9 bit)

I2C_MRIS_RXRIS : Receive FIFO Request Raw Interrupt Status
bits : 9 - 18 (10 bit)

I2C_MRIS_TXFERIS : Transmit FIFO Empty Raw Interrupt Status
bits : 10 - 20 (11 bit)

I2C_MRIS_RXFFRIS : Receive FIFO Full Raw Interrupt Status
bits : 11 - 22 (12 bit)


I2C0MMIS

I2C Master Masked Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MMIS I2C0MMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MMIS_MIS I2C_MMIS_CLKMIS I2C_MMIS_DMARXMIS I2C_MMIS_DMATXMIS I2C_MMIS_NACKMIS I2C_MMIS_STARTMIS I2C_MMIS_STOPMIS I2C_MMIS_ARBLOSTMIS I2C_MMIS_TXMIS I2C_MMIS_RXMIS I2C_MMIS_TXFEMIS I2C_MMIS_RXFFMIS

I2C_MMIS_MIS : Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MMIS_CLKMIS : Clock Timeout Masked Interrupt Status
bits : 1 - 2 (2 bit)

I2C_MMIS_DMARXMIS : Receive DMA Interrupt Status
bits : 2 - 4 (3 bit)

I2C_MMIS_DMATXMIS : Transmit DMA Interrupt Status
bits : 3 - 6 (4 bit)

I2C_MMIS_NACKMIS : Address/Data NACK Interrupt Mask
bits : 4 - 8 (5 bit)

I2C_MMIS_STARTMIS : START Detection Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_MMIS_STOPMIS : STOP Detection Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_MMIS_ARBLOSTMIS : Arbitration Lost Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_MMIS_TXMIS : Transmit Request Interrupt Mask
bits : 8 - 16 (9 bit)

I2C_MMIS_RXMIS : Receive FIFO Request Interrupt Mask
bits : 9 - 18 (10 bit)

I2C_MMIS_TXFEMIS : Transmit FIFO Empty Interrupt Mask
bits : 10 - 20 (11 bit)

I2C_MMIS_RXFFMIS : Receive FIFO Full Interrupt Mask
bits : 11 - 22 (12 bit)


MMIS

I2C Master Masked Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMIS MMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MMIS_MIS I2C_MMIS_CLKMIS I2C_MMIS_DMARXMIS I2C_MMIS_DMATXMIS I2C_MMIS_NACKMIS I2C_MMIS_STARTMIS I2C_MMIS_STOPMIS I2C_MMIS_ARBLOSTMIS I2C_MMIS_TXMIS I2C_MMIS_RXMIS I2C_MMIS_TXFEMIS I2C_MMIS_RXFFMIS

I2C_MMIS_MIS : Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_MMIS_CLKMIS : Clock Timeout Masked Interrupt Status
bits : 1 - 2 (2 bit)

I2C_MMIS_DMARXMIS : Receive DMA Interrupt Status
bits : 2 - 4 (3 bit)

I2C_MMIS_DMATXMIS : Transmit DMA Interrupt Status
bits : 3 - 6 (4 bit)

I2C_MMIS_NACKMIS : Address/Data NACK Interrupt Mask
bits : 4 - 8 (5 bit)

I2C_MMIS_STARTMIS : START Detection Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_MMIS_STOPMIS : STOP Detection Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_MMIS_ARBLOSTMIS : Arbitration Lost Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_MMIS_TXMIS : Transmit Request Interrupt Mask
bits : 8 - 16 (9 bit)

I2C_MMIS_RXMIS : Receive FIFO Request Interrupt Mask
bits : 9 - 18 (10 bit)

I2C_MMIS_TXFEMIS : Transmit FIFO Empty Interrupt Mask
bits : 10 - 20 (11 bit)

I2C_MMIS_RXFFMIS : Receive FIFO Full Interrupt Mask
bits : 11 - 22 (12 bit)


I2C0MICR

I2C Master Interrupt Clear
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2C0MICR I2C0MICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MICR_IC I2C_MICR_CLKIC I2C_MICR_DMARXIC I2C_MICR_DMATXIC I2C_MICR_NACKIC I2C_MICR_STARTIC I2C_MICR_STOPIC I2C_MICR_ARBLOSTIC I2C_MICR_TXIC I2C_MICR_RXIC I2C_MICR_TXFEIC I2C_MICR_RXFFIC

I2C_MICR_IC : Master Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_MICR_CLKIC : Clock Timeout Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only

I2C_MICR_DMARXIC : Receive DMA Interrupt Clear
bits : 2 - 4 (3 bit)
access : write-only

I2C_MICR_DMATXIC : Transmit DMA Interrupt Clear
bits : 3 - 6 (4 bit)
access : write-only

I2C_MICR_NACKIC : Address/Data NACK Interrupt Clear
bits : 4 - 8 (5 bit)
access : write-only

I2C_MICR_STARTIC : START Detection Interrupt Clear
bits : 5 - 10 (6 bit)
access : write-only

I2C_MICR_STOPIC : STOP Detection Interrupt Clear
bits : 6 - 12 (7 bit)
access : write-only

I2C_MICR_ARBLOSTIC : Arbitration Lost Interrupt Clear
bits : 7 - 14 (8 bit)
access : write-only

I2C_MICR_TXIC : Transmit FIFO Request Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only

I2C_MICR_RXIC : Receive FIFO Request Interrupt Clear
bits : 9 - 18 (10 bit)
access : write-only

I2C_MICR_TXFEIC : Transmit FIFO Empty Interrupt Clear
bits : 10 - 20 (11 bit)
access : write-only

I2C_MICR_RXFFIC : Receive FIFO Full Interrupt Clear
bits : 11 - 22 (12 bit)
access : write-only


MICR

I2C Master Interrupt Clear
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MICR MICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MICR_IC I2C_MICR_CLKIC I2C_MICR_DMARXIC I2C_MICR_DMATXIC I2C_MICR_NACKIC I2C_MICR_STARTIC I2C_MICR_STOPIC I2C_MICR_ARBLOSTIC I2C_MICR_TXIC I2C_MICR_RXIC I2C_MICR_TXFEIC I2C_MICR_RXFFIC

I2C_MICR_IC : Master Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_MICR_CLKIC : Clock Timeout Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only

I2C_MICR_DMARXIC : Receive DMA Interrupt Clear
bits : 2 - 4 (3 bit)
access : write-only

I2C_MICR_DMATXIC : Transmit DMA Interrupt Clear
bits : 3 - 6 (4 bit)
access : write-only

I2C_MICR_NACKIC : Address/Data NACK Interrupt Clear
bits : 4 - 8 (5 bit)
access : write-only

I2C_MICR_STARTIC : START Detection Interrupt Clear
bits : 5 - 10 (6 bit)
access : write-only

I2C_MICR_STOPIC : STOP Detection Interrupt Clear
bits : 6 - 12 (7 bit)
access : write-only

I2C_MICR_ARBLOSTIC : Arbitration Lost Interrupt Clear
bits : 7 - 14 (8 bit)
access : write-only

I2C_MICR_TXIC : Transmit FIFO Request Interrupt Clear
bits : 8 - 16 (9 bit)
access : write-only

I2C_MICR_RXIC : Receive FIFO Request Interrupt Clear
bits : 9 - 18 (10 bit)
access : write-only

I2C_MICR_TXFEIC : Transmit FIFO Empty Interrupt Clear
bits : 10 - 20 (11 bit)
access : write-only

I2C_MICR_RXFFIC : Receive FIFO Full Interrupt Clear
bits : 11 - 22 (12 bit)
access : write-only


I2C0MCR

I2C Master Configuration
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MCR I2C0MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCR_LPBK I2C_MCR_MFE I2C_MCR_SFE

I2C_MCR_LPBK : I2C Loopback
bits : 0 - 0 (1 bit)

I2C_MCR_MFE : I2C Master Function Enable
bits : 4 - 8 (5 bit)

I2C_MCR_SFE : I2C Slave Function Enable
bits : 5 - 10 (6 bit)


MCR

I2C Master Configuration
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCR MCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCR_LPBK I2C_MCR_MFE I2C_MCR_SFE

I2C_MCR_LPBK : I2C Loopback
bits : 0 - 0 (1 bit)

I2C_MCR_MFE : I2C Master Function Enable
bits : 4 - 8 (5 bit)

I2C_MCR_SFE : I2C Slave Function Enable
bits : 5 - 10 (6 bit)


I2C0MCLKOCNT

I2C Master Clock Low Timeout Count
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MCLKOCNT I2C0MCLKOCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCLKOCNT_CNTL

I2C_MCLKOCNT_CNTL : I2C Master Count
bits : 0 - 7 (8 bit)


MCLKOCNT

I2C Master Clock Low Timeout Count
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCLKOCNT MCLKOCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCLKOCNT_CNTL

I2C_MCLKOCNT_CNTL : I2C Master Count
bits : 0 - 7 (8 bit)


I2C0MBMON

I2C Master Bus Monitor
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MBMON I2C0MBMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBMON_SCL I2C_MBMON_SDA

I2C_MBMON_SCL : I2C SCL Status
bits : 0 - 0 (1 bit)

I2C_MBMON_SDA : I2C SDA Status
bits : 1 - 2 (2 bit)


MBMON

I2C Master Bus Monitor
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBMON MBMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBMON_SCL I2C_MBMON_SDA

I2C_MBMON_SCL : I2C SCL Status
bits : 0 - 0 (1 bit)

I2C_MBMON_SDA : I2C SDA Status
bits : 1 - 2 (2 bit)


I2C0MBLEN

I2C Master Burst Length
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MBLEN I2C0MBLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBLEN_CNTL

I2C_MBLEN_CNTL : I2C Burst Length
bits : 0 - 7 (8 bit)


MBLEN

I2C Master Burst Length
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBLEN MBLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBLEN_CNTL

I2C_MBLEN_CNTL : I2C Burst Length
bits : 0 - 7 (8 bit)


I2C0MBCNT

I2C Master Burst Count
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MBCNT I2C0MBCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBCNT_CNTL

I2C_MBCNT_CNTL : I2C Master Burst Count
bits : 0 - 7 (8 bit)


MBCNT

I2C Master Burst Count
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MBCNT MBCNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MBCNT_CNTL

I2C_MBCNT_CNTL : I2C Master Burst Count
bits : 0 - 7 (8 bit)


I2C0MCS

I2C Master Control/Status
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MCS I2C0MCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCS_RUN I2C_MCS_START I2C_MCS_ADRACK I2C_MCS_ACK I2C_MCS_ARBLST I2C_MCS_IDLE I2C_MCS_BURST I2C_MCS_CLKTO I2C_MCS_ACTDMATX I2C_MCS_ACTDMARX

I2C_MCS_RUN : I2C Master Enable
bits : 0 - 0 (1 bit)

I2C_MCS_START : Generate START
bits : 1 - 2 (2 bit)

I2C_MCS_ADRACK : Acknowledge Address
bits : 2 - 4 (3 bit)

I2C_MCS_ACK : Data Acknowledge Enable
bits : 3 - 6 (4 bit)

I2C_MCS_ARBLST : Arbitration Lost
bits : 4 - 8 (5 bit)

I2C_MCS_IDLE : I2C Idle
bits : 5 - 10 (6 bit)

I2C_MCS_BURST : Burst Enable
bits : 6 - 12 (7 bit)

I2C_MCS_CLKTO : Clock Timeout Error
bits : 7 - 14 (8 bit)

I2C_MCS_ACTDMATX : DMA TX Active Status
bits : 30 - 60 (31 bit)

I2C_MCS_ACTDMARX : DMA RX Active Status
bits : 31 - 62 (32 bit)


MCS

I2C Master Control/Status
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCS MCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MCS_RUN I2C_MCS_BUSY I2C_MCS_START I2C_MCS_ERROR I2C_MCS_ADRACK I2C_MCS_STOP I2C_MCS_ACK I2C_MCS_DATACK I2C_MCS_ARBLST I2C_MCS_HS I2C_MCS_IDLE I2C_MCS_QCMD I2C_MCS_BURST I2C_MCS_BUSBSY I2C_MCS_CLKTO I2C_MCS_ACTDMATX I2C_MCS_ACTDMARX

I2C_MCS_RUN : I2C Master Enable
bits : 0 - 0 (1 bit)

I2C_MCS_BUSY : I2C Busy
bits : 0 - 0 (1 bit)

I2C_MCS_START : Generate START
bits : 1 - 2 (2 bit)

I2C_MCS_ERROR : Error
bits : 1 - 2 (2 bit)

I2C_MCS_ADRACK : Acknowledge Address
bits : 2 - 4 (3 bit)

I2C_MCS_STOP : Generate STOP
bits : 2 - 4 (3 bit)

I2C_MCS_ACK : Data Acknowledge Enable
bits : 3 - 6 (4 bit)

I2C_MCS_DATACK : Acknowledge Data
bits : 3 - 6 (4 bit)

I2C_MCS_ARBLST : Arbitration Lost
bits : 4 - 8 (5 bit)

I2C_MCS_HS : High-Speed Enable
bits : 4 - 8 (5 bit)

I2C_MCS_IDLE : I2C Idle
bits : 5 - 10 (6 bit)

I2C_MCS_QCMD : Quick Command
bits : 5 - 10 (6 bit)

I2C_MCS_BURST : Burst Enable
bits : 6 - 12 (7 bit)

I2C_MCS_BUSBSY : Bus Busy
bits : 6 - 12 (7 bit)

I2C_MCS_CLKTO : Clock Timeout Error
bits : 7 - 14 (8 bit)

I2C_MCS_ACTDMATX : DMA TX Active Status
bits : 30 - 60 (31 bit)

I2C_MCS_ACTDMARX : DMA RX Active Status
bits : 31 - 62 (32 bit)


I2C0MDR

I2C Master Data
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MDR I2C0MDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MDR_DATA

I2C_MDR_DATA : This byte contains the data transferred during a transaction
bits : 0 - 7 (8 bit)


MDR

I2C Master Data
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MDR MDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MDR_DATA

I2C_MDR_DATA : This byte contains the data transferred during a transaction
bits : 0 - 7 (8 bit)


I2C0SOAR

I2C Slave Own Address
address_offset : 0x800 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SOAR I2C0SOAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR_OAR

I2C_SOAR_OAR : I2C Slave Own Address
bits : 0 - 6 (7 bit)


SOAR

I2C Slave Own Address
address_offset : 0x800 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOAR SOAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR_OAR

I2C_SOAR_OAR : I2C Slave Own Address
bits : 0 - 6 (7 bit)


I2C0SCSR

I2C Slave Control/Status
address_offset : 0x804 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SCSR I2C0SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SCSR_RREQ I2C_SCSR_TXFIFO I2C_SCSR_FBR I2C_SCSR_OAR2SEL I2C_SCSR_QCMDST I2C_SCSR_QCMDRW I2C_SCSR_ACTDMATX I2C_SCSR_ACTDMARX

I2C_SCSR_RREQ : Receive Request
bits : 0 - 0 (1 bit)

I2C_SCSR_TXFIFO : TX FIFO Enable
bits : 1 - 2 (2 bit)

I2C_SCSR_FBR : First Byte Received
bits : 2 - 4 (3 bit)

I2C_SCSR_OAR2SEL : OAR2 Address Matched
bits : 3 - 6 (4 bit)

I2C_SCSR_QCMDST : Quick Command Status
bits : 4 - 8 (5 bit)

I2C_SCSR_QCMDRW : Quick Command Read / Write
bits : 5 - 10 (6 bit)

I2C_SCSR_ACTDMATX : DMA TX Active Status
bits : 30 - 60 (31 bit)

I2C_SCSR_ACTDMARX : DMA RX Active Status
bits : 31 - 62 (32 bit)


SCSR

I2C Slave Control/Status
address_offset : 0x804 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCSR SCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SCSR_RREQ I2C_SCSR_DA I2C_SCSR_TXFIFO I2C_SCSR_TREQ I2C_SCSR_FBR I2C_SCSR_RXFIFO I2C_SCSR_OAR2SEL I2C_SCSR_QCMDST I2C_SCSR_QCMDRW I2C_SCSR_ACTDMATX I2C_SCSR_ACTDMARX

I2C_SCSR_RREQ : Receive Request
bits : 0 - 0 (1 bit)

I2C_SCSR_DA : Device Active
bits : 0 - 0 (1 bit)

I2C_SCSR_TXFIFO : TX FIFO Enable
bits : 1 - 2 (2 bit)

I2C_SCSR_TREQ : Transmit Request
bits : 1 - 2 (2 bit)

I2C_SCSR_FBR : First Byte Received
bits : 2 - 4 (3 bit)

I2C_SCSR_RXFIFO : RX FIFO Enable
bits : 2 - 4 (3 bit)

I2C_SCSR_OAR2SEL : OAR2 Address Matched
bits : 3 - 6 (4 bit)

I2C_SCSR_QCMDST : Quick Command Status
bits : 4 - 8 (5 bit)

I2C_SCSR_QCMDRW : Quick Command Read / Write
bits : 5 - 10 (6 bit)

I2C_SCSR_ACTDMATX : DMA TX Active Status
bits : 30 - 60 (31 bit)

I2C_SCSR_ACTDMARX : DMA RX Active Status
bits : 31 - 62 (32 bit)


I2C0SDR

I2C Slave Data
address_offset : 0x808 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SDR I2C0SDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SDR_DATA

I2C_SDR_DATA : Data for Transfer
bits : 0 - 7 (8 bit)


SDR

I2C Slave Data
address_offset : 0x808 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR SDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SDR_DATA

I2C_SDR_DATA : Data for Transfer
bits : 0 - 7 (8 bit)


I2C0SIMR

I2C Slave Interrupt Mask
address_offset : 0x80C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SIMR I2C0SIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SIMR_DATAIM I2C_SIMR_STARTIM I2C_SIMR_STOPIM I2C_SIMR_DMARXIM I2C_SIMR_DMATXIM I2C_SIMR_TXIM I2C_SIMR_RXIM I2C_SIMR_TXFEIM I2C_SIMR_RXFFIM

I2C_SIMR_DATAIM : Data Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_SIMR_STARTIM : Start Condition Interrupt Mask
bits : 1 - 2 (2 bit)

I2C_SIMR_STOPIM : Stop Condition Interrupt Mask
bits : 2 - 4 (3 bit)

I2C_SIMR_DMARXIM : Receive DMA Interrupt Mask
bits : 3 - 6 (4 bit)

I2C_SIMR_DMATXIM : Transmit DMA Interrupt Mask
bits : 4 - 8 (5 bit)

I2C_SIMR_TXIM : Transmit FIFO Request Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_SIMR_RXIM : Receive FIFO Request Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_SIMR_TXFEIM : Transmit FIFO Empty Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_SIMR_RXFFIM : Receive FIFO Full Interrupt Mask
bits : 8 - 16 (9 bit)


SIMR

I2C Slave Interrupt Mask
address_offset : 0x80C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIMR SIMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SIMR_DATAIM I2C_SIMR_STARTIM I2C_SIMR_STOPIM I2C_SIMR_DMARXIM I2C_SIMR_DMATXIM I2C_SIMR_TXIM I2C_SIMR_RXIM I2C_SIMR_TXFEIM I2C_SIMR_RXFFIM

I2C_SIMR_DATAIM : Data Interrupt Mask
bits : 0 - 0 (1 bit)

I2C_SIMR_STARTIM : Start Condition Interrupt Mask
bits : 1 - 2 (2 bit)

I2C_SIMR_STOPIM : Stop Condition Interrupt Mask
bits : 2 - 4 (3 bit)

I2C_SIMR_DMARXIM : Receive DMA Interrupt Mask
bits : 3 - 6 (4 bit)

I2C_SIMR_DMATXIM : Transmit DMA Interrupt Mask
bits : 4 - 8 (5 bit)

I2C_SIMR_TXIM : Transmit FIFO Request Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_SIMR_RXIM : Receive FIFO Request Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_SIMR_TXFEIM : Transmit FIFO Empty Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_SIMR_RXFFIM : Receive FIFO Full Interrupt Mask
bits : 8 - 16 (9 bit)


I2C0SRIS

I2C Slave Raw Interrupt Status
address_offset : 0x810 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SRIS I2C0SRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SRIS_DATARIS I2C_SRIS_STARTRIS I2C_SRIS_STOPRIS I2C_SRIS_DMARXRIS I2C_SRIS_DMATXRIS I2C_SRIS_TXRIS I2C_SRIS_RXRIS I2C_SRIS_TXFERIS I2C_SRIS_RXFFRIS

I2C_SRIS_DATARIS : Data Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SRIS_STARTRIS : Start Condition Raw Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SRIS_STOPRIS : Stop Condition Raw Interrupt Status
bits : 2 - 4 (3 bit)

I2C_SRIS_DMARXRIS : Receive DMA Raw Interrupt Status
bits : 3 - 6 (4 bit)

I2C_SRIS_DMATXRIS : Transmit DMA Raw Interrupt Status
bits : 4 - 8 (5 bit)

I2C_SRIS_TXRIS : Transmit Request Raw Interrupt Status
bits : 5 - 10 (6 bit)

I2C_SRIS_RXRIS : Receive FIFO Request Raw Interrupt Status
bits : 6 - 12 (7 bit)

I2C_SRIS_TXFERIS : Transmit FIFO Empty Raw Interrupt Status
bits : 7 - 14 (8 bit)

I2C_SRIS_RXFFRIS : Receive FIFO Full Raw Interrupt Status
bits : 8 - 16 (9 bit)


SRIS

I2C Slave Raw Interrupt Status
address_offset : 0x810 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRIS SRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SRIS_DATARIS I2C_SRIS_STARTRIS I2C_SRIS_STOPRIS I2C_SRIS_DMARXRIS I2C_SRIS_DMATXRIS I2C_SRIS_TXRIS I2C_SRIS_RXRIS I2C_SRIS_TXFERIS I2C_SRIS_RXFFRIS

I2C_SRIS_DATARIS : Data Raw Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SRIS_STARTRIS : Start Condition Raw Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SRIS_STOPRIS : Stop Condition Raw Interrupt Status
bits : 2 - 4 (3 bit)

I2C_SRIS_DMARXRIS : Receive DMA Raw Interrupt Status
bits : 3 - 6 (4 bit)

I2C_SRIS_DMATXRIS : Transmit DMA Raw Interrupt Status
bits : 4 - 8 (5 bit)

I2C_SRIS_TXRIS : Transmit Request Raw Interrupt Status
bits : 5 - 10 (6 bit)

I2C_SRIS_RXRIS : Receive FIFO Request Raw Interrupt Status
bits : 6 - 12 (7 bit)

I2C_SRIS_TXFERIS : Transmit FIFO Empty Raw Interrupt Status
bits : 7 - 14 (8 bit)

I2C_SRIS_RXFFRIS : Receive FIFO Full Raw Interrupt Status
bits : 8 - 16 (9 bit)


I2C0SMIS

I2C Slave Masked Interrupt Status
address_offset : 0x814 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SMIS I2C0SMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SMIS_DATAMIS I2C_SMIS_STARTMIS I2C_SMIS_STOPMIS I2C_SMIS_DMARXMIS I2C_SMIS_DMATXMIS I2C_SMIS_TXMIS I2C_SMIS_RXMIS I2C_SMIS_TXFEMIS I2C_SMIS_RXFFMIS

I2C_SMIS_DATAMIS : Data Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SMIS_STARTMIS : Start Condition Masked Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SMIS_STOPMIS : Stop Condition Masked Interrupt Status
bits : 2 - 4 (3 bit)

I2C_SMIS_DMARXMIS : Receive DMA Masked Interrupt Status
bits : 3 - 6 (4 bit)

I2C_SMIS_DMATXMIS : Transmit DMA Masked Interrupt Status
bits : 4 - 8 (5 bit)

I2C_SMIS_TXMIS : Transmit FIFO Request Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_SMIS_RXMIS : Receive FIFO Request Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_SMIS_TXFEMIS : Transmit FIFO Empty Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_SMIS_RXFFMIS : Receive FIFO Full Interrupt Mask
bits : 8 - 16 (9 bit)


SMIS

I2C Slave Masked Interrupt Status
address_offset : 0x814 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMIS SMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SMIS_DATAMIS I2C_SMIS_STARTMIS I2C_SMIS_STOPMIS I2C_SMIS_DMARXMIS I2C_SMIS_DMATXMIS I2C_SMIS_TXMIS I2C_SMIS_RXMIS I2C_SMIS_TXFEMIS I2C_SMIS_RXFFMIS

I2C_SMIS_DATAMIS : Data Masked Interrupt Status
bits : 0 - 0 (1 bit)

I2C_SMIS_STARTMIS : Start Condition Masked Interrupt Status
bits : 1 - 2 (2 bit)

I2C_SMIS_STOPMIS : Stop Condition Masked Interrupt Status
bits : 2 - 4 (3 bit)

I2C_SMIS_DMARXMIS : Receive DMA Masked Interrupt Status
bits : 3 - 6 (4 bit)

I2C_SMIS_DMATXMIS : Transmit DMA Masked Interrupt Status
bits : 4 - 8 (5 bit)

I2C_SMIS_TXMIS : Transmit FIFO Request Interrupt Mask
bits : 5 - 10 (6 bit)

I2C_SMIS_RXMIS : Receive FIFO Request Interrupt Mask
bits : 6 - 12 (7 bit)

I2C_SMIS_TXFEMIS : Transmit FIFO Empty Interrupt Mask
bits : 7 - 14 (8 bit)

I2C_SMIS_RXFFMIS : Receive FIFO Full Interrupt Mask
bits : 8 - 16 (9 bit)


I2C0SICR

I2C Slave Interrupt Clear
address_offset : 0x818 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

I2C0SICR I2C0SICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SICR_DATAIC I2C_SICR_STARTIC I2C_SICR_STOPIC I2C_SICR_DMARXIC I2C_SICR_DMATXIC I2C_SICR_TXIC I2C_SICR_RXIC I2C_SICR_TXFEIC I2C_SICR_RXFFIC

I2C_SICR_DATAIC : Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_SICR_STARTIC : Start Condition Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only

I2C_SICR_STOPIC : Stop Condition Interrupt Clear
bits : 2 - 4 (3 bit)
access : write-only

I2C_SICR_DMARXIC : Receive DMA Interrupt Clear
bits : 3 - 6 (4 bit)
access : write-only

I2C_SICR_DMATXIC : Transmit DMA Interrupt Clear
bits : 4 - 8 (5 bit)
access : write-only

I2C_SICR_TXIC : Transmit Request Interrupt Mask
bits : 5 - 10 (6 bit)
access : write-only

I2C_SICR_RXIC : Receive Request Interrupt Mask
bits : 6 - 12 (7 bit)
access : write-only

I2C_SICR_TXFEIC : Transmit FIFO Empty Interrupt Mask
bits : 7 - 14 (8 bit)
access : write-only

I2C_SICR_RXFFIC : Receive FIFO Full Interrupt Mask
bits : 8 - 16 (9 bit)
access : write-only


SICR

I2C Slave Interrupt Clear
address_offset : 0x818 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SICR SICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SICR_DATAIC I2C_SICR_STARTIC I2C_SICR_STOPIC I2C_SICR_DMARXIC I2C_SICR_DMATXIC I2C_SICR_TXIC I2C_SICR_RXIC I2C_SICR_TXFEIC I2C_SICR_RXFFIC

I2C_SICR_DATAIC : Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

I2C_SICR_STARTIC : Start Condition Interrupt Clear
bits : 1 - 2 (2 bit)
access : write-only

I2C_SICR_STOPIC : Stop Condition Interrupt Clear
bits : 2 - 4 (3 bit)
access : write-only

I2C_SICR_DMARXIC : Receive DMA Interrupt Clear
bits : 3 - 6 (4 bit)
access : write-only

I2C_SICR_DMATXIC : Transmit DMA Interrupt Clear
bits : 4 - 8 (5 bit)
access : write-only

I2C_SICR_TXIC : Transmit Request Interrupt Mask
bits : 5 - 10 (6 bit)
access : write-only

I2C_SICR_RXIC : Receive Request Interrupt Mask
bits : 6 - 12 (7 bit)
access : write-only

I2C_SICR_TXFEIC : Transmit FIFO Empty Interrupt Mask
bits : 7 - 14 (8 bit)
access : write-only

I2C_SICR_RXFFIC : Receive FIFO Full Interrupt Mask
bits : 8 - 16 (9 bit)
access : write-only


I2C0SOAR2

I2C Slave Own Address 2
address_offset : 0x81C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SOAR2 I2C0SOAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR2_OAR2 I2C_SOAR2_OAR2EN

I2C_SOAR2_OAR2 : I2C Slave Own Address 2
bits : 0 - 6 (7 bit)

I2C_SOAR2_OAR2EN : I2C Slave Own Address 2 Enable
bits : 7 - 14 (8 bit)


SOAR2

I2C Slave Own Address 2
address_offset : 0x81C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOAR2 SOAR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SOAR2_OAR2 I2C_SOAR2_OAR2EN

I2C_SOAR2_OAR2 : I2C Slave Own Address 2
bits : 0 - 6 (7 bit)

I2C_SOAR2_OAR2EN : I2C Slave Own Address 2 Enable
bits : 7 - 14 (8 bit)


I2C0SACKCTL

I2C Slave ACK Control
address_offset : 0x820 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0SACKCTL I2C0SACKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SACKCTL_ACKOEN I2C_SACKCTL_ACKOVAL

I2C_SACKCTL_ACKOEN : I2C Slave ACK Override Enable
bits : 0 - 0 (1 bit)

I2C_SACKCTL_ACKOVAL : I2C Slave ACK Override Value
bits : 1 - 2 (2 bit)


SACKCTL

I2C Slave ACK Control
address_offset : 0x820 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SACKCTL SACKCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_SACKCTL_ACKOEN I2C_SACKCTL_ACKOVAL

I2C_SACKCTL_ACKOEN : I2C Slave ACK Override Enable
bits : 0 - 0 (1 bit)

I2C_SACKCTL_ACKOVAL : I2C Slave ACK Override Value
bits : 1 - 2 (2 bit)


I2C0MTPR

I2C Master Timer Period
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0MTPR I2C0MTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MTPR_TPR I2C_MTPR_HS I2C_MTPR_PULSEL

I2C_MTPR_TPR : Timer Period
bits : 0 - 6 (7 bit)

I2C_MTPR_HS : High-Speed Enable
bits : 7 - 14 (8 bit)

I2C_MTPR_PULSEL : Glitch Suppression Pulse Width
bits : 16 - 34 (19 bit)

Enumeration:

0x0 : I2C_MTPR_PULSEL_BYPASS

Bypass

0x1 : I2C_MTPR_PULSEL_1

1 clock

0x2 : I2C_MTPR_PULSEL_2

2 clocks

0x3 : I2C_MTPR_PULSEL_3

3 clocks

0x4 : I2C_MTPR_PULSEL_4

4 clocks

0x5 : I2C_MTPR_PULSEL_8

8 clocks

0x6 : I2C_MTPR_PULSEL_16

16 clocks

0x7 : I2C_MTPR_PULSEL_31

31 clocks

End of enumeration elements list.


MTPR

I2C Master Timer Period
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTPR MTPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MTPR_TPR I2C_MTPR_HS I2C_MTPR_PULSEL

I2C_MTPR_TPR : Timer Period
bits : 0 - 6 (7 bit)

I2C_MTPR_HS : High-Speed Enable
bits : 7 - 14 (8 bit)

I2C_MTPR_PULSEL : Glitch Suppression Pulse Width
bits : 16 - 34 (19 bit)

Enumeration:

0x0 : I2C_MTPR_PULSEL_BYPASS

Bypass

0x1 : I2C_MTPR_PULSEL_1

1 clock

0x2 : I2C_MTPR_PULSEL_2

2 clocks

0x3 : I2C_MTPR_PULSEL_3

3 clocks

0x4 : I2C_MTPR_PULSEL_4

4 clocks

0x5 : I2C_MTPR_PULSEL_8

8 clocks

0x6 : I2C_MTPR_PULSEL_16

16 clocks

0x7 : I2C_MTPR_PULSEL_31

31 clocks

End of enumeration elements list.


I2C0FIFODATA

I2C FIFO Data
address_offset : 0xF00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0FIFODATA I2C0FIFODATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_FIFODATA_DATA

I2C_FIFODATA_DATA : I2C TX FIFO Write Data Byte
bits : 0 - 7 (8 bit)


FIFODATA

I2C FIFO Data
address_offset : 0xF00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFODATA FIFODATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_FIFODATA_DATA

I2C_FIFODATA_DATA : I2C TX FIFO Write Data Byte
bits : 0 - 7 (8 bit)


I2C0FIFOCTL

I2C FIFO Control
address_offset : 0xF04 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0FIFOCTL I2C0FIFOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_FIFOCTL_TXTRIG I2C_FIFOCTL_DMATXENA I2C_FIFOCTL_TXFLUSH I2C_FIFOCTL_TXASGNMT I2C_FIFOCTL_RXTRIG I2C_FIFOCTL_DMARXENA I2C_FIFOCTL_RXFLUSH I2C_FIFOCTL_RXASGNMT

I2C_FIFOCTL_TXTRIG : TX FIFO Trigger
bits : 0 - 2 (3 bit)

I2C_FIFOCTL_DMATXENA : DMA TX Channel Enable
bits : 13 - 26 (14 bit)

I2C_FIFOCTL_TXFLUSH : TX FIFO Flush
bits : 14 - 28 (15 bit)

I2C_FIFOCTL_TXASGNMT : TX Control Assignment
bits : 15 - 30 (16 bit)

I2C_FIFOCTL_RXTRIG : RX FIFO Trigger
bits : 16 - 34 (19 bit)

I2C_FIFOCTL_DMARXENA : DMA RX Channel Enable
bits : 29 - 58 (30 bit)

I2C_FIFOCTL_RXFLUSH : RX FIFO Flush
bits : 30 - 60 (31 bit)

I2C_FIFOCTL_RXASGNMT : RX Control Assignment
bits : 31 - 62 (32 bit)


FIFOCTL

I2C FIFO Control
address_offset : 0xF04 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOCTL FIFOCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_FIFOCTL_TXTRIG I2C_FIFOCTL_DMATXENA I2C_FIFOCTL_TXFLUSH I2C_FIFOCTL_TXASGNMT I2C_FIFOCTL_RXTRIG I2C_FIFOCTL_DMARXENA I2C_FIFOCTL_RXFLUSH I2C_FIFOCTL_RXASGNMT

I2C_FIFOCTL_TXTRIG : TX FIFO Trigger
bits : 0 - 2 (3 bit)

I2C_FIFOCTL_DMATXENA : DMA TX Channel Enable
bits : 13 - 26 (14 bit)

I2C_FIFOCTL_TXFLUSH : TX FIFO Flush
bits : 14 - 28 (15 bit)

I2C_FIFOCTL_TXASGNMT : TX Control Assignment
bits : 15 - 30 (16 bit)

I2C_FIFOCTL_RXTRIG : RX FIFO Trigger
bits : 16 - 34 (19 bit)

I2C_FIFOCTL_DMARXENA : DMA RX Channel Enable
bits : 29 - 58 (30 bit)

I2C_FIFOCTL_RXFLUSH : RX FIFO Flush
bits : 30 - 60 (31 bit)

I2C_FIFOCTL_RXASGNMT : RX Control Assignment
bits : 31 - 62 (32 bit)


I2C0FIFOSTATUS

I2C FIFO Status
address_offset : 0xF08 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0FIFOSTATUS I2C0FIFOSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_FIFOSTATUS_TXFE I2C_FIFOSTATUS_TXFF I2C_FIFOSTATUS_TXBLWTRIG I2C_FIFOSTATUS_RXFE I2C_FIFOSTATUS_RXFF I2C_FIFOSTATUS_RXABVTRIG

I2C_FIFOSTATUS_TXFE : TX FIFO Empty
bits : 0 - 0 (1 bit)

I2C_FIFOSTATUS_TXFF : TX FIFO Full
bits : 1 - 2 (2 bit)

I2C_FIFOSTATUS_TXBLWTRIG : TX FIFO Below Trigger Level
bits : 2 - 4 (3 bit)

I2C_FIFOSTATUS_RXFE : RX FIFO Empty
bits : 16 - 32 (17 bit)

I2C_FIFOSTATUS_RXFF : RX FIFO Full
bits : 17 - 34 (18 bit)

I2C_FIFOSTATUS_RXABVTRIG : RX FIFO Above Trigger Level
bits : 18 - 36 (19 bit)


FIFOSTATUS

I2C FIFO Status
address_offset : 0xF08 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFOSTATUS FIFOSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_FIFOSTATUS_TXFE I2C_FIFOSTATUS_TXFF I2C_FIFOSTATUS_TXBLWTRIG I2C_FIFOSTATUS_RXFE I2C_FIFOSTATUS_RXFF I2C_FIFOSTATUS_RXABVTRIG

I2C_FIFOSTATUS_TXFE : TX FIFO Empty
bits : 0 - 0 (1 bit)

I2C_FIFOSTATUS_TXFF : TX FIFO Full
bits : 1 - 2 (2 bit)

I2C_FIFOSTATUS_TXBLWTRIG : TX FIFO Below Trigger Level
bits : 2 - 4 (3 bit)

I2C_FIFOSTATUS_RXFE : RX FIFO Empty
bits : 16 - 32 (17 bit)

I2C_FIFOSTATUS_RXFF : RX FIFO Full
bits : 17 - 34 (18 bit)

I2C_FIFOSTATUS_RXABVTRIG : RX FIFO Above Trigger Level
bits : 18 - 36 (19 bit)


I2C0PP

I2C Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0PP I2C0PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_PP_HS

I2C_PP_HS : High-Speed Capable
bits : 0 - 0 (1 bit)


PP

I2C Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PP PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_PP_HS

I2C_PP_HS : High-Speed Capable
bits : 0 - 0 (1 bit)


I2C0PC

I2C Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C0PC I2C0PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_PC_HS

I2C_PC_HS : High-Speed Capable
bits : 0 - 0 (1 bit)


PC

I2C Peripheral Configuration
address_offset : 0xFC4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PC PC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_PC_HS

I2C_PC_HS : High-Speed Capable
bits : 0 - 0 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.