Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Comparator Control Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEIPSEL : Channel input selected for the V+ terminal
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : CEIPSEL_0
Channel 0 selected
1 : CEIPSEL_1
Channel 1 selected
2 : CEIPSEL_2
Channel 2 selected
3 : CEIPSEL_3
Channel 3 selected
4 : CEIPSEL_4
Channel 4 selected
5 : CEIPSEL_5
Channel 5 selected
6 : CEIPSEL_6
Channel 6 selected
7 : CEIPSEL_7
Channel 7 selected
8 : CEIPSEL_8
Channel 8 selected
9 : CEIPSEL_9
Channel 9 selected
10 : CEIPSEL_10
Channel 10 selected
11 : CEIPSEL_11
Channel 11 selected
12 : CEIPSEL_12
Channel 12 selected
13 : CEIPSEL_13
Channel 13 selected
14 : CEIPSEL_14
Channel 14 selected
15 : CEIPSEL_15
Channel 15 selected
End of enumeration elements list.
CEIPEN : Channel input enable for the V+ terminal
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CEIPEN_0
Selected analog input channel for V+ terminal is disabled
1 : CEIPEN_1
Selected analog input channel for V+ terminal is enabled
End of enumeration elements list.
CEIMSEL : Channel input selected for the - terminal
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : CEIMSEL_0
Channel 0 selected
1 : CEIMSEL_1
Channel 1 selected
2 : CEIMSEL_2
Channel 2 selected
3 : CEIMSEL_3
Channel 3 selected
4 : CEIMSEL_4
Channel 4 selected
5 : CEIMSEL_5
Channel 5 selected
6 : CEIMSEL_6
Channel 6 selected
7 : CEIMSEL_7
Channel 7 selected
8 : CEIMSEL_8
Channel 8 selected
9 : CEIMSEL_9
Channel 9 selected
10 : CEIMSEL_10
Channel 10 selected
11 : CEIMSEL_11
Channel 11 selected
12 : CEIMSEL_12
Channel 12 selected
13 : CEIMSEL_13
Channel 13 selected
14 : CEIMSEL_14
Channel 14 selected
15 : CEIMSEL_15
Channel 15 selected
End of enumeration elements list.
CEIMEN : Channel input enable for the - terminal
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CEIMEN_0
Selected analog input channel for V- terminal is disabled
1 : CEIMEN_1
Selected analog input channel for V- terminal is enabled
End of enumeration elements list.
Comparator Control Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEOUT : Comparator output value
bits : 0 - 0 (1 bit)
access : read-write
CEOUTPOL : Comparator output polarity
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CEOUTPOL_0
Noninverted
1 : CEOUTPOL_1
Inverted
End of enumeration elements list.
CEF : Comparator output filter
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : CEF_0
Comparator output is not filtered
1 : CEF_1
Comparator output is filtered
End of enumeration elements list.
CEIES : Interrupt edge select for CEIIFG and CEIFG
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CEIES_0
Rising edge for CEIFG, falling edge for CEIIFG
1 : CEIES_1
Falling edge for CEIFG, rising edge for CEIIFG
End of enumeration elements list.
CESHORT : Input short
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CESHORT_0
Inputs not shorted
1 : CESHORT_1
Inputs shorted
End of enumeration elements list.
CEEX : Exchange
bits : 5 - 5 (1 bit)
access : read-write
CEFDLY : Filter delay
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : CEFDLY_0
Typical filter delay of TBD (450) ns
1 : CEFDLY_1
Typical filter delay of TBD (900) ns
2 : CEFDLY_2
Typical filter delay of TBD (1800) ns
3 : CEFDLY_3
Typical filter delay of TBD (3600) ns
End of enumeration elements list.
CEPWRMD : Power Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : CEPWRMD_0
High-speed mode
1 : CEPWRMD_1
Normal mode
2 : CEPWRMD_2
Ultra-low power mode
End of enumeration elements list.
CEON : Comparator On
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : CEON_0
Off
1 : CEON_1
On
End of enumeration elements list.
CEMRVL : This bit is valid of CEMRVS is set to 1
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CEMRVL_0
VREF0 is selected if CERS = 00, 01, or 10
1 : CEMRVL_1
VREF1 is selected if CERS = 00, 01, or 10
End of enumeration elements list.
CEMRVS : This bit defines if the comparator output selects between VREF0 or VREF1 if CERS = 00, 01, or 10.
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CEMRVS_0
Comparator output state selects between VREF0 or VREF1
1 : CEMRVS_1
CEMRVL selects between VREF0 or VREF1
End of enumeration elements list.
Comparator Control Register 2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEREF0 : Reference resistor tap 0
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0 : CEREF0_0
Reference resistor tap for setting 0.
1 : CEREF0_1
Reference resistor tap for setting 1.
2 : CEREF0_2
Reference resistor tap for setting 2.
3 : CEREF0_3
Reference resistor tap for setting 3.
4 : CEREF0_4
Reference resistor tap for setting 4.
5 : CEREF0_5
Reference resistor tap for setting 5.
6 : CEREF0_6
Reference resistor tap for setting 6.
7 : CEREF0_7
Reference resistor tap for setting 7.
8 : CEREF0_8
Reference resistor tap for setting 8.
9 : CEREF0_9
Reference resistor tap for setting 9.
10 : CEREF0_10
Reference resistor tap for setting 10.
11 : CEREF0_11
Reference resistor tap for setting 11.
12 : CEREF0_12
Reference resistor tap for setting 12.
13 : CEREF0_13
Reference resistor tap for setting 13.
14 : CEREF0_14
Reference resistor tap for setting 14.
15 : CEREF0_15
Reference resistor tap for setting 15.
16 : CEREF0_16
Reference resistor tap for setting 16.
17 : CEREF0_17
Reference resistor tap for setting 17.
18 : CEREF0_18
Reference resistor tap for setting 18.
19 : CEREF0_19
Reference resistor tap for setting 19.
20 : CEREF0_20
Reference resistor tap for setting 20.
21 : CEREF0_21
Reference resistor tap for setting 21.
22 : CEREF0_22
Reference resistor tap for setting 22.
23 : CEREF0_23
Reference resistor tap for setting 23.
24 : CEREF0_24
Reference resistor tap for setting 24.
25 : CEREF0_25
Reference resistor tap for setting 25.
26 : CEREF0_26
Reference resistor tap for setting 26.
27 : CEREF0_27
Reference resistor tap for setting 27.
28 : CEREF0_28
Reference resistor tap for setting 28.
29 : CEREF0_29
Reference resistor tap for setting 29.
30 : CEREF0_30
Reference resistor tap for setting 30.
31 : CEREF0_31
Reference resistor tap for setting 31.
End of enumeration elements list.
CERSEL : Reference select
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : CERSEL_0
When CEEX = 0, VREF is applied to the V+ terminal When CEEX = 1, VREF is applied to the V- terminal
1 : CERSEL_1
When CEEX = 0, VREF is applied to the V- terminal When CEEX = 1, VREF is applied to the V+ terminal
End of enumeration elements list.
CERS : Reference source
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : CERS_0
No current is drawn by the reference circuitry
1 : CERS_1
VCC applied to the resistor ladder
2 : CERS_2
Shared reference voltage applied to the resistor ladder
3 : CERS_3
Shared reference voltage supplied to V(CREF). Resistor ladder is off
End of enumeration elements list.
CEREF1 : Reference resistor tap 1
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : CEREF1_0
Reference resistor tap for setting 0.
1 : CEREF1_1
Reference resistor tap for setting 1.
2 : CEREF1_2
Reference resistor tap for setting 2.
3 : CEREF1_3
Reference resistor tap for setting 3.
4 : CEREF1_4
Reference resistor tap for setting 4.
5 : CEREF1_5
Reference resistor tap for setting 5.
6 : CEREF1_6
Reference resistor tap for setting 6.
7 : CEREF1_7
Reference resistor tap for setting 7.
8 : CEREF1_8
Reference resistor tap for setting 8.
9 : CEREF1_9
Reference resistor tap for setting 9.
10 : CEREF1_10
Reference resistor tap for setting 10.
11 : CEREF1_11
Reference resistor tap for setting 11.
12 : CEREF1_12
Reference resistor tap for setting 12.
13 : CEREF1_13
Reference resistor tap for setting 13.
14 : CEREF1_14
Reference resistor tap for setting 14.
15 : CEREF1_15
Reference resistor tap for setting 15.
16 : CEREF1_16
Reference resistor tap for setting 16.
17 : CEREF1_17
Reference resistor tap for setting 17.
18 : CEREF1_18
Reference resistor tap for setting 18.
19 : CEREF1_19
Reference resistor tap for setting 19.
20 : CEREF1_20
Reference resistor tap for setting 20.
21 : CEREF1_21
Reference resistor tap for setting 21.
22 : CEREF1_22
Reference resistor tap for setting 22.
23 : CEREF1_23
Reference resistor tap for setting 23.
24 : CEREF1_24
Reference resistor tap for setting 24.
25 : CEREF1_25
Reference resistor tap for setting 25.
26 : CEREF1_26
Reference resistor tap for setting 26.
27 : CEREF1_27
Reference resistor tap for setting 27.
28 : CEREF1_28
Reference resistor tap for setting 28.
29 : CEREF1_29
Reference resistor tap for setting 29.
30 : CEREF1_30
Reference resistor tap for setting 30.
31 : CEREF1_31
Reference resistor tap for setting 31.
End of enumeration elements list.
CEREFL : Reference voltage level
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0 : CEREFL_0
Reference amplifier is disabled. No reference voltage is requested
1 : CEREFL_1
1.2 V is selected as shared reference voltage input
2 : CEREFL_2
2.0 V is selected as shared reference voltage input
3 : CEREFL_3
2.5 V is selected as shared reference voltage input
End of enumeration elements list.
CEREFACC : Reference accuracy
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CEREFACC_0
Static mode
1 : CEREFACC_1
Clocked (low power, low accuracy) mode
End of enumeration elements list.
Comparator Control Register 3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEPD0 : Port disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CEPD0_0
The input buffer is enabled
1 : CEPD0_1
The input buffer is disabled
End of enumeration elements list.
CEPD1 : Port disable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CEPD1_0
The input buffer is enabled
1 : CEPD1_1
The input buffer is disabled
End of enumeration elements list.
CEPD2 : Port disable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : CEPD2_0
The input buffer is enabled
1 : CEPD2_1
The input buffer is disabled
End of enumeration elements list.
CEPD3 : Port disable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CEPD3_0
The input buffer is enabled
1 : CEPD3_1
The input buffer is disabled
End of enumeration elements list.
CEPD4 : Port disable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CEPD4_0
The input buffer is enabled
1 : CEPD4_1
The input buffer is disabled
End of enumeration elements list.
CEPD5 : Port disable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : CEPD5_0
The input buffer is enabled
1 : CEPD5_1
The input buffer is disabled
End of enumeration elements list.
CEPD6 : Port disable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CEPD6_0
The input buffer is enabled
1 : CEPD6_1
The input buffer is disabled
End of enumeration elements list.
CEPD7 : Port disable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CEPD7_0
The input buffer is enabled
1 : CEPD7_1
The input buffer is disabled
End of enumeration elements list.
CEPD8 : Port disable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CEPD8_0
The input buffer is enabled
1 : CEPD8_1
The input buffer is disabled
End of enumeration elements list.
CEPD9 : Port disable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : CEPD9_0
The input buffer is enabled
1 : CEPD9_1
The input buffer is disabled
End of enumeration elements list.
CEPD10 : Port disable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : CEPD10_0
The input buffer is enabled
1 : CEPD10_1
The input buffer is disabled
End of enumeration elements list.
CEPD11 : Port disable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CEPD11_0
The input buffer is enabled
1 : CEPD11_1
The input buffer is disabled
End of enumeration elements list.
CEPD12 : Port disable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CEPD12_0
The input buffer is enabled
1 : CEPD12_1
The input buffer is disabled
End of enumeration elements list.
CEPD13 : Port disable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : CEPD13_0
The input buffer is enabled
1 : CEPD13_1
The input buffer is disabled
End of enumeration elements list.
CEPD14 : Port disable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CEPD14_0
The input buffer is enabled
1 : CEPD14_1
The input buffer is disabled
End of enumeration elements list.
CEPD15 : Port disable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : CEPD15_0
The input buffer is enabled
1 : CEPD15_1
The input buffer is disabled
End of enumeration elements list.
Comparator Interrupt Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CEIFG : Comparator output interrupt flag
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CEIFG_0
No interrupt pending
1 : CEIFG_1
Interrupt pending
End of enumeration elements list.
CEIIFG : Comparator output inverted interrupt flag
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : CEIIFG_0
No interrupt pending
1 : CEIIFG_1
Interrupt pending
End of enumeration elements list.
CERDYIFG : Comparator ready interrupt flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CERDYIFG_0
No interrupt pending
1 : CERDYIFG_1
Interrupt pending
End of enumeration elements list.
CEIE : Comparator output interrupt enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CEIE_0
Interrupt disabled
1 : CEIE_1
Interrupt enabled
End of enumeration elements list.
CEIIE : Comparator output interrupt enable inverted polarity
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : CEIIE_0
Interrupt disabled
1 : CEIIE_1
Interrupt enabled
End of enumeration elements list.
CERDYIE : Comparator ready interrupt enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : CERDYIE_0
Interrupt disabled
1 : CERDYIE_1
Interrupt enabled
End of enumeration elements list.
Comparator Interrupt Vector Word Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CEIV : Comparator interrupt vector word register
bits : 0 - 15 (16 bit)
access : read-only
Enumeration: CEIV_enum_read ( read )
0 : CEIV_0
No interrupt pending
2 : CEIV_2
Interrupt Source: CEOUT interrupt Interrupt Flag: CEIFG Interrupt Priority: Highest
4 : CEIV_4
Interrupt Source: CEOUT interrupt inverted polarity Interrupt Flag: CEIIFG
10 : CEIV_10
Interrupt Source: Comparator ready interrupt Interrupt Flag: CERDYIFG Interrupt Priority: Lowest
End of enumeration elements list.
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