\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
ITM Stimulus Port 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 7
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 8
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 9
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 10
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 11
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 12
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 13
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 14
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 15
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 16
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 17
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 18
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 19
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 20
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 21
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 22
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 23
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 24
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 25
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 26
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 27
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 28
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 29
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 30
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 31
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Stimulus Port 3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM Trace Enable Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMENA : Bit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.
bits : 0 - 31 (32 bit)
access : read-write
ITM Trace Privilege Register
address_offset : 0xE40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIVMASK : Bit mask to enable tracing on ITM stimulus ports: bit [0] = stimulus ports [7:0], bit [1] = stimulus ports [15:8], bit [2] = stimulus ports [23:16], bit [3] = stimulus ports [31:24].
bits : 0 - 3 (4 bit)
access : read-write
ITM Trace Control Register
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITMENA : Enable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.
bits : 0 - 0 (1 bit)
access : read-write
TSENA : Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows. Timestamps are emitted during idle times after a fixed number of two million cycles. This provides a time reference for packets and inter-packet gaps. If SWOENA (bit [4]) is set, timestamps are triggered by activity on the internal trace bus only. In this case there is no regular timestamp output when the ITM is idle.
bits : 1 - 1 (1 bit)
access : read-write
SYNCENA : Enables sync packets for TPIU.
bits : 2 - 2 (1 bit)
access : read-write
DWTENA : Enables the DWT stimulus.
bits : 3 - 3 (1 bit)
access : read-write
SWOENA : Enables asynchronous clocking of the timestamp counter.
bits : 4 - 4 (1 bit)
access : read-write
TSPRESCALE : TSPrescale Timestamp prescaler.
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : en_0b00
no prescaling
1 : en_0b01
divide by 4
2 : en_0b10
divide by 16
3 : en_0b11
divide by 64
End of enumeration elements list.
ATBID : ATB ID for CoreSight system.
bits : 16 - 22 (7 bit)
access : read-write
BUSY : Set when ITM events present and being drained.
bits : 23 - 23 (1 bit)
access : read-write
ITM Integration Write Register
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ATVALIDM : When the integration mode is set: 0 = ATVALIDM clear. 1 = ATVALIDM set.
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
0 : en_0b0
ATVALIDM clear
1 : en_0b1
ATVALIDM set
End of enumeration elements list.
ITM Integration Mode Control Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTEGRATION :
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
ATVALIDM normal
1 : en_0b1
ATVALIDM driven from Integration Write Register
End of enumeration elements list.
ITM Lock Access Register
address_offset : 0xFB0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LOCK_ACCESS : A privileged write of 0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC. An invalid write removes write access.
bits : 0 - 31 (32 bit)
access : write-only
ITM Lock Status Register
address_offset : 0xFB4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PRESENT : Indicates that a lock mechanism exists for this component.
bits : 0 - 0 (1 bit)
access : read-only
ACCESS : Write access to component is blocked. All writes are ignored, reads are permitted.
bits : 1 - 1 (1 bit)
access : read-only
BYTEACC : You cannot implement 8-bit lock accesses.
bits : 2 - 2 (1 bit)
access : read-only
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