Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable SysTick counter
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : First
Counter disabled
End of enumeration elements list.
TICKINT :
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : VAL_0
Counting down to zero does not pend the SysTick handler. Software can use COUNTFLAG to determine if the SysTick handler has ever counted to zero.
1 : VAL_1
Counting down to zero pends the SysTick handler.
End of enumeration elements list.
CLKSOURCE : Clock source.
bits : 2 - 2 (1 bit)
access : read-only
Enumeration: CLKSOURCE_enum_read ( read )
0 : VAL_0
Not applicable
1 : VAL_1
Core clock
End of enumeration elements list.
COUNTFLAG : Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.
bits : 16 - 16 (1 bit)
access : read-only
Irq 0 to 31 Set Enable Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields.
bits : 0 - 31 (32 bit)
access : read-write
Irq 32 to 63 Set Enable Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : Writing 0 to a SETENA bit has no effect, writing 1 to a bit enables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the SETENA fields.
bits : 0 - 31 (32 bit)
access : read-write
SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Value to load into the SysTick Current Value Register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
bits : 0 - 23 (24 bit)
access : read-write
Irq 0 to 31 Clear Enable Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field.
bits : 0 - 31 (32 bit)
access : read-write
Irq 32 to 63 Clear Enable Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : Writing 0 to a CLRENA bit has no effect, writing 1 to a bit disables the corresponding interrupt. Reading the bit returns its current enable state. Reset clears the CLRENA field.
bits : 0 - 31 (32 bit)
access : read-write
SysTick Calibration Value Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TENMS : Reads as zero. Indicates calibration value is not known.
bits : 0 - 23 (24 bit)
access : read-only
SKEW : Reads as one. The calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.
bits : 30 - 30 (1 bit)
access : read-only
NOREF : Reads as one. Indicates that no separate reference clock is provided.
bits : 31 - 31 (1 bit)
access : read-only
Irq 0 to 31 Set Pending Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state.
bits : 0 - 31 (32 bit)
access : read-write
Irq 32 to 63 Set Pending Register
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : Writing 0 to a SETPEND bit has no effect, writing 1 to a bit pends the corresponding interrupt. Reading the bit returns its current state.
bits : 0 - 31 (32 bit)
access : read-write
Irq 0 to 31 Clear Pending Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state.
bits : 0 - 31 (32 bit)
access : read-write
Irq 32 to 63 Clear Pending Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : Writing 0 to a CLRPEND bit has no effect, writing 1 to a bit clears the corresponding pending interrupt. Reading the bit returns its current state.
bits : 0 - 31 (32 bit)
access : read-write
Irq 0 to 31 Active Bit Register
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked.
bits : 0 - 31 (32 bit)
access : read-only
Irq 32 to 63 Active Bit Register
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : Interrupt active flags. Reading 0 implies the interrupt is not active or stacked. Reading 1 implies the interrupt is active or pre-empted and stacked.
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Control Type Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
INTLINESNUM : Total number of interrupt lines in groups of 32.
bits : 0 - 4 (5 bit)
access : read-only
Irq 0 to 3 Priority Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_0 : Priority of interrupt 0
bits : 0 - 7 (8 bit)
access : read-write
PRI_1 : Priority of interrupt 1
bits : 8 - 15 (8 bit)
access : read-write
PRI_2 : Priority of interrupt 2
bits : 16 - 23 (8 bit)
access : read-write
PRI_3 : Priority of interrupt 3
bits : 24 - 31 (8 bit)
access : read-write
Irq 4 to 7 Priority Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of interrupt 4
bits : 0 - 7 (8 bit)
access : read-write
PRI_5 : Priority of interrupt 5
bits : 8 - 15 (8 bit)
access : read-write
PRI_6 : Priority of interrupt 6
bits : 16 - 23 (8 bit)
access : read-write
PRI_7 : Priority of interrupt 7
bits : 24 - 31 (8 bit)
access : read-write
Irq 8 to 11 Priority Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority of interrupt 8
bits : 0 - 7 (8 bit)
access : read-write
PRI_9 : Priority of interrupt 9
bits : 8 - 15 (8 bit)
access : read-write
PRI_10 : Priority of interrupt 10
bits : 16 - 23 (8 bit)
access : read-write
PRI_11 : Priority of interrupt 11
bits : 24 - 31 (8 bit)
access : read-write
Irq 12 to 15 Priority Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of interrupt 12
bits : 0 - 7 (8 bit)
access : read-write
PRI_13 : Priority of interrupt 13
bits : 8 - 15 (8 bit)
access : read-write
PRI_14 : Priority of interrupt 14
bits : 16 - 23 (8 bit)
access : read-write
PRI_15 : Priority of interrupt 15
bits : 24 - 31 (8 bit)
access : read-write
Irq 16 to 19 Priority Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_16 : Priority of interrupt 16
bits : 0 - 7 (8 bit)
access : read-write
PRI_17 : Priority of interrupt 17
bits : 8 - 15 (8 bit)
access : read-write
PRI_18 : Priority of interrupt 18
bits : 16 - 23 (8 bit)
access : read-write
PRI_19 : Priority of interrupt 19
bits : 24 - 31 (8 bit)
access : read-write
Irq 20 to 23 Priority Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_20 : Priority of interrupt 20
bits : 0 - 7 (8 bit)
access : read-write
PRI_21 : Priority of interrupt 21
bits : 8 - 15 (8 bit)
access : read-write
PRI_22 : Priority of interrupt 22
bits : 16 - 23 (8 bit)
access : read-write
PRI_23 : Priority of interrupt 23
bits : 24 - 31 (8 bit)
access : read-write
Irq 24 to 27 Priority Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_24 : Priority of interrupt 24
bits : 0 - 7 (8 bit)
access : read-write
PRI_25 : Priority of interrupt 25
bits : 8 - 15 (8 bit)
access : read-write
PRI_26 : Priority of interrupt 26
bits : 16 - 23 (8 bit)
access : read-write
PRI_27 : Priority of interrupt 27
bits : 24 - 31 (8 bit)
access : read-write
Irq 28 to 31 Priority Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_28 : Priority of interrupt 28
bits : 0 - 7 (8 bit)
access : read-write
PRI_29 : Priority of interrupt 29
bits : 8 - 15 (8 bit)
access : read-write
PRI_30 : Priority of interrupt 30
bits : 16 - 23 (8 bit)
access : read-write
PRI_31 : Priority of interrupt 31
bits : 24 - 31 (8 bit)
access : read-write
Irq 32 to 35 Priority Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_32 : Priority of interrupt 32
bits : 0 - 7 (8 bit)
access : read-write
PRI_33 : Priority of interrupt 33
bits : 8 - 15 (8 bit)
access : read-write
PRI_34 : Priority of interrupt 34
bits : 16 - 23 (8 bit)
access : read-write
PRI_35 : Priority of interrupt 35
bits : 24 - 31 (8 bit)
access : read-write
Irq 36 to 39 Priority Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_36 : Priority of interrupt 36
bits : 0 - 7 (8 bit)
access : read-write
PRI_37 : Priority of interrupt 37
bits : 8 - 15 (8 bit)
access : read-write
PRI_38 : Priority of interrupt 38
bits : 16 - 23 (8 bit)
access : read-write
PRI_39 : Priority of interrupt 39
bits : 24 - 31 (8 bit)
access : read-write
Irq 40 to 43 Priority Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_40 : Priority of interrupt 40
bits : 0 - 7 (8 bit)
access : read-write
PRI_41 : Priority of interrupt 41
bits : 8 - 15 (8 bit)
access : read-write
PRI_42 : Priority of interrupt 42
bits : 16 - 23 (8 bit)
access : read-write
PRI_43 : Priority of interrupt 43
bits : 24 - 31 (8 bit)
access : read-write
Irq 44 to 47 Priority Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_44 : Priority of interrupt 44
bits : 0 - 7 (8 bit)
access : read-write
PRI_45 : Priority of interrupt 45
bits : 8 - 15 (8 bit)
access : read-write
PRI_46 : Priority of interrupt 46
bits : 16 - 23 (8 bit)
access : read-write
PRI_47 : Priority of interrupt 47
bits : 24 - 31 (8 bit)
access : read-write
Irq 48 to 51 Priority Register
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_48 : Priority of interrupt 48
bits : 0 - 7 (8 bit)
access : read-write
PRI_49 : Priority of interrupt 49
bits : 8 - 15 (8 bit)
access : read-write
PRI_50 : Priority of interrupt 50
bits : 16 - 23 (8 bit)
access : read-write
PRI_51 : Priority of interrupt 51
bits : 24 - 31 (8 bit)
access : read-write
Irq 52 to 55 Priority Register
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_52 : Priority of interrupt 52
bits : 0 - 7 (8 bit)
access : read-write
PRI_53 : Priority of interrupt 53
bits : 8 - 15 (8 bit)
access : read-write
PRI_54 : Priority of interrupt 54
bits : 16 - 23 (8 bit)
access : read-write
PRI_55 : Priority of interrupt 55
bits : 24 - 31 (8 bit)
access : read-write
Irq 56 to 59 Priority Register
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_56 : Priority of interrupt 56
bits : 0 - 7 (8 bit)
access : read-write
PRI_57 : Priority of interrupt 57
bits : 8 - 15 (8 bit)
access : read-write
PRI_58 : Priority of interrupt 58
bits : 16 - 23 (8 bit)
access : read-write
PRI_59 : Priority of interrupt 59
bits : 24 - 31 (8 bit)
access : read-write
Irq 60 to 63 Priority Register
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_60 : Priority of interrupt 60
bits : 0 - 7 (8 bit)
access : read-write
PRI_61 : Priority of interrupt 61
bits : 8 - 15 (8 bit)
access : read-write
PRI_62 : Priority of interrupt 62
bits : 16 - 23 (8 bit)
access : read-write
PRI_63 : Priority of interrupt 63
bits : 24 - 31 (8 bit)
access : read-write
Auxiliary Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISMCYCINT : Disables interruption of multi-cycle instructions. This increases the interrupt latency of the processor becuase LDM/STM completes before interrupt stacking occurs.
bits : 0 - 0 (1 bit)
access : read-write
DISDEFWBUF : Disables write buffer us during default memorty map accesses. This causes all bus faults to be precise bus faults but decreases the performance of the processor because the stores to memory have to complete before the next instruction can be executed.
bits : 1 - 1 (1 bit)
access : read-write
DISFOLD : Disables IT folding.
bits : 2 - 2 (1 bit)
access : read-write
DISFPCA : Disable automatic update of CONTROL.FPCA
bits : 8 - 8 (1 bit)
access : read-write
DISOOFP : Disables floating point instructions completing out of order with respect to integer instructions.
bits : 9 - 9 (1 bit)
access : read-write
CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
REVISION : Implementation defined revision number.
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : Number of processor within family.
bits : 4 - 15 (12 bit)
access : read-only
CONSTANT : Reads as 0xC
bits : 16 - 19 (4 bit)
access : read-only
VARIANT : Implementation defined variant number.
bits : 20 - 23 (4 bit)
access : read-only
IMPLEMENTER : Implementor code.
bits : 24 - 31 (8 bit)
access : read-only
Interrupt Control State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active ISR number field. Reset clears the VECTACTIVE field.
bits : 0 - 8 (9 bit)
access : read-only
RETTOBASE : This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set.
bits : 11 - 11 (1 bit)
access : read-only
VECTPENDING : Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR.
bits : 12 - 17 (6 bit)
access : read-only
ISRPENDING : Interrupt pending flag. Excludes NMI and faults.
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
interrupt not pending
1 : en_0b1
interrupt pending
End of enumeration elements list.
ISRPREEMPT : You must only use this at debug time. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
a pending exception is not serviced.
1 : en_0b1
a pending exception is serviced on exit from the debug halt state
End of enumeration elements list.
PENDSTCLR : Clear pending SysTick bit
bits : 25 - 25 (1 bit)
access : write-only
Enumeration:
0 : en_0b0
do not clear pending SysTick
1 : en_0b1
clear pending SysTick
End of enumeration elements list.
PENDSTSET : Set a pending SysTick bit.
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
do not set pending SysTick
1 : en_0b1
set pending SysTick
End of enumeration elements list.
PENDSVCLR : Clear pending pendSV bit
bits : 27 - 27 (1 bit)
access : write-only
Enumeration:
0 : en_0b0
do not clear pending pendSV
1 : en_0b1
clear pending pendSV
End of enumeration elements list.
PENDSVSET : Set pending pendSV bit.
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
do not set pending pendSV
1 : en_0b1
set pending PendSV
End of enumeration elements list.
NMIPENDSET : Set pending NMI bit. NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
do not set pending NMI
1 : en_0b1
set pending NMI
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space.
bits : 7 - 28 (22 bit)
access : read-write
TBLBASE : Table base is in Code (0) or RAM (1).
bits : 29 - 29 (1 bit)
access : read-write
Application Interrupt/Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : System Reset bit. Resets the system, with the exception of debug components. The VECTRESET bit self-clears. Reset clears the VECTRESET bit. For debugging, only write this bit when the core is halted.
bits : 0 - 0 (1 bit)
access : write-only
VECTCLRACTIVE : Clears all active state information for active NMI, fault, and interrupts. It is the responsibility of the application to reinitialize the stack. The VECTCLRACTIVE bit is for returning to a known state during debug. The VECTCLRACTIVE bit self-clears. IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.
bits : 1 - 1 (1 bit)
access : write-only
SYSRESETREQ : Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running.
bits : 2 - 2 (1 bit)
access : write-only
PRIGROUP : Interrupt priority grouping field. The PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices
bits : 8 - 10 (3 bit)
access : read-write
ENDIANESS : Data endianness bit. ENDIANNESS is sampled from the BIGEND input port during reset. You cannot change ENDIANNESS outside of reset.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
little endian
1 : en_0b1
big endian
End of enumeration elements list.
VECTKEY : Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored.
bits : 16 - 31 (16 bit)
access : write-only
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
do not sleep when returning to thread mode
1 : en_0b1
sleep on ISR exit
End of enumeration elements list.
SLEEPDEEP : Sleep deep bit.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
not OK to turn off system clock
1 : en_0b1
indicates to the system that Cortex-M4 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped.
End of enumeration elements list.
SEVONPEND : When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE.
bits : 4 - 4 (1 bit)
access : read-write
Configuration Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHREDENA : When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value.
bits : 0 - 0 (1 bit)
access : read-write
USERSETMPEND : If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.
bits : 1 - 1 (1 bit)
access : read-write
UNALIGN_TRP : Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED.
bits : 3 - 3 (1 bit)
access : read-write
DIV_0_TRP : Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO.
bits : 4 - 4 (1 bit)
access : read-write
BFHFNMIGN : When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored therefore you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them.
bits : 8 - 8 (1 bit)
access : read-write
STKALIGN : Stack alignment bit.
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
Only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.
1 : en_0b1
On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return.
End of enumeration elements list.
System Handlers 4-7 Priority Register
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of system handler 4.
bits : 0 - 7 (8 bit)
access : read-write
PRI_5 : Priority of system handler 5.
bits : 8 - 15 (8 bit)
access : read-write
PRI_6 : Priority of system handler 6.
bits : 16 - 23 (8 bit)
access : read-write
PRI_7 : Priority of system handler 7.
bits : 24 - 31 (8 bit)
access : read-write
System Handlers 8-11 Priority Register
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Priority of system handler 8.
bits : 0 - 7 (8 bit)
access : read-write
PRI_9 : Priority of system handler 9.
bits : 8 - 15 (8 bit)
access : read-write
PRI_10 : Priority of system handler 10.
bits : 16 - 23 (8 bit)
access : read-write
PRI_11 : Priority of system handler 11.
bits : 24 - 31 (8 bit)
access : read-write
System Handlers 12-15 Priority Register
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of system handler 12.
bits : 0 - 7 (8 bit)
access : read-write
PRI_13 : Priority of system handler 13.
bits : 8 - 15 (8 bit)
access : read-write
PRI_14 : Priority of system handler 14.
bits : 16 - 23 (8 bit)
access : read-write
PRI_15 : Priority of system handler 15.
bits : 24 - 31 (8 bit)
access : read-write
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : MemManage active flag.
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
BUSFAULTACT : BusFault active flag.
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
USGFAULTACT : UsageFault active flag.
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
SVCALLACT : SVCall active flag.
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
MONITORACT : the Monitor active flag.
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
PENDSVACT : PendSV active flag.
bits : 10 - 10 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
SYSTICKACT : SysTick active flag.
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not active
1 : en_0b1
active
End of enumeration elements list.
USGFAULTPENDED : usage fault pended flag.
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not pended
1 : en_0b1
pended
End of enumeration elements list.
MEMFAULTPENDED : MemManage pended flag.
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not pended
1 : en_0b1
pended
End of enumeration elements list.
BUSFAULTPENDED : BusFault pended flag.
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not pended
1 : en_0b1
pended
End of enumeration elements list.
SVCALLPENDED : SVCall pended flag.
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : en_0b0
not pended
1 : en_0b1
pended
End of enumeration elements list.
MEMFAULTENA : MemManage fault system handler enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
disabled
1 : en_0b1
enabled
End of enumeration elements list.
BUSFAULTENA : Bus fault system handler enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
disabled
1 : en_0b1
enabled
End of enumeration elements list.
USGFAULTENA : Usage fault system handler enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
disabled
1 : en_0b1
enabled
End of enumeration elements list.
Configurable Fault Status Registers
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL : Instruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written.
bits : 0 - 0 (1 bit)
access : read-write
DACCVIOL : Data access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access.
bits : 1 - 1 (1 bit)
access : read-write
MUNSTKERR : Unstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written.
bits : 3 - 3 (1 bit)
access : read-write
MSTKERR : Stacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written.
bits : 4 - 4 (1 bit)
access : read-write
MLSPERR : Indicates if MemManage fault occurred during FP lazy state preservation.
bits : 5 - 5 (1 bit)
access : read-write
MMARVALID : Memory Manage Address Register (MMAR) address valid flag. A later-arriving fault, such as a bus fault, can clear a memory manage fault.. If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten.
bits : 7 - 7 (1 bit)
access : read-write
IBUSERR : Instruction bus error flag. The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written.
bits : 8 - 8 (1 bit)
access : read-write
PRECISERR : Precise data bus error return.
bits : 9 - 9 (1 bit)
access : read-write
IMPRECISERR : Imprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written.
bits : 10 - 10 (1 bit)
access : read-write
UNSTKERR : Unstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written.
bits : 11 - 11 (1 bit)
access : read-write
STKERR : Stacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written.
bits : 12 - 12 (1 bit)
access : read-write
LSPERR : Indicates if bus fault occurred during FP lazy state preservation.
bits : 13 - 13 (1 bit)
access : read-write
BFARVALID : This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later. If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.
bits : 15 - 15 (1 bit)
access : read-write
UNDEFINSTR : The UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.
bits : 16 - 16 (1 bit)
access : read-write
INVSTATE : Invalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state.
bits : 17 - 17 (1 bit)
access : read-write
INVPC : Attempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.
bits : 18 - 18 (1 bit)
access : read-write
NOCP : Attempt to use a coprocessor instruction. The processor does not support coprocessor instructions.
bits : 19 - 19 (1 bit)
access : read-write
UNALIGNED : When UNALIGN_TRP is enabled (see Configuration Control Register on page 8-26), and there is an attempt to make an unaligned memory access, then this fault occurs. Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
bits : 24 - 24 (1 bit)
access : read-write
DIVBYZERO : When DIV_0_TRP (see Configuration Control Register on page 8-26) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0.
bits : 25 - 25 (1 bit)
access : read-write
Hard Fault Status Register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.
bits : 1 - 1 (1 bit)
access : read-write
FORCED : Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause.
bits : 30 - 30 (1 bit)
access : read-write
DEBUGEVT : This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.
bits : 31 - 31 (1 bit)
access : read-write
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : Halt request flag. The processor is halted on the next instruction.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
no halt request
1 : en_0b1
halt requested by NVIC, including step
End of enumeration elements list.
BKPT : BKPT flag. The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
no BKPT instruction execution
1 : en_0b1
BKPT instruction execution
End of enumeration elements list.
DWTTRAP : Data Watchpoint and Trace (DWT) flag. The processor stops at the current instruction or at the next instruction.
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
no DWT match
1 : en_0b1
DWT match
End of enumeration elements list.
VCATCH : Vector catch flag. When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
no vector catch occurred
1 : en_0b1
vector catch occurred
End of enumeration elements list.
EXTERNAL : External debug request flag. The processor stops on next instruction boundary.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
EDBGRQ signal not asserted
1 : en_0b1
EDBGRQ signal asserted
End of enumeration elements list.
Mem Manage Fault Address Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault
bits : 0 - 31 (32 bit)
access : read-write
Bus Fault Address Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault
bits : 0 - 31 (32 bit)
access : read-write
Auxiliary Fault Status Register
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMPDEF : Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs.
bits : 0 - 31 (32 bit)
access : read-write
Processor Feature register0
address_offset : 0xD40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
STATE0 : State0 (T-bit == 0)
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no ARM encoding
1 : en_0b0001
N/A
End of enumeration elements list.
STATE1 : State1 (T-bit == 1)
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
N/A
1 : en_0b0001
N/A
2 : en_0b0010
Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL but no other 32-bit basic instructions (Note non-basic 32-bit instructions can be added using the appropriate instruction attribute, but other 32-bit basic instructions cannot.)
3 : en_0b0011
Thumb-2 encoding with all Thumb-2 basic instructions
End of enumeration elements list.
Processor Feature register1
address_offset : 0xD44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MICROCONTROLLER_PROGRAMMERS_MODEL : Microcontroller programmer's model
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
not supported
2 : en_0b0010
two-stack support
End of enumeration elements list.
Debug Feature register0
address_offset : 0xD48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MICROCONTROLLER_DEBUG_MODEL : Microcontroller Debug Model - memory mapped
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
not supported
1 : en_0b0001
Microcontroller debug v1 (ITMv1, DWTv1, optional ETM)
End of enumeration elements list.
Auxiliary Feature register0
address_offset : 0xD4C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature register0
address_offset : 0xD50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
PMSA_SUPPORT : PMSA support
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
not supported
1 : en_0b0001
IMPLEMENTATION DEFINED (N/A)
2 : en_0b0010
PMSA base (features as defined for ARMv6) (N/A)
3 : en_0b0011
PMSAv7 (base plus subregion support)
End of enumeration elements list.
CACHE_COHERENCE_SUPPORT : Cache coherence support
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no shared support
1 : en_0b0001
partial-inner-shared coherency (coherency amongst some - but not all - of the entities within an inner-coherent domain)
2 : en_0b0010
full-inner-shared coherency (coherency amongst all of the entities within an inner-coherent domain)
3 : en_0b0011
full coherency (coherency amongst all of the entities)
End of enumeration elements list.
OUTER_NON_SHARABLE_SUPPORT : Outer non-sharable support
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
Outer non-sharable not supported
1 : en_0b0001
Outer sharable supported
End of enumeration elements list.
AUXILIARY_REGISTER_SUPPORT : Auxiliary register support
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
not supported
1 : en_0b0001
Auxiliary control register
End of enumeration elements list.
Memory Model Feature register1
address_offset : 0xD54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Memory Model Feature register2
address_offset : 0xD58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WAIT_FOR_INTERRUPT_STALLING : wait for interrupt stalling
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
not supported
1 : en_0b0001
wait for interrupt supported
End of enumeration elements list.
Memory Model Feature register3
address_offset : 0xD5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ISA Feature register0
address_offset : 0xD60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BITCOUNT_INSTRS : BitCount instructions
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no bit-counting instructions present
1 : en_0b0001
adds CLZ
End of enumeration elements list.
BITFIELD_INSTRS : BitField instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no bitfield instructions present
1 : en_0b0001
adds BFC, BFI, SBFX, UBFX
End of enumeration elements list.
CMPBRANCH_INSTRS : CmpBranch instructions
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no combined compare-and-branch instructions present
1 : en_0b0001
adds CB{N}Z
End of enumeration elements list.
COPROC_INSTRS : Coprocessor instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no coprocessor support, other than for separately attributed architectures such as CP15 or VFP
1 : en_0b0001
adds generic CDP, LDC, MCR, MRC, STC
2 : en_0b0010
adds generic CDP2, LDC2, MCR2, MRC2, STC2
3 : en_0b0011
adds generic MCRR, MRRC
4 : en_0b0100
adds generic MCRR2, MRRC2
End of enumeration elements list.
DEBUG_INSTRS : Debug instructions
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no debug instructions present
1 : en_0b0001
adds BKPT
End of enumeration elements list.
DIVIDE_INSTRS : Divide instructions
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no divide instructions present
1 : en_0b0001
adds SDIV, UDIV (v1 quotient only result)
End of enumeration elements list.
ISA Feature register1
address_offset : 0xD64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
EXTEND_INSRS : Extend instructions. Note that the shift options on these instructions are also controlled by the WithShifts_instrs attribute.
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no scalar (i.e. non-SIMD) sign/zero-extend instructions present
1 : en_0b0001
adds SXTB, SXTH, UXTB, UXTH
2 : en_0b0010
N/A
End of enumeration elements list.
IFTHEN_INSTRS : IfThen instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
IT instructions not present
1 : en_0b0001
adds IT instructions (and IT bits in PSRs)
End of enumeration elements list.
IMMEDIATE_INSTRS : Immediate instructions
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no special immediate-generating instructions present
1 : en_0b0001
adds ADDW, MOVW, MOVT, SUBW
End of enumeration elements list.
INTERWORK_INSTRS : Interwork instructions
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no interworking instructions supported
1 : en_0b0001
adds BX (and T bit in PSRs)
2 : en_0b0010
adds BLX, and PC loads have BX-like behavior
3 : en_0b0011
N/A
End of enumeration elements list.
ISA Feature register2
address_offset : 0xD68 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LOADSTORE_INSTRS : LoadStore instructions
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no additional normal load/store instructions present
1 : en_0b0001
adds LDRD/STRD
End of enumeration elements list.
MEMHINT_INSTRS : MemoryHint instructions
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no memory hint instructions presen
1 : en_0b0001
adds PLD
2 : en_0b0010
adds PLD (ie a repeat on value 1)
3 : en_0b0011
adds PLI
End of enumeration elements list.
MULTIACCESSINT_INSTRS : Multi-Access interruptible instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
the (LDM/STM) instructions are non-interruptible
1 : en_0b0001
the (LDM/STM) instructions are restartable
2 : en_0b0010
the (LDM/STM) instructions are continuable
End of enumeration elements list.
MULT_INSTRS : Multiply instructions
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
only MUL present
1 : en_0b0001
adds MLA
2 : en_0b0010
adds MLS
End of enumeration elements list.
MULTS_INSTRS : Multiply instructions (advanced, signed)
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no signed multiply instructions present
1 : en_0b0001
adds SMULL, SMLAL
2 : en_0b0010
N/A
3 : en_0b0011
N/A
End of enumeration elements list.
MULTU_INSTRS : Multiply instructions (advanced, unsigned)
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no unsigned multiply instructions present
1 : en_0b0001
adds UMULL, UMLAL
2 : en_0b0010
N/A
End of enumeration elements list.
REVERSAL_INSTRS : Reversal instructions
bits : 28 - 31 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no reversal instructions present
1 : en_0b0001
adds REV, REV16, REVSH
2 : en_0b0010
adds RBIT
End of enumeration elements list.
ISA Feature register3
address_offset : 0xD6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SATRUATE_INSTRS : Saturate instructions
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no non-SIMD saturate instructions present
1 : en_0b0001
N/A
End of enumeration elements list.
SIMD_INSTRS : SIMD instructions
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no SIMD instructions present
1 : en_0b0001
adds SSAT, USAT (and the Q flag in the PSRs)
3 : en_0b0011
N/A
End of enumeration elements list.
SVC_INSTRS : SVC instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no SVC (SWI) instructions present
1 : en_0b0001
adds SVC (SWI)
End of enumeration elements list.
SYNCPRIM_INSTRS : SyncPrim instructions. Note there are no LDREXD or STREXD in ARMv7-M. This attribute is used in conjunction with the SyncPrim_instrs_frac attribute in ID_ISAR4[23:20].
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no synchronization primitives present
1 : en_0b0001
adds LDREX, STREX
2 : en_0b0010
adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A)
End of enumeration elements list.
TABBRANCH_INSTRS : TableBranch instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no table-branch instructions present
1 : en_0b0001
adds TBB, TBH
End of enumeration elements list.
THUMBCOPY_INSTRS : ThumbCopy instructions
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
Thumb MOV(register) instruction does not allow low reg -> low reg
1 : en_0b0001
adds Thumb MOV(register) low reg -> low reg and the CPY alias
End of enumeration elements list.
TRUENOP_INSTRS : TrueNOP instructions
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
true NOP instructions not present - that is, NOP instructions with no register dependencies
1 : en_0b0001
adds "true NOP", and the capability of additional "NOP compatible hints"
End of enumeration elements list.
ISA Feature register4
address_offset : 0xD70 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UNPRIV_INSTRS : Unprivileged instructions
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no "T variant" instructions exist
1 : en_0b0001
adds LDRBT, LDRT, STRBT, STRT
2 : en_0b0010
adds LDRHT, LDRSBT, LDRSHT, STRHT
End of enumeration elements list.
WITHSHIFTS_INSTRS : WithShift instructions. Note that all additions only apply in cases where the encoding supports them - e.g. there is no difference between levels 3 and 4 in the Thumb-2 instruction set. Also note that MOV instructions with shift options should instead be treated as ASR, LSL, LSR, ROR or RRX instructions.
bits : 4 - 7 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
non-zero shifts only support MOV and shift instructions (see notes)
1 : en_0b0001
shifts of loads/stores over the range LSL 0-3
3 : en_0b0010
adds other constant shift options.
4 : en_0b0100
adds register-controlled shift options.
End of enumeration elements list.
WRITEBACK_INSTRS : Writeback instructions
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
only non-writeback addressing modes present, except that LDMIA/STMDB/PUSH/POP instructions support writeback addressing.
1 : en_0b0001
adds all currently-defined writeback addressing modes (ARMv7, Thumb-2)
End of enumeration elements list.
BARRIER_INSTRS : Barrier instructions
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no barrier instructions supported
1 : en_0b0001
adds DMB, DSB, ISB barrier instructions
End of enumeration elements list.
SYNCPRIM_INSTRS_FRAC : SyncPrim_instrs_frac
bits : 20 - 23 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
no additional support
3 : en_0b0011
adds CLREX, LDREXB, STREXB, LDREXH, STREXH
End of enumeration elements list.
PSR_M_INSTRS : PSR_M_instrs
bits : 24 - 27 (4 bit)
access : read-only
Enumeration:
0 : en_0b0000
instructions not present
1 : en_0b0001
adds CPS, MRS, and MSR instructions (M-profile forms)
End of enumeration elements list.
Coprocessor Access Control Register
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP10 : Access privileges for coprocessor 10. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP11, this controls access to the Floating Point Coprocessor.
bits : 20 - 21 (2 bit)
access : read-write
CP11 : Access privileges for coprocessor 11. The possible values of each field are: 0b00 = Access denied. Any attempted access generates a NOCP UsageFault. 0b01 = Privileged access only. An unprivileged access generates a NOCP UsageFault. 0b10 = Reserved. 0b11 = Full access. Used in conjunction with the control for CP10, this controls access to the Floating Point Coprocessor.
bits : 22 - 23 (2 bit)
access : read-write
MPU Type Register
address_offset : 0xD90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SEPARATE : Because the processor core uses only a unified MPU, SEPARATE is always 0.
bits : 0 - 0 (1 bit)
access : read-only
DREGION : Number of supported MPU regions field. DREGION contains 0x08 if the implementation contains an MPU indicating eight MPU regions, otherwise it contains 0x00.
bits : 8 - 15 (8 bit)
access : read-only
IREGION : Because the processor core uses only a unified MPU, IREGION always contains 0x00.
bits : 16 - 23 (8 bit)
access : read-only
MPU Control Register
address_offset : 0xD94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : MPU enable bit. Reset clears the ENABLE bit.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
disable MPU
1 : en_0b1
enable MPU
End of enumeration elements list.
HFNMIENA : This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit = 0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit =1 and ENABLE = 0, behavior is Unpredictable. Reset clears the HFNMIENA bit.
bits : 1 - 1 (1 bit)
access : read-write
PRIVDEFENA : This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it. If this bit = 0, the default memory map is disabled, and memory not covered by a region faults. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data. When the MPU is disabled, the default map acts on both privileged and user mode code. XN and SO rules always apply to the System partition whether this enable is set or not. If the MPU is disabled, this bit is ignored. Reset clears the PRIVDEFENA bit.
bits : 2 - 2 (1 bit)
access : read-write
MPU Region Number Register
address_offset : 0xD98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : Region select field. Selects the region to operate on when using the Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this.
bits : 0 - 7 (8 bit)
access : read-write
MPU Region Base Address Register
address_offset : 0xD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : MPU region override field.
bits : 0 - 3 (4 bit)
access : read-write
VALID : MPU Region Number valid bit.
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
MPU Region Number Register remains unchanged and is interpreted.
1 : en_0b1
MPU Region Number Register is overwritten by bits 3:0 (the REGION value).
End of enumeration elements list.
ADDR : Region base address field. The position of the LSB depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used.
bits : 5 - 31 (27 bit)
access : read-write
MPU Region Attribute and Size Register
address_offset : 0xDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Region enable bit.
bits : 0 - 0 (1 bit)
access : read-write
SIZE : MPU Protection Region Size Field.
bits : 1 - 5 (5 bit)
access : read-write
Enumeration:
4 : en_0b00100
32B
5 : en_0b00101
64B
6 : en_0b00110
128B
7 : en_0b00111
256B
8 : en_0b01000
512B
9 : en_0b01001
1KB
10 : en_0b01010
2KB
11 : en_0b01011
4KB
12 : en_0b01100
8KB
13 : en_0b01101
16KB
14 : en_0b01110
32KB
15 : en_0b01111
64KB
16 : en_0b10000
128KB
17 : en_0b10001
256KB
18 : en_0b10010
512KB
19 : en_0b10011
1MB
20 : en_0b10100
2MB
21 : en_0b10101
4MB
22 : en_0b10110
8MB
23 : en_0b10111
16MB
24 : en_0b11000
32MB
25 : en_0b11001
64MB
26 : en_0b11010
128MB
27 : en_0b11011
256MB
28 : en_0b11100
512MB
29 : en_0b11101
1GB
30 : en_0b11110
2GB
31 : en_0b11111
4GB
End of enumeration elements list.
SRD : Sub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less.
bits : 8 - 15 (8 bit)
access : read-write
B : Bufferable bit
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
not bufferable
1 : en_0b1
bufferable
End of enumeration elements list.
C : Cacheable bit
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
not cacheable
1 : en_0b1
cacheable
End of enumeration elements list.
S : Shareable bit
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
not shareable
1 : en_0b1
shareable
End of enumeration elements list.
TEX : Type extension field
bits : 19 - 21 (3 bit)
access : read-write
AP : Data access permission field
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0 : en_0b000
Priviliged permissions: No access. User permissions: No access.
1 : en_0b001
Priviliged permissions: Read-write. User permissions: No access.
2 : en_0b010
Priviliged permissions: Read-write. User permissions: Read-only.
3 : en_0b011
Priviliged permissions: Read-write. User permissions: Read-write.
5 : en_0b101
Priviliged permissions: Read-only. User permissions: No access.
6 : en_0b110
Priviliged permissions: Read-only. User permissions: Read-only.
7 : en_0b111
Priviliged permissions: Read-only. User permissions: Read-only.
End of enumeration elements list.
XN : Instruction access disable bit
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
enable instruction fetches
1 : en_0b1
disable instruction fetches
End of enumeration elements list.
MPU Alias 1 Region Base Address register
address_offset : 0xDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 1 Region Attribute and Size register
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 2 Region Base Address register
address_offset : 0xDAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 2 Region Attribute and Size register
address_offset : 0xDB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 3 Region Base Address register
address_offset : 0xDB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPU Alias 3 Region Attribute and Size register
address_offset : 0xDB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Debug Halting Control and Status Register
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C_DEBUGEN : Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it. The core must write a 1 to it when writing C_HALT to halt itself.
bits : 0 - 0 (1 bit)
access : read-write
C_HALT : Halts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. This bit can only be written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0] is 2'b11). The core can halt itself, but only if C_DEBUGEN is already 1 and only if it writes with b11).
bits : 1 - 1 (1 bit)
access : read-write
C_STEP : Steps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1).
bits : 2 - 2 (1 bit)
access : read-write
C_MASKINTS : Mask interrupts when stepping or running in halted debug. Does not affect NMI, which is not maskable. Must only be modified when the processor is halted (S_HALT == 1). Also does not affect fault exceptions and SVC caused by execution of the instructions. CMASKINTS must be set or cleared before halt is released. This means that the writes to set or clear C_MASKINTS and to set or clear C_HALT must be separate.
bits : 3 - 3 (1 bit)
access : read-write
C_SNAPSTALL : If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if: C_DEBUGEN = 1 and C_HALT = 1. The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse. The bus state is Unpredictable when this is used. S_RETIRE can detect core stalls on load/store operations.
bits : 5 - 5 (1 bit)
access : read-write
S_REGRDY : Register Read/Write on the Debug Core Register Selector register is available. Last transfer is complete.
bits : 16 - 16 (1 bit)
access : read-only
S_HALT : The core is in debug state when S_HALT is set.
bits : 17 - 17 (1 bit)
access : read-only
S_SLEEP : Indicates that the core is sleeping (WFI, WFE, or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up.
bits : 18 - 18 (1 bit)
access : read-only
S_LOCKUP : Reads as one if the core is running (not halted) and a lockup condition is present.
bits : 19 - 19 (1 bit)
access : read-only
S_RETIRE_ST : Indicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch.
bits : 24 - 24 (1 bit)
access : read-only
S_RESET_ST : Indicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still).
bits : 25 - 25 (1 bit)
access : read-only
Deubg Core Register Selector Register
address_offset : 0xDF4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
REGSEL : Register select
bits : 0 - 4 (5 bit)
access : write-only
Enumeration:
0 : en_0b00000
R0
1 : en_0b00001
R1
2 : en_0b00010
R2
3 : en_0b00011
R3
4 : en_0b00100
R4
5 : en_0b00101
R5
6 : en_0b00110
R6
7 : en_0b00111
R7
8 : en_0b01000
R8
9 : en_0b01001
R9
10 : en_0b01010
R10
11 : en_0b01011
R11
12 : en_0b01100
R12
13 : en_0b01101
Current SP
14 : en_0b01110
LR
15 : en_0b01111
DebugReturnAddress
16 : en_0b10000
xPSR/flags, execution state information, and exception number
17 : en_0b10001
MSP (Main SP)
18 : en_0b10010
PSP (Process SP)
20 : en_0b10100
CONTROL bits [31:24], FAULTMASK bits [23:16], BASEPRI bits [15:8], PRIMASK bits [7:0]
End of enumeration elements list.
REGWNR : Write = 1, Read = 0
bits : 16 - 16 (1 bit)
access : write-only
Debug Core Register Data Register
address_offset : 0xDF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Debug Exception and Monitor Control Register
address_offset : 0xDFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VC_CORERESET : Reset Vector Catch. Halt running system if Core reset occurs.
bits : 0 - 0 (1 bit)
access : read-write
VC_MMERR : Debug trap on Memory Management faults.
bits : 4 - 4 (1 bit)
access : read-write
VC_NOCPERR : Debug trap on Usage Fault access to Coprocessor that is not present or marked as not present in CAR register.
bits : 5 - 5 (1 bit)
access : read-write
VC_CHKERR : Debug trap on Usage Fault enabled checking errors.
bits : 6 - 6 (1 bit)
access : read-write
VC_STATERR : Debug trap on Usage Fault state errors.
bits : 7 - 7 (1 bit)
access : read-write
VC_BUSERR : Debug Trap on normal Bus error.
bits : 8 - 8 (1 bit)
access : read-write
VC_INTERR : Debug Trap on interrupt/exception service errors. These are a subset of other faults and catches before BUSERR or HARDERR.
bits : 9 - 9 (1 bit)
access : read-write
VC_HARDERR : Debug trap on Hard Fault.
bits : 10 - 10 (1 bit)
access : read-write
MON_EN : Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. C_DEBUGEN in the Debug Halting Control and Statue register overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.
bits : 16 - 16 (1 bit)
access : read-write
MON_PEND : Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a POR reset. Software in the reset handler or later, or by the DAP must enable the debug monitor.
bits : 17 - 17 (1 bit)
access : read-write
MON_STEP : When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI.
bits : 18 - 18 (1 bit)
access : read-write
MON_REQ : This enables the monitor to identify how it wakes up. This bit clears on a Core Reset.
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : en_0b0
woken up by debug exception.
1 : en_0b1
woken up by MON_PEND
End of enumeration elements list.
TRCENA : This bit must be set to 1 to enable use of the trace and debug blocks: Data Watchpoint and Trace (DWT), Instrumentation Trace Macrocell (ITM), Embedded Trace Macrocell (ETM), Trace Port Interface Unit (TPIU). This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger. Note that if no debug or trace components are present in the implementation then it is not possible to set TRCENA.
bits : 24 - 24 (1 bit)
access : read-write
Software Trigger Interrupt Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
INTID : Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.
bits : 0 - 8 (9 bit)
access : write-only
Floating Point Context Control Register
address_offset : 0xF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSPACT : Indicates whether Lazy preservation of the FP state is active.
bits : 0 - 0 (1 bit)
access : read-write
USER : Indicates the privilege level of the software executing was User (Unpriviledged) when the processor allocated the FP stack frame.
bits : 1 - 1 (1 bit)
access : read-write
THREAD : Indicates the processor mode was Thread when it allocated the FP stack frame.
bits : 3 - 3 (1 bit)
access : read-write
HFRDY : Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending.
bits : 4 - 4 (1 bit)
access : read-write
MMRDY : Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending.
bits : 5 - 5 (1 bit)
access : read-write
BFRDY : Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending.
bits : 6 - 6 (1 bit)
access : read-write
MONRDY : Indicates whether the the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending.
bits : 8 - 8 (1 bit)
access : read-write
LSPEN : Lazy State Preservation ENable. When the processor performs a context save, space on the stack is reserved for the floating point state but it is not stacked until the new context performs a floating point operation.
bits : 30 - 30 (1 bit)
access : read-write
ASPEN : Automatic State Preservation ENable. When this bit is set is will cause bit [2] of the Special CONTROL register to be set (FPCA) on execution of a floating point instruction which results in the floating point state automatically being preserved on exception entry.
bits : 31 - 31 (1 bit)
access : read-write
Floating-Point Context Address Register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Holds the (double-word-aligned) location of the unpopulated floating-point register space allocated on an exception stack frame.
bits : 2 - 30 (29 bit)
access : read-write
Floating Point Default Status Control Register
address_offset : 0xF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMODE : Default value for Rounding Mode control field. (The encoding for this field is: 0b00 Round to Nearest (RN) mode, 0b01 Round towards Plus Infinity (RP) mode, 0b10 Round towards Minus Infinity (RM) mode, 0b11 Round towards Zero (RZ) mode. The specified rounding mode is used by almost all floating-point instructions).
bits : 22 - 23 (2 bit)
access : read-write
FZ : Default value for Flush-to-Zero mode bit. (If this bit is set to 1 then Flush-to-zero mode is enabled).
bits : 24 - 24 (1 bit)
access : read-write
DN : Default value for Default NaN mode bit. (If this bit is set to 1 then any operation involving one or more NaNs returns the Default NaN).
bits : 25 - 25 (1 bit)
access : read-write
AHP : Default value for Alternative Half Precision bit. (If this bit is set to 1 then Alternative half-precision format is selected).
bits : 26 - 26 (1 bit)
access : read-write
Media and FP Feature Register 0 (MVFR0)
address_offset : 0xF40 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
A_SIMD_REGISTERS : Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers.
bits : 0 - 3 (4 bit)
access : read-only
SINGLE_PRECISION : Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported.
bits : 4 - 7 (4 bit)
access : read-only
DOUBLE_PRECISION : Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported in ARMv7-M.
bits : 8 - 11 (4 bit)
access : read-only
FP_EXCEPTION_TRAPPING : Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported in ARMv7-M.
bits : 12 - 15 (4 bit)
access : read-only
DIVIDE : Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported.
bits : 16 - 19 (4 bit)
access : read-only
SQUARE_ROOT : Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported.
bits : 20 - 23 (4 bit)
access : read-only
SHORT_VECTORS : Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported in ARMv7-M.
bits : 24 - 27 (4 bit)
access : read-only
FP_ROUNDING_MODES : Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported.
bits : 28 - 31 (4 bit)
access : read-only
Media and FP Feature Register 1 (MVFR1)
address_offset : 0xF44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FTZ_MODE : Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation. The value of this field is: 0b0001 - hardware supports full denormalized number arithmetic.
bits : 0 - 3 (4 bit)
access : read-only
D_NAN_MODE : Indicates whether the FP hardware implementation supports only the Default NaN mode. The value of this field is: 0b0001 - hardware supports propagation of NaN values.
bits : 4 - 7 (4 bit)
access : read-only
FP_HPFP : Indicates whether the FP supports half-precision floating-point conversion operations. The value of this field is: 0b0001 - supported.
bits : 24 - 27 (4 bit)
access : read-only
FP_FUSED_MAC : Indicates whether the FP supports fused multiply accumulate operations. The value of this field is: 0b0001 - supported.
bits : 28 - 31 (4 bit)
access : read-only
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