Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected
eUSCI_Bx Control Word Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCSWRST : Software reset enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UCSWRST_0
Disabled. eUSCI_B reset released for operation
1 : UCSWRST_1
Enabled. eUSCI_B logic held in reset state
End of enumeration elements list.
UCTXSTT : Transmit START condition in master mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : UCTXSTT_0
Do not generate START condition
1 : UCTXSTT_1
Generate START condition
End of enumeration elements list.
UCTXSTP : Transmit STOP condition in master mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : UCTXSTP_0
No STOP generated
1 : UCTXSTP_1
Generate STOP
End of enumeration elements list.
UCTXNACK : Transmit a NACK
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : UCTXNACK_0
Acknowledge normally
1 : UCTXNACK_1
Generate NACK
End of enumeration elements list.
UCTR : Transmitter/receiver
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : UCTR_0
Receiver
1 : UCTR_1
Transmitter
End of enumeration elements list.
UCTXACK : Transmit ACK condition in slave mode
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : UCTXACK_0
Do not acknowledge the slave address
1 : UCTXACK_1
Acknowledge the slave address
End of enumeration elements list.
UCSSEL : eUSCI_B clock source select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : UCSSEL_0
UCLKI
1 : UCSSEL_1
ACLK
2 : UCSSEL_2
SMCLK
3 : UCSSEL_3
SMCLK
End of enumeration elements list.
UCSYNC : Synchronous mode enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : UCSYNC_0
Asynchronous mode
1 : UCSYNC_1
Synchronous mode
End of enumeration elements list.
UCMODE : eUSCI_B mode
bits : 9 - 10 (2 bit)
access : read-write
Enumeration:
0 : UCMODE_0
3-pin SPI
1 : UCMODE_1
4-pin SPI (master or slave enabled if STE = 1)
2 : UCMODE_2
4-pin SPI (master or slave enabled if STE = 0)
3 : UCMODE_3
I2C mode
End of enumeration elements list.
UCMST : Master mode select
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : UCMST_0
Slave mode
1 : UCMST_1
Master mode
End of enumeration elements list.
UCMM : Multi-master environment select
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : UCMM_0
Single master environment. There is no other master in the system. The address compare unit is disabled.
1 : UCMM_1
Multi-master environment
End of enumeration elements list.
UCSLA10 : Slave addressing mode select
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : UCSLA10_0
Address slave with 7-bit address
1 : UCSLA10_1
Address slave with 10-bit address
End of enumeration elements list.
UCA10 : Own addressing mode select
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : UCA10_0
Own address is a 7-bit address
1 : UCA10_1
Own address is a 10-bit address
End of enumeration elements list.
eUSCI_Bx I2C Own Address 0 Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2COA0 : I2C own address
bits : 0 - 9 (10 bit)
access : read-write
UCOAEN : Own Address enable register
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : UCOAEN_0
The slave address defined in I2COA0 is disabled
1 : UCOAEN_1
The slave address defined in I2COA0 is enabled
End of enumeration elements list.
UCGCEN : General call response enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : UCGCEN_0
Do not respond to a general call
1 : UCGCEN_1
Respond to a general call
End of enumeration elements list.
eUSCI_Bx I2C Own Address 1 Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2COA1 : I2C own address
bits : 0 - 9 (10 bit)
access : read-write
UCOAEN : Own Address enable register
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : UCOAEN_0
The slave address defined in I2COA1 is disabled
1 : UCOAEN_1
The slave address defined in I2COA1 is enabled
End of enumeration elements list.
eUSCI_Bx I2C Own Address 2 Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2COA2 : I2C own address
bits : 0 - 9 (10 bit)
access : read-write
UCOAEN : Own Address enable register
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : UCOAEN_0
The slave address defined in I2COA2 is disabled
1 : UCOAEN_1
The slave address defined in I2COA2 is enabled
End of enumeration elements list.
eUSCI_Bx I2C Own Address 3 Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2COA3 : I2C own address
bits : 0 - 9 (10 bit)
access : read-write
UCOAEN : Own Address enable register
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : UCOAEN_0
The slave address defined in I2COA3 is disabled
1 : UCOAEN_1
The slave address defined in I2COA3 is enabled
End of enumeration elements list.
eUSCI_Bx I2C Received Address Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDRX : Received Address Register
bits : 0 - 9 (10 bit)
access : read-only
eUSCI_Bx I2C Address Mask Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDMASK : Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1.
bits : 0 - 9 (10 bit)
access : read-write
eUSCI_Bx Control Word Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCGLIT : Deglitch time
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : UCGLIT_0
50 ns
1 : UCGLIT_1
25 ns
2 : UCGLIT_2
12.5 ns
3 : UCGLIT_3
6.25 ns
End of enumeration elements list.
UCASTP : Automatic STOP condition generation
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : UCASTP_0
No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care.
1 : UCASTP_1
UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT
2 : UCASTP_2
A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold
End of enumeration elements list.
UCSWACK : SW or HW ACK control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : UCSWACK_0
The address acknowledge of the slave is controlled by the eUSCI_B module
1 : UCSWACK_1
The user needs to trigger the sending of the address ACK by issuing UCTXACK
End of enumeration elements list.
UCSTPNACK : ACK all master bytes
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : UCSTPNACK_0
Send a non-acknowledge before the STOP condition as a master receiver (conform to I2C standard)
1 : UCSTPNACK_1
All bytes are acknowledged by the eUSCI_B when configured as master receiver
End of enumeration elements list.
UCCLTO : Clock low timeout select
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : UCCLTO_0
Disable clock low timeout counter
1 : UCCLTO_1
135 000 SYSCLK cycles (approximately 28 ms)
2 : UCCLTO_2
150 000 SYSCLK cycles (approximately 31 ms)
3 : UCCLTO_3
165 000 SYSCLK cycles (approximately 34 ms)
End of enumeration elements list.
UCETXINT : Early UCTXIFG0
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : UCETXINT_0
UCTXIFGx is set after an address match with UCxI2COAx and the direction bit indicating slave transmit
1 : UCETXINT_1
UCTXIFG0 is set for each START condition
End of enumeration elements list.
eUSCI_Bx I2C Slave Address Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
I2CSA : I2C slave address
bits : 0 - 9 (10 bit)
access : read-write
eUSCI_Bx Interrupt Enable Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCRXIE0 : Receive interrupt enable 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UCRXIE0_0
Interrupt disabled
1 : UCRXIE0_1
Interrupt enabled
End of enumeration elements list.
UCTXIE0 : Transmit interrupt enable 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : UCTXIE0_0
Interrupt disabled
1 : UCTXIE0_1
Interrupt enabled
End of enumeration elements list.
UCSTTIE : START condition interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : UCSTTIE_0
Interrupt disabled
1 : UCSTTIE_1
Interrupt enabled
End of enumeration elements list.
UCSTPIE : STOP condition interrupt enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : UCSTPIE_0
Interrupt disabled
1 : UCSTPIE_1
Interrupt enabled
End of enumeration elements list.
UCALIE : Arbitration lost interrupt enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : UCALIE_0
Interrupt disabled
1 : UCALIE_1
Interrupt enabled
End of enumeration elements list.
UCNACKIE : Not-acknowledge interrupt enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : UCNACKIE_0
Interrupt disabled
1 : UCNACKIE_1
Interrupt enabled
End of enumeration elements list.
UCBCNTIE : Byte counter interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : UCBCNTIE_0
Interrupt disabled
1 : UCBCNTIE_1
Interrupt enabled
End of enumeration elements list.
UCCLTOIE : Clock low timeout interrupt enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : UCCLTOIE_0
Interrupt disabled
1 : UCCLTOIE_1
Interrupt enabled
End of enumeration elements list.
UCRXIE1 : Receive interrupt enable 1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : UCRXIE1_0
Interrupt disabled
1 : UCRXIE1_1
Interrupt enabled
End of enumeration elements list.
UCTXIE1 : Transmit interrupt enable 1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : UCTXIE1_0
Interrupt disabled
1 : UCTXIE1_1
Interrupt enabled
End of enumeration elements list.
UCRXIE2 : Receive interrupt enable 2
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : UCRXIE2_0
Interrupt disabled
1 : UCRXIE2_1
Interrupt enabled
End of enumeration elements list.
UCTXIE2 : Transmit interrupt enable 2
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : UCTXIE2_0
Interrupt disabled
1 : UCTXIE2_1
Interrupt enabled
End of enumeration elements list.
UCRXIE3 : Receive interrupt enable 3
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : UCRXIE3_0
Interrupt disabled
1 : UCRXIE3_1
Interrupt enabled
End of enumeration elements list.
UCTXIE3 : Transmit interrupt enable 3
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : UCTXIE3_0
Interrupt disabled
1 : UCTXIE3_1
Interrupt enabled
End of enumeration elements list.
UCBIT9IE : Bit position 9 interrupt enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : UCBIT9IE_0
Interrupt disabled
1 : UCBIT9IE_1
Interrupt enabled
End of enumeration elements list.
eUSCI_Bx Interrupt Flag Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCRXIFG0 : eUSCI_B receive interrupt flag 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : UCRXIFG0_0
No interrupt pending
1 : UCRXIFG0_1
Interrupt pending
End of enumeration elements list.
UCTXIFG0 : eUSCI_B transmit interrupt flag 0
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : UCTXIFG0_0
No interrupt pending
1 : UCTXIFG0_1
Interrupt pending
End of enumeration elements list.
UCSTTIFG : START condition interrupt flag
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : UCSTTIFG_0
No interrupt pending
1 : UCSTTIFG_1
Interrupt pending
End of enumeration elements list.
UCSTPIFG : STOP condition interrupt flag
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : UCSTPIFG_0
No interrupt pending
1 : UCSTPIFG_1
Interrupt pending
End of enumeration elements list.
UCALIFG : Arbitration lost interrupt flag
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : UCALIFG_0
No interrupt pending
1 : UCALIFG_1
Interrupt pending
End of enumeration elements list.
UCNACKIFG : Not-acknowledge received interrupt flag
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : UCNACKIFG_0
No interrupt pending
1 : UCNACKIFG_1
Interrupt pending
End of enumeration elements list.
UCBCNTIFG : Byte counter interrupt flag
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : UCBCNTIFG_0
No interrupt pending
1 : UCBCNTIFG_1
Interrupt pending
End of enumeration elements list.
UCCLTOIFG : Clock low timeout interrupt flag
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : UCCLTOIFG_0
No interrupt pending
1 : UCCLTOIFG_1
Interrupt pending
End of enumeration elements list.
UCRXIFG1 : eUSCI_B receive interrupt flag 1
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : UCRXIFG1_0
No interrupt pending
1 : UCRXIFG1_1
Interrupt pending
End of enumeration elements list.
UCTXIFG1 : eUSCI_B transmit interrupt flag 1
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : UCTXIFG1_0
No interrupt pending
1 : UCTXIFG1_1
Interrupt pending
End of enumeration elements list.
UCRXIFG2 : eUSCI_B receive interrupt flag 2
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : UCRXIFG2_0
No interrupt pending
1 : UCRXIFG2_1
Interrupt pending
End of enumeration elements list.
UCTXIFG2 : eUSCI_B transmit interrupt flag 2
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : UCTXIFG2_0
No interrupt pending
1 : UCTXIFG2_1
Interrupt pending
End of enumeration elements list.
UCRXIFG3 : eUSCI_B receive interrupt flag 3
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : UCRXIFG3_0
No interrupt pending
1 : UCRXIFG3_1
Interrupt pending
End of enumeration elements list.
UCTXIFG3 : eUSCI_B transmit interrupt flag 3
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : UCTXIFG3_0
No interrupt pending
1 : UCTXIFG3_1
Interrupt pending
End of enumeration elements list.
UCBIT9IFG : Bit position 9 interrupt flag
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : UCBIT9IFG_0
No interrupt pending
1 : UCBIT9IFG_1
Interrupt pending
End of enumeration elements list.
eUSCI_Bx Interrupt Vector Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UCIV : eUSCI_B interrupt vector value
bits : 0 - 15 (16 bit)
access : read-only
Enumeration: UCIV_enum_read ( read )
0 : UCIV_0
No interrupt pending
2 : UCIV_2
Interrupt Source: Arbitration lost Interrupt Flag: UCALIFG Interrupt Priority: Highest
4 : UCIV_4
Interrupt Source: Not acknowledgment Interrupt Flag: UCNACKIFG
6 : UCIV_6
Interrupt Source: Start condition received Interrupt Flag: UCSTTIFG
8 : UCIV_8
Interrupt Source: Stop condition received Interrupt Flag: UCSTPIFG
10 : UCIV_10
Interrupt Source: Slave 3 Data received Interrupt Flag: UCRXIFG3
12 : UCIV_12
Interrupt Source: Slave 3 Transmit buffer empty Interrupt Flag: UCTXIFG3
14 : UCIV_14
Interrupt Source: Slave 2 Data received Interrupt Flag: UCRXIFG2
16 : UCIV_16
Interrupt Source: Slave 2 Transmit buffer empty Interrupt Flag: UCTXIFG2
18 : UCIV_18
Interrupt Source: Slave 1 Data received Interrupt Flag: UCRXIFG1
20 : UCIV_20
Interrupt Source: Slave 1 Transmit buffer empty Interrupt Flag: UCTXIFG1
22 : UCIV_22
Interrupt Source: Data received Interrupt Flag: UCRXIFG0
24 : UCIV_24
Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG0
26 : UCIV_26
Interrupt Source: Byte counter zero Interrupt Flag: UCBCNTIFG
28 : UCIV_28
Interrupt Source: Clock low timeout Interrupt Flag: UCCLTOIFG
30 : UCIV_30
Interrupt Source: Nineth bit position Interrupt Flag: UCBIT9IFG Priority: Lowest
End of enumeration elements list.
eUSCI_Bx Baud Rate Control Word Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCBR : Bit clock prescaler
bits : 0 - 15 (16 bit)
access : read-write
eUSCI_Bx Status Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCBBUSY : Bus busy
bits : 4 - 4 (1 bit)
access : read-only
Enumeration: UCBBUSY_enum_read ( read )
0 : UCBBUSY_0
Bus inactive
1 : UCBBUSY_1
Bus busy
End of enumeration elements list.
UCGC : General call address received
bits : 5 - 5 (1 bit)
access : read-only
Enumeration: UCGC_enum_read ( read )
0 : UCGC_0
No general call address received
1 : UCGC_1
General call address received
End of enumeration elements list.
UCSCLLOW : SCL low
bits : 6 - 6 (1 bit)
access : read-only
Enumeration: UCSCLLOW_enum_read ( read )
0 : UCSCLLOW_0
SCL is not held low
1 : UCSCLLOW_1
SCL is held low
End of enumeration elements list.
UCBCNT : Hardware byte counter value
bits : 8 - 15 (8 bit)
access : read-only
eUSCI_Bx Byte Counter Threshold Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCTBCNT : Byte counter threshold value
bits : 0 - 7 (8 bit)
access : read-write
eUSCI_Bx Receive Buffer Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
UCRXBUF : Receive data buffer
bits : 0 - 7 (8 bit)
access : read-only
eUSCI_Bx Transmit Buffer Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UCTXBUF : Transmit data buffer
bits : 0 - 7 (8 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.