\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Control 0 Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMR : Active Mode Request
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0 : AMR_0
LDO based Active Mode at Core voltage setting 0.
1 : AMR_1
LDO based Active Mode at Core voltage setting 1.
4 : AMR_4
DC-DC based Active Mode at Core voltage setting 0.
5 : AMR_5
DC-DC based Active Mode at Core voltage setting 1.
8 : AMR_8
Low-Frequency Active Mode at Core voltage setting 0.
9 : AMR_9
Low-Frequency Active Mode at Core voltage setting 1.
End of enumeration elements list.
LPMR : Low Power Mode Request
bits : 4 - 7 (4 bit)
access : read-write
Enumeration:
0 : LPMR_0
LPM3. Core voltage setting is similar to the mode from which LPM3 is entered.
10 : LPMR_10
LPM3.5. Core voltage setting 0.
12 : LPMR_12
LPM4.5
End of enumeration elements list.
CPM : Current Power Mode
bits : 8 - 13 (6 bit)
access : read-only
Enumeration: CPM_enum_read ( read )
0 : CPM_0
LDO based Active Mode at Core voltage setting 0.
1 : CPM_1
LDO based Active Mode at Core voltage setting 1.
4 : CPM_4
DC-DC based Active Mode at Core voltage setting 0.
5 : CPM_5
DC-DC based Active Mode at Core voltage setting 1.
8 : CPM_8
Low-Frequency Active Mode at Core voltage setting 0.
9 : CPM_9
Low-Frequency Active Mode at Core voltage setting 1.
16 : CPM_16
LDO based LPM0 at Core voltage setting 0.
17 : CPM_17
LDO based LPM0 at Core voltage setting 1.
20 : CPM_20
DC-DC based LPM0 at Core voltage setting 0.
21 : CPM_21
DC-DC based LPM0 at Core voltage setting 1.
24 : CPM_24
Low-Frequency LPM0 at Core voltage setting 0.
25 : CPM_25
Low-Frequency LPM0 at Core voltage setting 1.
32 : CPM_32
LPM3
End of enumeration elements list.
PCMKEY : PCM key
bits : 16 - 31 (16 bit)
access : read-write
Clear Interrupt Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR_LPM_INVALID_TR_IFG : Clear LPM invalid transition flag
bits : 0 - 0 (1 bit)
access : write-only
CLR_LPM_INVALID_CLK_IFG : Clear LPM invalid clock flag
bits : 1 - 1 (1 bit)
access : write-only
CLR_AM_INVALID_TR_IFG : Clear active mode invalid transition flag
bits : 2 - 2 (1 bit)
access : write-only
CLR_DCDC_ERROR_IFG : Clear DC-DC error flag
bits : 6 - 6 (1 bit)
access : write-only
Control 1 Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKLPM5 : Lock LPM5
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LOCKLPM5_0
LPMx.5 configuration defaults to reset condition
1 : LOCKLPM5_1
LPMx.5 configuration remains locked during LPMx.5 entry and exit
End of enumeration elements list.
LOCKBKUP : Lock Backup
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LOCKBKUP_0
Backup domain configuration defaults to reset condition
1 : LOCKBKUP_1
Backup domain configuration remains locked during LPM3.5 entry and exit
End of enumeration elements list.
FORCE_LPM_ENTRY : Force LPM entry
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : FORCE_LPM_ENTRY_0
PCM aborts LPM3/LPMx.5 transition if the active clock configuration does not meet the LPM3/LPMx.5 entry criteria. PCM generates the LPM_INVALID_CLK flag on abort to LPM3/LPMx.5 entry.
1 : FORCE_LPM_ENTRY_1
PCM enters LPM3/LPMx.5 after shuting off the clocks forcefully. Application needs to ensure RTC and WDT are clocked using BCLK tree to keep these modules alive in LPM3/LPM3.5. In LPM4.5 all clocks are forcefully shutoff and the core voltage is turned off.
End of enumeration elements list.
PMR_BUSY : Power mode request busy flag
bits : 8 - 8 (1 bit)
access : read-write
PCMKEY : PCM key
bits : 16 - 31 (16 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPM_INVALID_TR_IE : LPM invalid transition interrupt enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LPM_INVALID_TR_IE_0
Disabled
1 : LPM_INVALID_TR_IE_1
Enabled
End of enumeration elements list.
LPM_INVALID_CLK_IE : LPM invalid clock interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LPM_INVALID_CLK_IE_0
Disabled
1 : LPM_INVALID_CLK_IE_1
Enabled
End of enumeration elements list.
AM_INVALID_TR_IE : Active mode invalid transition interrupt enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AM_INVALID_TR_IE_0
Disabled
1 : AM_INVALID_TR_IE_1
Enabled
End of enumeration elements list.
DCDC_ERROR_IE : DC-DC error interrupt enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DCDC_ERROR_IE_0
Disabled
1 : DCDC_ERROR_IE_1
Enabled
End of enumeration elements list.
Interrupt Flag Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
LPM_INVALID_TR_IFG : LPM invalid transition flag
bits : 0 - 0 (1 bit)
access : read-only
LPM_INVALID_CLK_IFG : LPM invalid clock flag
bits : 1 - 1 (1 bit)
access : read-only
AM_INVALID_TR_IFG : Active mode invalid transition flag
bits : 2 - 2 (1 bit)
access : read-only
DCDC_ERROR_IFG : DC-DC error flag
bits : 6 - 6 (1 bit)
access : read-only
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