CTRL

SLEEPCNT

LSUCNT

FOLDCNT

PCSR

COMP0

MASK0

FUNCTION0

COMP1

MASK1

FUNCTION1

CYCCNT

COMP2

MASK2

FUNCTION2

COMP3

MASK3

FUNCTION3

CPICNT

EXCCNT

CYCCNTENA : Enable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0.
bits : 0 - 0 (1 bit)
access : read-write

POSTPRESET : Reload value for POSTCNT, bits [8:5], post-scalar counter. If this value is 0, events are triggered on each tap change (a power of 2). If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change.
bits : 1 - 4 (4 bit)
access : read-write

POSTCNT : Post-scalar counter for CYCTAP. When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0. If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]).
bits : 5 - 8 (4 bit)
access : read-write

CYCTAP : Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]. When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SYNCTAP : Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1.
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

PCSAMPLEENA : Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]). Reset clears the PCSAMPLENA bit.
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXCTRCENA : Enables Interrupt event tracing. Reset clears the EXCEVTENA bit.
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CPIEVTENA : Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions). Reset clears the CPIEVTENA bit.
bits : 17 - 17 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EXCEVTENA : Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead). Reset clears the EXCEVTENA bit.
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

SLEEPEVTENA : Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping). Reset clears the SLEEPEVTENA bit.
bits : 19 - 19 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

LSUEVTENA : Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction. Reset clears the LSUEVTENA bit.
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

FOLDEVTENA : Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle. Reset clears the FOLDEVTENA bit.
bits : 21 - 21 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

CYCEVTENA : Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details. This event is only emitted if PCSAMPLENA, bit [12], is disabled. PCSAMPLENA overrides the setting of this bit. Reset clears the CYCEVTENA bit.
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

End of enumeration elements list.

NOPRFCNT : When set, DWT_FOLDCNT, DWT_LSUCNT, DWT_SLEEPCNT, DWT_EXCCNT, and DWT_CPICNT are not supported.
bits : 24 - 24 (1 bit)
access : read-write

NOCYCCNT : When set, DWT_CYCCNT is not supported.
bits : 25 - 25 (1 bit)
access : read-write

SLEEPCNT : Sleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Note that SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep.
bits : 0 - 7 (8 bit)
access : read-write

LSUCNT : LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted. For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles). Clears to 0 on enabling.
bits : 0 - 7 (8 bit)
access : read-write

FOLDCNT : This counts the total number folded instructions. This counter initializes to 0 when enabled.
bits : 0 - 7 (8 bit)
access : read-write

EIASAMPLE : Execution instruction address sample, or 0xFFFFFFFF if the core is halted.
bits : 0 - 31 (32 bit)
access : read-only

COMP : Data value to compare against PC and the data address as given by DWT_FUNCTION0. DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT).
bits : 0 - 31 (32 bit)
access : read-write

MASK : Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.
bits : 0 - 3 (4 bit)
access : read-write

FUNCTION : Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMITRANGE : Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.
bits : 5 - 5 (1 bit)
access : read-write

DATAVMATCH : This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.
bits : 8 - 8 (1 bit)
access : read-write

LNK1ENA :
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATAVSIZE : Defines the size of the data in the COMP register that is to be matched:
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATAVADDR0 : Identity of a linked address comparator for data value matching when DATAVMATCH == 1.
bits : 12 - 15 (4 bit)
access : read-write

DATAVADDR1 : Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.
bits : 16 - 19 (4 bit)
access : read-write

MATCHED : This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.
bits : 24 - 24 (1 bit)
access : read-write

COMP : Data value to compare against PC and the data address as given by DWT_FUNCTION1.
bits : 0 - 31 (32 bit)
access : read-write

MASK : Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.
bits : 0 - 3 (4 bit)
access : read-write

FUNCTION : Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 in DWT_FUNCTION1if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches. Note 4: If the data matching functionality is not included during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If it is not settable then data matching is unavailable. Note 5: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMITRANGE : Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.
bits : 5 - 5 (1 bit)
access : read-write

CYCMATCH : Only available in comparator 0. When set, this comparator compares against the clock cycle counter.
bits : 7 - 7 (1 bit)
access : read-write

DATAVMATCH : This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.
bits : 8 - 8 (1 bit)
access : read-write

LNK1ENA :
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATAVSIZE : Defines the size of the data in the COMP register that is to be matched:
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATAVADDR0 : Identity of a linked address comparator for data value matching when DATAVMATCH == 1.
bits : 12 - 15 (4 bit)
access : read-write

DATAVADDR1 : Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.
bits : 16 - 19 (4 bit)
access : read-write

MATCHED : This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.
bits : 24 - 24 (1 bit)
access : read-write

CYCCNT : Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted. CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow. The debugger must initialize this to 0 when first enabling.
bits : 0 - 31 (32 bit)
access : read-write

COMP : Data value to compare against PC and the data address as given by DWT_FUNCTION2.
bits : 0 - 31 (32 bit)
access : read-write

MASK : Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.
bits : 0 - 3 (4 bit)
access : read-write

FUNCTION : Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMITRANGE : Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.
bits : 5 - 5 (1 bit)
access : read-write

DATAVMATCH : This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.
bits : 8 - 8 (1 bit)
access : read-write

LNK1ENA :
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATAVSIZE : Defines the size of the data in the COMP register that is to be matched:
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATAVADDR0 : Identity of a linked address comparator for data value matching when DATAVMATCH == 1.
bits : 12 - 15 (4 bit)
access : read-write

DATAVADDR1 : Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.
bits : 16 - 19 (4 bit)
access : read-write

MATCHED : This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.
bits : 24 - 24 (1 bit)
access : read-write

COMP : Data value to compare against PC and the data address as given by DWT_FUNCTION3.
bits : 0 - 31 (32 bit)
access : read-write

MASK : Mask on data address when matching against COMP. This is the size of the ignore mask. hat is, DWT matching is performed as:(ADDR ANDed with (~0 left bit-shifted by MASK)) == COMP. However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.
bits : 0 - 3 (4 bit)
access : read-write

FUNCTION : Function settings. Note 1: If the ETM is not fitted, then ETM trigger is not possible. Note 2: Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst. Note 3: PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

End of enumeration elements list.

EMITRANGE : Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled. EMITRANGE only applies for: FUNCTION = b0001, b0010, b0011, b1100, b1101, b1110, and b1111.
bits : 5 - 5 (1 bit)
access : read-write

DATAVMATCH : This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares. The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.
bits : 8 - 8 (1 bit)
access : read-write

LNK1ENA :
bits : 9 - 9 (1 bit)
access : read-only

Enumeration:

End of enumeration elements list.

DATAVSIZE : Defines the size of the data in the COMP register that is to be matched:
bits : 10 - 11 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

DATAVADDR0 : Identity of a linked address comparator for data value matching when DATAVMATCH == 1.
bits : 12 - 15 (4 bit)
access : read-write

DATAVADDR1 : Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.
bits : 16 - 19 (4 bit)
access : read-write

MATCHED : This bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.
bits : 24 - 24 (1 bit)
access : read-write

CPICNT : Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by DWT_LSUCNT. This counter also increments on all instruction fetch stalls. If CPIEVTENA is set, an event is emitted when the counter overflows. Clears to 0 on enabling.
bits : 0 - 7 (8 bit)
access : read-write

EXCCNT : Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled. Clears to 0 on enabling.
bits : 0 - 7 (8 bit)
access : read-write