\n

DMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1050 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DEVICE_CFG

CH_SRCCFG0

CH_SRCCFG[%s] (CH_SRCCFG[7])

INT1_SRCCFG

STAT

CFG

CTLBASE

ALTBASE

WAITSTAT

SWREQ

USEBURSTSET

USEBURSTCLR

REQMASKSET

REQMASKCLR

ENASET

ENACLR

ALTSET

ALTCLR

PRIOSET

PRIOCLR

INT2_SRCCFG

ERRCLR

INT3_SRCCFG

INT0_SRCFLG

INT0_CLRFLG

CH_SRCCFG[%s] (CH_SRCCFG[8])

CH_SRCCFG1

CH_SRCCFG[%s] (CH_SRCCFG[9])

CH_SRCCFG2

CH_SRCCFG[%s] (CH_SRCCFG[10])

CH_SRCCFG3

CH_SRCCFG[%s] (CH_SRCCFG[11])

CH_SRCCFG[%s] (CH_SRCCFG[0])

CH_SRCCFG4

CH_SRCCFG[%s] (CH_SRCCFG[12])

CH_SRCCFG5

CH_SRCCFG[%s] (CH_SRCCFG[13])

CH_SRCCFG6

CH_SRCCFG[%s] (CH_SRCCFG[14])

CH_SRCCFG7

CH_SRCCFG[%s] (CH_SRCCFG[15])

CH_SRCCFG8

CH_SRCCFG[%s] (CH_SRCCFG[1])

CH_SRCCFG9

CH_SRCCFG[%s] (CH_SRCCFG[16])

CH_SRCCFG10

CH_SRCCFG[%s] (CH_SRCCFG[17])

CH_SRCCFG11

CH_SRCCFG[%s] (CH_SRCCFG[18])

SW_CHTRIG

CH_SRCCFG12

CH_SRCCFG13

CH_SRCCFG[%s] (CH_SRCCFG[19])

CH_SRCCFG14

CH_SRCCFG[%s] (CH_SRCCFG[20])

CH_SRCCFG[%s] (CH_SRCCFG[2])

CH_SRCCFG15

CH_SRCCFG16

CH_SRCCFG[%s] (CH_SRCCFG[21])

CH_SRCCFG17

CH_SRCCFG[%s] (CH_SRCCFG[22])

CH_SRCCFG18

CH_SRCCFG19

CH_SRCCFG[%s] (CH_SRCCFG[23])

CH_SRCCFG20

CH_SRCCFG21

CH_SRCCFG[%s] (CH_SRCCFG[24])

CH_SRCCFG[%s] (CH_SRCCFG[3])

CH_SRCCFG22

CH_SRCCFG23

CH_SRCCFG[%s] (CH_SRCCFG[25])

CH_SRCCFG24

CH_SRCCFG[%s] (CH_SRCCFG[26])

CH_SRCCFG25

CH_SRCCFG26

CH_SRCCFG[%s] (CH_SRCCFG[27])

CH_SRCCFG27

CH_SRCCFG28

CH_SRCCFG[%s] (CH_SRCCFG[28])

CH_SRCCFG29

CH_SRCCFG[%s] (CH_SRCCFG[4])

CH_SRCCFG30

CH_SRCCFG[%s] (CH_SRCCFG[29])

CH_SRCCFG31

CH_SRCCFG[%s] (CH_SRCCFG[30])

CH_SRCCFG[%s] (CH_SRCCFG[31])

CH_SRCCFG[%s] (CH_SRCCFG[5])

CH_SRCCFG[%s] (CH_SRCCFG[6])


DEVICE_CFG

Device Configuration Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVICE_CFG DEVICE_CFG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NUM_DMA_CHANNELS NUM_SRC_PER_CHANNEL

NUM_DMA_CHANNELS : Number of DMA channels available
bits : 0 - 7 (8 bit)
access : read-only

NUM_SRC_PER_CHANNEL : Number of DMA sources per channel
bits : 8 - 15 (8 bit)
access : read-only


CH_SRCCFG0

Channel n Source Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG0 CH_SRCCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[7])

Channel n Source Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


INT1_SRCCFG

Interrupt 1 Source Channel Configuration
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT1_SRCCFG INT1_SRCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC EN

INT_SRC : Controls which channel's completion event is mapped as a source of this Interrupt
bits : 0 - 4 (5 bit)
access : read-write

EN : Enables DMA_INT1 mapping
bits : 5 - 5 (1 bit)
access : read-write


STAT

Status Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTEN STATE DMACHANS TESTSTAT

MASTEN : Enable status of the controller
bits : 0 - 0 (1 bit)
access : read-only

Enumeration: MASTEN_enum_read ( read )

0 : MASTEN_0

Controller disabled

1 : MASTEN_1

Controller enabled

End of enumeration elements list.

STATE : Current state of the control state machine. State can be one of the following:
bits : 4 - 7 (4 bit)
access : read-only

Enumeration: STATE_enum_read ( read )

0 : STATE_0

idle

1 : STATE_1

reading channel controller data

2 : STATE_2

reading source data end pointer

3 : STATE_3

reading destination data end pointer

4 : STATE_4

reading source data

5 : STATE_5

writing destination data

6 : STATE_6

waiting for DMA request to clear

7 : STATE_7

writing channel controller data

8 : STATE_8

stalled

9 : STATE_9

done

10 : STATE_10

peripheral scatter-gather transition

End of enumeration elements list.

DMACHANS : Number of available DMA channels minus one.
bits : 16 - 20 (5 bit)
access : read-only

Enumeration: DMACHANS_enum_read ( read )

0 : DMACHANS_0

Controller configured to use 1 DMA channel

1 : DMACHANS_1

Controller configured to use 2 DMA channels

30 : DMACHANS_30

Controller configured to use 31 DMA channels

31 : DMACHANS_31

Controller configured to use 32 DMA channels

End of enumeration elements list.

TESTSTAT : To reduce the gate count the controller can be configured to exclude the integration test logic. The values 2h to Fh are Reserved.
bits : 28 - 31 (4 bit)
access : read-only

Enumeration: TESTSTAT_enum_read ( read )

0 : TESTSTAT_0

Controller does not include the integration test logic

1 : TESTSTAT_1

Controller includes the integration test logic

End of enumeration elements list.


CFG

Configuration Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CFG CFG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MASTEN CHPROTCTRL

MASTEN : Enable status of the controller
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: MASTEN_enum_write ( write )

0 : MASTEN_0

Controller disabled

1 : MASTEN_1

Controller enabled

End of enumeration elements list.

CHPROTCTRL : Sets the AHB-Lite protection by controlling the HPROT[3:1] signal levels as follows: Bit [7] Controls HPROT[3] to indicate if a cacheable access is occurring. Bit [6] Controls HPROT[2] to indicate if a bufferable access is occurring. Bit [5] Controls HPROT[1] to indicate if a privileged access is occurring. Note: When bit [n] = 1 then the corresponding HPROT is HIGH. When bit [n] = 0 then the corresponding HPROT is LOW.
bits : 5 - 7 (3 bit)
access : write-only


CTLBASE

Channel Control Data Base Pointer Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLBASE CTLBASE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Pointer to the base address of the primary data structure.
bits : 5 - 31 (27 bit)
access : read-write


ALTBASE

Channel Alternate Control Data Base Pointer Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ALTBASE ALTBASE read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : Base address of the alternate data structure
bits : 0 - 31 (32 bit)
access : read-only


WAITSTAT

Channel Wait on Request Status Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WAITSTAT WAITSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAITREQ

WAITREQ : Channel wait on request status.
bits : 0 - 31 (32 bit)
access : read-only

Enumeration: WAITREQ_enum_read ( read )

0 : WAITREQ_0

dma_waitonreq[C] is LOW.

1 : WAITREQ_1

dma_waitonreq[C] is HIGH.

End of enumeration elements list.


SWREQ

Channel Software Request Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWREQ SWREQ write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHNL_SW_REQ

CHNL_SW_REQ : Set the appropriate bit to generate a software DMA request on the corresponding DMA channel. Writing to a bit where a DMA channel is not implemented does not create a DMA request for that channel.
bits : 0 - 31 (32 bit)
access : write-only

Enumeration: CHNL_SW_REQ_enum_write ( write )

0 : CHNL_SW_REQ_0

Does not create a DMA request for the channel

1 : CHNL_SW_REQ_1

Creates a DMA request for the channel

End of enumeration elements list.


USEBURSTSET

Channel Useburst Set Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USEBURSTSET USEBURSTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET

SET : Returns the useburst status, or disables dma_sreq from generating DMA requests.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration: SET_enum_write ( write )

0 : SET_0_WRITE

No effect. Use the DMA_USEBURST_CLR Register to set bit [C] to 0.

1 : SET_1_WRITE

Disables dma_sreq[C] from generating DMA requests. The controller performs 2R transfers. Writing to a bit where a DMA channel is not implemented has no effect.

0 : SET_0_READ

DMA channel C responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2R, or single, bus transfers.

1 : SET_1_READ

DMA channel C does not respond to requests that it receives on dma_sreq[C]. The controller only responds to dma_req[C] requests and performs 2R transfers.

End of enumeration elements list.


USEBURSTCLR

Channel Useburst Clear Register
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USEBURSTCLR USEBURSTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : Set the appropriate bit to enable dma_sreq to generate requests.
bits : 0 - 31 (32 bit)
access : write-only

Enumeration: CLR_enum_write ( write )

0 : CLR_0

No effect. Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests.

1 : CLR_1

Enables dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect.

End of enumeration elements list.


REQMASKSET

Channel Request Mask Set Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQMASKSET REQMASKSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET

SET : Returns the request mask status of dma_req and dma_sreq, or disables the corresponding channel from generating DMA requests.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration: SET_enum_write ( write )

0 : SET_0_WRITE

No effect. Use the DMA_REQMASKCLR Register to enable DMA requests.

1 : SET_1_WRITE

Disables dma_req[C] and dma_sreq[C] from generating DMA requests. Writing to a bit where a DMA channel is not implemented has no effect.

0 : SET_0_READ

External requests are enabled for channel C.

1 : SET_1_READ

External requests are disabled for channel C.

End of enumeration elements list.


REQMASKCLR

Channel Request Mask Clear Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

REQMASKCLR REQMASKCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req and dma_sreq.
bits : 0 - 31 (32 bit)
access : write-only

Enumeration: CLR_enum_write ( write )

0 : CLR_0

No effect. Use the DMA_REQMASKSET Register to disable dma_req and dma_sreq from generating requests.

1 : CLR_1

Enables dma_req[C] or dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect.

End of enumeration elements list.


ENASET

Channel Enable Set Register
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENASET ENASET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET

SET : Returns the enable status of the channels, or enables the corresponding channels.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration: SET_enum_write ( write )

0 : SET_0_WRITE

No effect. Use the DMA_ENACLR Register to disable a channel.

1 : SET_1_WRITE

Enables channel C. Writing to a bit where a DMA channel is not implemented has no effect.

0 : SET_0_READ

Channel C is disabled.

1 : SET_1_READ

Channel C is enabled.

End of enumeration elements list.


ENACLR

Channel Enable Clear Register
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ENACLR ENACLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus.
bits : 0 - 31 (32 bit)
access : write-only

Enumeration: CLR_enum_write ( write )

0 : CLR_0

No effect. Use the DMA_ENASET Register to enable DMA channels.

1 : CLR_1

Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect.

End of enumeration elements list.


ALTSET

Channel Primary-Alternate Set Register
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALTSET ALTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET

SET : Channel Primary-Alternate Set Register
bits : 0 - 31 (32 bit)
access : read-write

Enumeration: SET_enum_write ( write )

0 : SEL_0_WRITE

No effect. Use the DMA_ALTCLR Register to set bit [C] to 0.

1 : SEL_1_WRITE

Selects the alternate data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect.

0 : SET_0_READ

DMA channel C is using the primary data structure.

1 : SET_1_READ

DMA channel C is using the alternate data structure.

End of enumeration elements list.


ALTCLR

Channel Primary-Alternate Clear Register
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ALTCLR ALTCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : Channel Primary-Alternate Clear Register
bits : 0 - 31 (32 bit)
access : write-only

Enumeration: CLR_enum_write ( write )

0 : CLR_0

No effect. Use the DMA_ALTSET Register to select the alternate data structure.

1 : CLR_1

Selects the primary data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect.

End of enumeration elements list.


PRIOSET

Channel Priority Set Register
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIOSET PRIOSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SET

SET : Returns the channel priority mask status, or sets the channel priority to high.
bits : 0 - 31 (32 bit)
access : read-write

Enumeration: SET_enum_write ( write )

0 : SET_0_WRITE

No effect. Use the DMA_PRIOCLR Register to set channel C to the default priority level.

1 : SET_1_WRITE

Channel C uses the high priority level. Writing to a bit where a DMA channel is not implemented has no effect.

0 : SET_0_READ

DMA channel C is using the default priority level.

1 : SET_1_READ

DMA channel C is using a high priority level.

End of enumeration elements list.


PRIOCLR

Channel Priority Clear Register
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PRIOCLR PRIOCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : Set the appropriate bit to select the default priority level for the specified DMA channel.
bits : 0 - 31 (32 bit)
access : write-only

Enumeration: CLR_enum_write ( write )

0 : CLR_0

No effect. Use the DMA_PRIOSET Register to set channel C to the high priority level.

1 : CLR_1

Channel C uses the default priority level. Writing to a bit where a DMA channel is not implemented has no effect.

End of enumeration elements list.


INT2_SRCCFG

Interrupt 2 Source Channel Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT2_SRCCFG INT2_SRCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC EN

INT_SRC : Controls which channel's completion event is mapped as a source of this Interrupt
bits : 0 - 4 (5 bit)
access : read-write

EN : Enables DMA_INT2 mapping
bits : 5 - 5 (1 bit)
access : read-write


ERRCLR

Bus Error Clear Register
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ERRCLR ERRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ERRCLR

ERRCLR : Returns the status of dma_err, or sets the signal LOW. For test purposes, use the ERRSET register to set dma_err HIGH. Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted.
bits : 0 - 0 (1 bit)
access : read-write

Enumeration: ERRCLR_enum_write ( write )

0 : ERRCLR_0_WRITE

No effect, status of dma_err is unchanged.

1 : ERRCLR_1_WRITE

Sets dma_err LOW.

0 : ERRCLR_0_READ

dma_err is LOW

1 : ERRCLR_1_READ

dma_err is HIGH.

End of enumeration elements list.


INT3_SRCCFG

Interrupt 3 Source Channel Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT3_SRCCFG INT3_SRCCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_SRC EN

INT_SRC : Controls which channel's completion event is mapped as a source of this Interrupt
bits : 0 - 4 (5 bit)
access : read-write

EN : Enables DMA_INT3 mapping
bits : 5 - 5 (1 bit)
access : read-write


INT0_SRCFLG

Interrupt 0 Source Channel Flag Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

INT0_SRCFLG INT0_SRCFLG read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31

CH0 : Channel 0 was the source of DMA_INT0
bits : 0 - 0 (1 bit)
access : read-only

CH1 : Channel 1 was the source of DMA_INT0
bits : 1 - 1 (1 bit)
access : read-only

CH2 : Channel 2 was the source of DMA_INT0
bits : 2 - 2 (1 bit)
access : read-only

CH3 : Channel 3 was the source of DMA_INT0
bits : 3 - 3 (1 bit)
access : read-only

CH4 : Channel 4 was the source of DMA_INT0
bits : 4 - 4 (1 bit)
access : read-only

CH5 : Channel 5 was the source of DMA_INT0
bits : 5 - 5 (1 bit)
access : read-only

CH6 : Channel 6 was the source of DMA_INT0
bits : 6 - 6 (1 bit)
access : read-only

CH7 : Channel 7 was the source of DMA_INT0
bits : 7 - 7 (1 bit)
access : read-only

CH8 : Channel 8 was the source of DMA_INT0
bits : 8 - 8 (1 bit)
access : read-only

CH9 : Channel 9 was the source of DMA_INT0
bits : 9 - 9 (1 bit)
access : read-only

CH10 : Channel 10 was the source of DMA_INT0
bits : 10 - 10 (1 bit)
access : read-only

CH11 : Channel 11 was the source of DMA_INT0
bits : 11 - 11 (1 bit)
access : read-only

CH12 : Channel 12 was the source of DMA_INT0
bits : 12 - 12 (1 bit)
access : read-only

CH13 : Channel 13 was the source of DMA_INT0
bits : 13 - 13 (1 bit)
access : read-only

CH14 : Channel 14 was the source of DMA_INT0
bits : 14 - 14 (1 bit)
access : read-only

CH15 : Channel 15 was the source of DMA_INT0
bits : 15 - 15 (1 bit)
access : read-only

CH16 : Channel 16 was the source of DMA_INT0
bits : 16 - 16 (1 bit)
access : read-only

CH17 : Channel 17 was the source of DMA_INT0
bits : 17 - 17 (1 bit)
access : read-only

CH18 : Channel 18 was the source of DMA_INT0
bits : 18 - 18 (1 bit)
access : read-only

CH19 : Channel 19 was the source of DMA_INT0
bits : 19 - 19 (1 bit)
access : read-only

CH20 : Channel 20 was the source of DMA_INT0
bits : 20 - 20 (1 bit)
access : read-only

CH21 : Channel 21 was the source of DMA_INT0
bits : 21 - 21 (1 bit)
access : read-only

CH22 : Channel 22 was the source of DMA_INT0
bits : 22 - 22 (1 bit)
access : read-only

CH23 : Channel 23 was the source of DMA_INT0
bits : 23 - 23 (1 bit)
access : read-only

CH24 : Channel 24 was the source of DMA_INT0
bits : 24 - 24 (1 bit)
access : read-only

CH25 : Channel 25 was the source of DMA_INT0
bits : 25 - 25 (1 bit)
access : read-only

CH26 : Channel 26 was the source of DMA_INT0
bits : 26 - 26 (1 bit)
access : read-only

CH27 : Channel 27 was the source of DMA_INT0
bits : 27 - 27 (1 bit)
access : read-only

CH28 : Channel 28 was the source of DMA_INT0
bits : 28 - 28 (1 bit)
access : read-only

CH29 : Channel 29 was the source of DMA_INT0
bits : 29 - 29 (1 bit)
access : read-only

CH30 : Channel 30 was the source of DMA_INT0
bits : 30 - 30 (1 bit)
access : read-only

CH31 : Channel 31 was the source of DMA_INT0
bits : 31 - 31 (1 bit)
access : read-only


INT0_CLRFLG

Interrupt 0 Source Channel Clear Flag Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

INT0_CLRFLG INT0_CLRFLG write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31

CH0 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 0 - 0 (1 bit)
access : write-only

CH1 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 1 - 1 (1 bit)
access : write-only

CH2 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 2 - 2 (1 bit)
access : write-only

CH3 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 3 - 3 (1 bit)
access : write-only

CH4 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 4 - 4 (1 bit)
access : write-only

CH5 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 5 - 5 (1 bit)
access : write-only

CH6 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 6 - 6 (1 bit)
access : write-only

CH7 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 7 - 7 (1 bit)
access : write-only

CH8 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 8 - 8 (1 bit)
access : write-only

CH9 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 9 - 9 (1 bit)
access : write-only

CH10 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 10 - 10 (1 bit)
access : write-only

CH11 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 11 - 11 (1 bit)
access : write-only

CH12 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 12 - 12 (1 bit)
access : write-only

CH13 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 13 - 13 (1 bit)
access : write-only

CH14 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 14 - 14 (1 bit)
access : write-only

CH15 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 15 - 15 (1 bit)
access : write-only

CH16 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 16 - 16 (1 bit)
access : write-only

CH17 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 17 - 17 (1 bit)
access : write-only

CH18 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 18 - 18 (1 bit)
access : write-only

CH19 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 19 - 19 (1 bit)
access : write-only

CH20 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 20 - 20 (1 bit)
access : write-only

CH21 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 21 - 21 (1 bit)
access : write-only

CH22 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 22 - 22 (1 bit)
access : write-only

CH23 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 23 - 23 (1 bit)
access : write-only

CH24 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 24 - 24 (1 bit)
access : write-only

CH25 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 25 - 25 (1 bit)
access : write-only

CH26 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 26 - 26 (1 bit)
access : write-only

CH27 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 27 - 27 (1 bit)
access : write-only

CH28 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 28 - 28 (1 bit)
access : write-only

CH29 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 29 - 29 (1 bit)
access : write-only

CH30 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 30 - 30 (1 bit)
access : write-only

CH31 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 31 - 31 (1 bit)
access : write-only


CH_SRCCFG[%s] (CH_SRCCFG[8])

Channel n Source Configuration Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG1

Channel n Source Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG1 CH_SRCCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[9])

Channel n Source Configuration Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG2

Channel n Source Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG2 CH_SRCCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[10])

Channel n Source Configuration Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG3

Channel n Source Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG3 CH_SRCCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[11])

Channel n Source Configuration Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[0])

Channel n Source Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG4

Channel n Source Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG4 CH_SRCCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[12])

Channel n Source Configuration Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG5

Channel n Source Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG5 CH_SRCCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[13])

Channel n Source Configuration Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG6

Channel n Source Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG6 CH_SRCCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[14])

Channel n Source Configuration Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG7

Channel n Source Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG7 CH_SRCCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[15])

Channel n Source Configuration Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG8

Channel n Source Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG8 CH_SRCCFG8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[1])

Channel n Source Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG9

Channel n Source Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG9 CH_SRCCFG9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[16])

Channel n Source Configuration Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG10

Channel n Source Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG10 CH_SRCCFG10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[17])

Channel n Source Configuration Register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG11

Channel n Source Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG11 CH_SRCCFG11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[18])

Channel n Source Configuration Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


SW_CHTRIG

Software Channel Trigger Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SW_CHTRIG SW_CHTRIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11 CH12 CH13 CH14 CH15 CH16 CH17 CH18 CH19 CH20 CH21 CH22 CH23 CH24 CH25 CH26 CH27 CH28 CH29 CH30 CH31

CH0 : Write 1, triggers DMA_CHANNEL0
bits : 0 - 0 (1 bit)
access : read-write

CH1 : Write 1, triggers DMA_CHANNEL1
bits : 1 - 1 (1 bit)
access : read-write

CH2 : Write 1, triggers DMA_CHANNEL2
bits : 2 - 2 (1 bit)
access : read-write

CH3 : Write 1, triggers DMA_CHANNEL3
bits : 3 - 3 (1 bit)
access : read-write

CH4 : Write 1, triggers DMA_CHANNEL4
bits : 4 - 4 (1 bit)
access : read-write

CH5 : Write 1, triggers DMA_CHANNEL5
bits : 5 - 5 (1 bit)
access : read-write

CH6 : Write 1, triggers DMA_CHANNEL6
bits : 6 - 6 (1 bit)
access : read-write

CH7 : Write 1, triggers DMA_CHANNEL7
bits : 7 - 7 (1 bit)
access : read-write

CH8 : Write 1, triggers DMA_CHANNEL8
bits : 8 - 8 (1 bit)
access : read-write

CH9 : Write 1, triggers DMA_CHANNEL9
bits : 9 - 9 (1 bit)
access : read-write

CH10 : Write 1, triggers DMA_CHANNEL10
bits : 10 - 10 (1 bit)
access : read-write

CH11 : Write 1, triggers DMA_CHANNEL11
bits : 11 - 11 (1 bit)
access : read-write

CH12 : Write 1, triggers DMA_CHANNEL12
bits : 12 - 12 (1 bit)
access : read-write

CH13 : Write 1, triggers DMA_CHANNEL13
bits : 13 - 13 (1 bit)
access : read-write

CH14 : Write 1, triggers DMA_CHANNEL14
bits : 14 - 14 (1 bit)
access : read-write

CH15 : Write 1, triggers DMA_CHANNEL15
bits : 15 - 15 (1 bit)
access : read-write

CH16 : Write 1, triggers DMA_CHANNEL16
bits : 16 - 16 (1 bit)
access : read-write

CH17 : Write 1, triggers DMA_CHANNEL17
bits : 17 - 17 (1 bit)
access : read-write

CH18 : Write 1, triggers DMA_CHANNEL18
bits : 18 - 18 (1 bit)
access : read-write

CH19 : Write 1, triggers DMA_CHANNEL19
bits : 19 - 19 (1 bit)
access : read-write

CH20 : Write 1, triggers DMA_CHANNEL20
bits : 20 - 20 (1 bit)
access : read-write

CH21 : Write 1, triggers DMA_CHANNEL21
bits : 21 - 21 (1 bit)
access : read-write

CH22 : Write 1, triggers DMA_CHANNEL22
bits : 22 - 22 (1 bit)
access : read-write

CH23 : Write 1, triggers DMA_CHANNEL23
bits : 23 - 23 (1 bit)
access : read-write

CH24 : Write 1, triggers DMA_CHANNEL24
bits : 24 - 24 (1 bit)
access : read-write

CH25 : Write 1, triggers DMA_CHANNEL25
bits : 25 - 25 (1 bit)
access : read-write

CH26 : Write 1, triggers DMA_CHANNEL26
bits : 26 - 26 (1 bit)
access : read-write

CH27 : Write 1, triggers DMA_CHANNEL27
bits : 27 - 27 (1 bit)
access : read-write

CH28 : Write 1, triggers DMA_CHANNEL28
bits : 28 - 28 (1 bit)
access : read-write

CH29 : Write 1, triggers DMA_CHANNEL29
bits : 29 - 29 (1 bit)
access : read-write

CH30 : Write 1, triggers DMA_CHANNEL30
bits : 30 - 30 (1 bit)
access : read-write

CH31 : Write 1, triggers DMA_CHANNEL31
bits : 31 - 31 (1 bit)
access : read-write


CH_SRCCFG12

Channel n Source Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG12 CH_SRCCFG12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG13

Channel n Source Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG13 CH_SRCCFG13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[19])

Channel n Source Configuration Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG14

Channel n Source Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG14 CH_SRCCFG14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[20])

Channel n Source Configuration Register
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[2])

Channel n Source Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG15

Channel n Source Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG15 CH_SRCCFG15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG16

Channel n Source Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG16 CH_SRCCFG16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[21])

Channel n Source Configuration Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG17

Channel n Source Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG17 CH_SRCCFG17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[22])

Channel n Source Configuration Register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG18

Channel n Source Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG18 CH_SRCCFG18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG19

Channel n Source Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG19 CH_SRCCFG19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[23])

Channel n Source Configuration Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG20

Channel n Source Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG20 CH_SRCCFG20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG21

Channel n Source Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG21 CH_SRCCFG21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[24])

Channel n Source Configuration Register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[3])

Channel n Source Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG22

Channel n Source Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG22 CH_SRCCFG22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG23

Channel n Source Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG23 CH_SRCCFG23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[25])

Channel n Source Configuration Register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG24

Channel n Source Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG24 CH_SRCCFG24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[26])

Channel n Source Configuration Register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG25

Channel n Source Configuration Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG25 CH_SRCCFG25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG26

Channel n Source Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG26 CH_SRCCFG26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[27])

Channel n Source Configuration Register
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG27

Channel n Source Configuration Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG27 CH_SRCCFG27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG28

Channel n Source Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG28 CH_SRCCFG28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[28])

Channel n Source Configuration Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG29

Channel n Source Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG29 CH_SRCCFG29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[4])

Channel n Source Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG30

Channel n Source Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG30 CH_SRCCFG30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[29])

Channel n Source Configuration Register
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG31

Channel n Source Configuration Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG31 CH_SRCCFG31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[30])

Channel n Source Configuration Register
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[31])

Channel n Source Configuration Register
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[5])

Channel n Source Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write


CH_SRCCFG[%s] (CH_SRCCFG[6])

Channel n Source Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH_SRCCFG[%s] CH_SRCCFG[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_SRC

DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.