\n
address_offset : 0x0 Bytes (0x0)
size : 0x1050 byte (0x0)
mem_usage : registers
protection : not protected
Device Configuration Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
NUM_DMA_CHANNELS : Number of DMA channels available
bits : 0 - 7 (8 bit)
access : read-only
NUM_SRC_PER_CHANNEL : Number of DMA sources per channel
bits : 8 - 15 (8 bit)
access : read-only
Channel n Source Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Interrupt 1 Source Channel Configuration
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Controls which channel's completion event is mapped as a source of this Interrupt
bits : 0 - 4 (5 bit)
access : read-write
EN : Enables DMA_INT1 mapping
bits : 5 - 5 (1 bit)
access : read-write
Status Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MASTEN : Enable status of the controller
bits : 0 - 0 (1 bit)
access : read-only
Enumeration: MASTEN_enum_read ( read )
0 : MASTEN_0
Controller disabled
1 : MASTEN_1
Controller enabled
End of enumeration elements list.
STATE : Current state of the control state machine. State can be one of the following:
bits : 4 - 7 (4 bit)
access : read-only
Enumeration: STATE_enum_read ( read )
0 : STATE_0
idle
1 : STATE_1
reading channel controller data
2 : STATE_2
reading source data end pointer
3 : STATE_3
reading destination data end pointer
4 : STATE_4
reading source data
5 : STATE_5
writing destination data
6 : STATE_6
waiting for DMA request to clear
7 : STATE_7
writing channel controller data
8 : STATE_8
stalled
9 : STATE_9
done
10 : STATE_10
peripheral scatter-gather transition
End of enumeration elements list.
DMACHANS : Number of available DMA channels minus one.
bits : 16 - 20 (5 bit)
access : read-only
Enumeration: DMACHANS_enum_read ( read )
0 : DMACHANS_0
Controller configured to use 1 DMA channel
1 : DMACHANS_1
Controller configured to use 2 DMA channels
30 : DMACHANS_30
Controller configured to use 31 DMA channels
31 : DMACHANS_31
Controller configured to use 32 DMA channels
End of enumeration elements list.
TESTSTAT : To reduce the gate count the controller can be configured to exclude the integration test logic. The values 2h to Fh are Reserved.
bits : 28 - 31 (4 bit)
access : read-only
Enumeration: TESTSTAT_enum_read ( read )
0 : TESTSTAT_0
Controller does not include the integration test logic
1 : TESTSTAT_1
Controller includes the integration test logic
End of enumeration elements list.
Configuration Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MASTEN : Enable status of the controller
bits : 0 - 0 (1 bit)
access : write-only
Enumeration: MASTEN_enum_write ( write )
0 : MASTEN_0
Controller disabled
1 : MASTEN_1
Controller enabled
End of enumeration elements list.
CHPROTCTRL : Sets the AHB-Lite protection by controlling the HPROT[3:1] signal levels as follows: Bit [7] Controls HPROT[3] to indicate if a cacheable access is occurring. Bit [6] Controls HPROT[2] to indicate if a bufferable access is occurring. Bit [5] Controls HPROT[1] to indicate if a privileged access is occurring. Note: When bit [n] = 1 then the corresponding HPROT is HIGH. When bit [n] = 0 then the corresponding HPROT is LOW.
bits : 5 - 7 (3 bit)
access : write-only
Channel Control Data Base Pointer Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : Pointer to the base address of the primary data structure.
bits : 5 - 31 (27 bit)
access : read-write
Channel Alternate Control Data Base Pointer Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ADDR : Base address of the alternate data structure
bits : 0 - 31 (32 bit)
access : read-only
Channel Wait on Request Status Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WAITREQ : Channel wait on request status.
bits : 0 - 31 (32 bit)
access : read-only
Enumeration: WAITREQ_enum_read ( read )
0 : WAITREQ_0
dma_waitonreq[C] is LOW.
1 : WAITREQ_1
dma_waitonreq[C] is HIGH.
End of enumeration elements list.
Channel Software Request Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNL_SW_REQ : Set the appropriate bit to generate a software DMA request on the corresponding DMA channel. Writing to a bit where a DMA channel is not implemented does not create a DMA request for that channel.
bits : 0 - 31 (32 bit)
access : write-only
Enumeration: CHNL_SW_REQ_enum_write ( write )
0 : CHNL_SW_REQ_0
Does not create a DMA request for the channel
1 : CHNL_SW_REQ_1
Creates a DMA request for the channel
End of enumeration elements list.
Channel Useburst Set Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : Returns the useburst status, or disables dma_sreq from generating DMA requests.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration: SET_enum_write ( write )
0 : SET_0_WRITE
No effect. Use the DMA_USEBURST_CLR Register to set bit [C] to 0.
1 : SET_1_WRITE
Disables dma_sreq[C] from generating DMA requests. The controller performs 2R transfers. Writing to a bit where a DMA channel is not implemented has no effect.
0 : SET_0_READ
DMA channel C responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2R, or single, bus transfers.
1 : SET_1_READ
DMA channel C does not respond to requests that it receives on dma_sreq[C]. The controller only responds to dma_req[C] requests and performs 2R transfers.
End of enumeration elements list.
Channel Useburst Clear Register
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Set the appropriate bit to enable dma_sreq to generate requests.
bits : 0 - 31 (32 bit)
access : write-only
Enumeration: CLR_enum_write ( write )
0 : CLR_0
No effect. Use the DMA_USEBURST_SET Register to disable dma_sreq from generating requests.
1 : CLR_1
Enables dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect.
End of enumeration elements list.
Channel Request Mask Set Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : Returns the request mask status of dma_req and dma_sreq, or disables the corresponding channel from generating DMA requests.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration: SET_enum_write ( write )
0 : SET_0_WRITE
No effect. Use the DMA_REQMASKCLR Register to enable DMA requests.
1 : SET_1_WRITE
Disables dma_req[C] and dma_sreq[C] from generating DMA requests. Writing to a bit where a DMA channel is not implemented has no effect.
0 : SET_0_READ
External requests are enabled for channel C.
1 : SET_1_READ
External requests are disabled for channel C.
End of enumeration elements list.
Channel Request Mask Clear Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req and dma_sreq.
bits : 0 - 31 (32 bit)
access : write-only
Enumeration: CLR_enum_write ( write )
0 : CLR_0
No effect. Use the DMA_REQMASKSET Register to disable dma_req and dma_sreq from generating requests.
1 : CLR_1
Enables dma_req[C] or dma_sreq[C] to generate DMA requests. Writing to a bit where a DMA channel is not implemented has no effect.
End of enumeration elements list.
Channel Enable Set Register
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : Returns the enable status of the channels, or enables the corresponding channels.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration: SET_enum_write ( write )
0 : SET_0_WRITE
No effect. Use the DMA_ENACLR Register to disable a channel.
1 : SET_1_WRITE
Enables channel C. Writing to a bit where a DMA channel is not implemented has no effect.
0 : SET_0_READ
Channel C is disabled.
1 : SET_1_READ
Channel C is enabled.
End of enumeration elements list.
Channel Enable Clear Register
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus.
bits : 0 - 31 (32 bit)
access : write-only
Enumeration: CLR_enum_write ( write )
0 : CLR_0
No effect. Use the DMA_ENASET Register to enable DMA channels.
1 : CLR_1
Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect.
End of enumeration elements list.
Channel Primary-Alternate Set Register
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : Channel Primary-Alternate Set Register
bits : 0 - 31 (32 bit)
access : read-write
Enumeration: SET_enum_write ( write )
0 : SEL_0_WRITE
No effect. Use the DMA_ALTCLR Register to set bit [C] to 0.
1 : SEL_1_WRITE
Selects the alternate data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect.
0 : SET_0_READ
DMA channel C is using the primary data structure.
1 : SET_1_READ
DMA channel C is using the alternate data structure.
End of enumeration elements list.
Channel Primary-Alternate Clear Register
address_offset : 0x1034 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Channel Primary-Alternate Clear Register
bits : 0 - 31 (32 bit)
access : write-only
Enumeration: CLR_enum_write ( write )
0 : CLR_0
No effect. Use the DMA_ALTSET Register to select the alternate data structure.
1 : CLR_1
Selects the primary data structure for channel C. Writing to a bit where a DMA channel is not implemented has no effect.
End of enumeration elements list.
Channel Priority Set Register
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET : Returns the channel priority mask status, or sets the channel priority to high.
bits : 0 - 31 (32 bit)
access : read-write
Enumeration: SET_enum_write ( write )
0 : SET_0_WRITE
No effect. Use the DMA_PRIOCLR Register to set channel C to the default priority level.
1 : SET_1_WRITE
Channel C uses the high priority level. Writing to a bit where a DMA channel is not implemented has no effect.
0 : SET_0_READ
DMA channel C is using the default priority level.
1 : SET_1_READ
DMA channel C is using a high priority level.
End of enumeration elements list.
Channel Priority Clear Register
address_offset : 0x103C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLR : Set the appropriate bit to select the default priority level for the specified DMA channel.
bits : 0 - 31 (32 bit)
access : write-only
Enumeration: CLR_enum_write ( write )
0 : CLR_0
No effect. Use the DMA_PRIOSET Register to set channel C to the high priority level.
1 : CLR_1
Channel C uses the default priority level. Writing to a bit where a DMA channel is not implemented has no effect.
End of enumeration elements list.
Interrupt 2 Source Channel Configuration Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Controls which channel's completion event is mapped as a source of this Interrupt
bits : 0 - 4 (5 bit)
access : read-write
EN : Enables DMA_INT2 mapping
bits : 5 - 5 (1 bit)
access : read-write
Bus Error Clear Register
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERRCLR : Returns the status of dma_err, or sets the signal LOW. For test purposes, use the ERRSET register to set dma_err HIGH. Note: If you deassert dma_err at the same time as an ERROR occurs on the AHB-Lite bus, then the ERROR condition takes precedence and dma_err remains asserted.
bits : 0 - 0 (1 bit)
access : read-write
Enumeration: ERRCLR_enum_write ( write )
0 : ERRCLR_0_WRITE
No effect, status of dma_err is unchanged.
1 : ERRCLR_1_WRITE
Sets dma_err LOW.
0 : ERRCLR_0_READ
dma_err is LOW
1 : ERRCLR_1_READ
dma_err is HIGH.
End of enumeration elements list.
Interrupt 3 Source Channel Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INT_SRC : Controls which channel's completion event is mapped as a source of this Interrupt
bits : 0 - 4 (5 bit)
access : read-write
EN : Enables DMA_INT3 mapping
bits : 5 - 5 (1 bit)
access : read-write
Interrupt 0 Source Channel Flag Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Channel 0 was the source of DMA_INT0
bits : 0 - 0 (1 bit)
access : read-only
CH1 : Channel 1 was the source of DMA_INT0
bits : 1 - 1 (1 bit)
access : read-only
CH2 : Channel 2 was the source of DMA_INT0
bits : 2 - 2 (1 bit)
access : read-only
CH3 : Channel 3 was the source of DMA_INT0
bits : 3 - 3 (1 bit)
access : read-only
CH4 : Channel 4 was the source of DMA_INT0
bits : 4 - 4 (1 bit)
access : read-only
CH5 : Channel 5 was the source of DMA_INT0
bits : 5 - 5 (1 bit)
access : read-only
CH6 : Channel 6 was the source of DMA_INT0
bits : 6 - 6 (1 bit)
access : read-only
CH7 : Channel 7 was the source of DMA_INT0
bits : 7 - 7 (1 bit)
access : read-only
CH8 : Channel 8 was the source of DMA_INT0
bits : 8 - 8 (1 bit)
access : read-only
CH9 : Channel 9 was the source of DMA_INT0
bits : 9 - 9 (1 bit)
access : read-only
CH10 : Channel 10 was the source of DMA_INT0
bits : 10 - 10 (1 bit)
access : read-only
CH11 : Channel 11 was the source of DMA_INT0
bits : 11 - 11 (1 bit)
access : read-only
CH12 : Channel 12 was the source of DMA_INT0
bits : 12 - 12 (1 bit)
access : read-only
CH13 : Channel 13 was the source of DMA_INT0
bits : 13 - 13 (1 bit)
access : read-only
CH14 : Channel 14 was the source of DMA_INT0
bits : 14 - 14 (1 bit)
access : read-only
CH15 : Channel 15 was the source of DMA_INT0
bits : 15 - 15 (1 bit)
access : read-only
CH16 : Channel 16 was the source of DMA_INT0
bits : 16 - 16 (1 bit)
access : read-only
CH17 : Channel 17 was the source of DMA_INT0
bits : 17 - 17 (1 bit)
access : read-only
CH18 : Channel 18 was the source of DMA_INT0
bits : 18 - 18 (1 bit)
access : read-only
CH19 : Channel 19 was the source of DMA_INT0
bits : 19 - 19 (1 bit)
access : read-only
CH20 : Channel 20 was the source of DMA_INT0
bits : 20 - 20 (1 bit)
access : read-only
CH21 : Channel 21 was the source of DMA_INT0
bits : 21 - 21 (1 bit)
access : read-only
CH22 : Channel 22 was the source of DMA_INT0
bits : 22 - 22 (1 bit)
access : read-only
CH23 : Channel 23 was the source of DMA_INT0
bits : 23 - 23 (1 bit)
access : read-only
CH24 : Channel 24 was the source of DMA_INT0
bits : 24 - 24 (1 bit)
access : read-only
CH25 : Channel 25 was the source of DMA_INT0
bits : 25 - 25 (1 bit)
access : read-only
CH26 : Channel 26 was the source of DMA_INT0
bits : 26 - 26 (1 bit)
access : read-only
CH27 : Channel 27 was the source of DMA_INT0
bits : 27 - 27 (1 bit)
access : read-only
CH28 : Channel 28 was the source of DMA_INT0
bits : 28 - 28 (1 bit)
access : read-only
CH29 : Channel 29 was the source of DMA_INT0
bits : 29 - 29 (1 bit)
access : read-only
CH30 : Channel 30 was the source of DMA_INT0
bits : 30 - 30 (1 bit)
access : read-only
CH31 : Channel 31 was the source of DMA_INT0
bits : 31 - 31 (1 bit)
access : read-only
Interrupt 0 Source Channel Clear Flag Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CH0 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 0 - 0 (1 bit)
access : write-only
CH1 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 1 - 1 (1 bit)
access : write-only
CH2 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 2 - 2 (1 bit)
access : write-only
CH3 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 3 - 3 (1 bit)
access : write-only
CH4 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 4 - 4 (1 bit)
access : write-only
CH5 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 5 - 5 (1 bit)
access : write-only
CH6 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 6 - 6 (1 bit)
access : write-only
CH7 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 7 - 7 (1 bit)
access : write-only
CH8 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 8 - 8 (1 bit)
access : write-only
CH9 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 9 - 9 (1 bit)
access : write-only
CH10 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 10 - 10 (1 bit)
access : write-only
CH11 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 11 - 11 (1 bit)
access : write-only
CH12 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 12 - 12 (1 bit)
access : write-only
CH13 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 13 - 13 (1 bit)
access : write-only
CH14 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 14 - 14 (1 bit)
access : write-only
CH15 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 15 - 15 (1 bit)
access : write-only
CH16 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 16 - 16 (1 bit)
access : write-only
CH17 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 17 - 17 (1 bit)
access : write-only
CH18 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 18 - 18 (1 bit)
access : write-only
CH19 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 19 - 19 (1 bit)
access : write-only
CH20 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 20 - 20 (1 bit)
access : write-only
CH21 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 21 - 21 (1 bit)
access : write-only
CH22 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 22 - 22 (1 bit)
access : write-only
CH23 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 23 - 23 (1 bit)
access : write-only
CH24 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 24 - 24 (1 bit)
access : write-only
CH25 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 25 - 25 (1 bit)
access : write-only
CH26 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 26 - 26 (1 bit)
access : write-only
CH27 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 27 - 27 (1 bit)
access : write-only
CH28 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 28 - 28 (1 bit)
access : write-only
CH29 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 29 - 29 (1 bit)
access : write-only
CH30 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 30 - 30 (1 bit)
access : write-only
CH31 : Clear corresponding DMA_INT0_SRCFLG_REG
bits : 31 - 31 (1 bit)
access : write-only
Channel n Source Configuration Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Software Channel Trigger Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0 : Write 1, triggers DMA_CHANNEL0
bits : 0 - 0 (1 bit)
access : read-write
CH1 : Write 1, triggers DMA_CHANNEL1
bits : 1 - 1 (1 bit)
access : read-write
CH2 : Write 1, triggers DMA_CHANNEL2
bits : 2 - 2 (1 bit)
access : read-write
CH3 : Write 1, triggers DMA_CHANNEL3
bits : 3 - 3 (1 bit)
access : read-write
CH4 : Write 1, triggers DMA_CHANNEL4
bits : 4 - 4 (1 bit)
access : read-write
CH5 : Write 1, triggers DMA_CHANNEL5
bits : 5 - 5 (1 bit)
access : read-write
CH6 : Write 1, triggers DMA_CHANNEL6
bits : 6 - 6 (1 bit)
access : read-write
CH7 : Write 1, triggers DMA_CHANNEL7
bits : 7 - 7 (1 bit)
access : read-write
CH8 : Write 1, triggers DMA_CHANNEL8
bits : 8 - 8 (1 bit)
access : read-write
CH9 : Write 1, triggers DMA_CHANNEL9
bits : 9 - 9 (1 bit)
access : read-write
CH10 : Write 1, triggers DMA_CHANNEL10
bits : 10 - 10 (1 bit)
access : read-write
CH11 : Write 1, triggers DMA_CHANNEL11
bits : 11 - 11 (1 bit)
access : read-write
CH12 : Write 1, triggers DMA_CHANNEL12
bits : 12 - 12 (1 bit)
access : read-write
CH13 : Write 1, triggers DMA_CHANNEL13
bits : 13 - 13 (1 bit)
access : read-write
CH14 : Write 1, triggers DMA_CHANNEL14
bits : 14 - 14 (1 bit)
access : read-write
CH15 : Write 1, triggers DMA_CHANNEL15
bits : 15 - 15 (1 bit)
access : read-write
CH16 : Write 1, triggers DMA_CHANNEL16
bits : 16 - 16 (1 bit)
access : read-write
CH17 : Write 1, triggers DMA_CHANNEL17
bits : 17 - 17 (1 bit)
access : read-write
CH18 : Write 1, triggers DMA_CHANNEL18
bits : 18 - 18 (1 bit)
access : read-write
CH19 : Write 1, triggers DMA_CHANNEL19
bits : 19 - 19 (1 bit)
access : read-write
CH20 : Write 1, triggers DMA_CHANNEL20
bits : 20 - 20 (1 bit)
access : read-write
CH21 : Write 1, triggers DMA_CHANNEL21
bits : 21 - 21 (1 bit)
access : read-write
CH22 : Write 1, triggers DMA_CHANNEL22
bits : 22 - 22 (1 bit)
access : read-write
CH23 : Write 1, triggers DMA_CHANNEL23
bits : 23 - 23 (1 bit)
access : read-write
CH24 : Write 1, triggers DMA_CHANNEL24
bits : 24 - 24 (1 bit)
access : read-write
CH25 : Write 1, triggers DMA_CHANNEL25
bits : 25 - 25 (1 bit)
access : read-write
CH26 : Write 1, triggers DMA_CHANNEL26
bits : 26 - 26 (1 bit)
access : read-write
CH27 : Write 1, triggers DMA_CHANNEL27
bits : 27 - 27 (1 bit)
access : read-write
CH28 : Write 1, triggers DMA_CHANNEL28
bits : 28 - 28 (1 bit)
access : read-write
CH29 : Write 1, triggers DMA_CHANNEL29
bits : 29 - 29 (1 bit)
access : read-write
CH30 : Write 1, triggers DMA_CHANNEL30
bits : 30 - 30 (1 bit)
access : read-write
CH31 : Write 1, triggers DMA_CHANNEL31
bits : 31 - 31 (1 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x574 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x5E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x6C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x7B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x8BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0x9D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
Channel n Source Configuration Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_SRC : Device level DMA source mapping to channel input
bits : 0 - 7 (8 bit)
access : read-write
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