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TIMER_A2

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x30 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTL (TAxCTL)

R (TAxR)

CCR0 (TAxCCR0)

CCR1 (TAxCCR1)

CCTL[%s] (TAxCCTL[3])

CCR2 (TAxCCR2)

CCR3 (TAxCCR3)

CCR4 (TAxCCR4)

CCTL0 (TAxCCTL0)

CCTL[%s] (TAxCCTL[4])

EX0 (TAxEX0)

CCR[%s] (TAxCCR[0])

IV (TAxIV)

CCR[%s] (TAxCCR[1])

CCTL[%s] (TAxCCTL[0])

CCTL1 (TAxCCTL1)

CCR[%s] (TAxCCR[2])

CCTL2 (TAxCCTL2)

CCR[%s] (TAxCCR[3])

CCTL[%s] (TAxCCTL[1])

CCTL3 (TAxCCTL3)

CCR[%s] (TAxCCR[4])

CCTL4 (TAxCCTL4)

CCTL[%s] (TAxCCTL[2])


CTL (TAxCTL)

TimerAx Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAIFG TAIE TACLR MC ID TASSEL

TAIFG : TimerA interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : TAIFG_0

No interrupt pending

1 : TAIFG_1

Interrupt pending

End of enumeration elements list.

TAIE : TimerA interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : TAIE_0

Interrupt disabled

1 : TAIE_1

Interrupt enabled

End of enumeration elements list.

TACLR : TimerA clear
bits : 2 - 2 (1 bit)
access : read-write

MC : Mode control
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : MC_0

Stop mode: Timer is halted

1 : MC_1

Up mode: Timer counts up to TAxCCR0

2 : MC_2

Continuous mode: Timer counts up to 0FFFFh

3 : MC_3

Up/down mode: Timer counts up to TAxCCR0 then down to 0000h

End of enumeration elements list.

ID : Input divider
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0 : ID_0

/1

1 : ID_1

/2

2 : ID_2

/4

3 : ID_3

/8

End of enumeration elements list.

TASSEL : TimerA clock source select
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0 : TASSEL_0

TAxCLK

1 : TASSEL_1

ACLK

2 : TASSEL_2

SMCLK

3 : TASSEL_3

INCLK

End of enumeration elements list.


R (TAxR)

TimerA register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CCR0 (TAxCCR0)

Timer_A Capture/Compare Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR0 CCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCR1 (TAxCCR1)

Timer_A Capture/Compare Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR1 CCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCTL[%s] (TAxCCTL[3])

Timer_A Capture/Compare Control Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL[%s] CCTL[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCR2 (TAxCCR2)

Timer_A Capture/Compare Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR2 CCR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCR3 (TAxCCR3)

Timer_A Capture/Compare Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR3 CCR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCR4 (TAxCCR4)

Timer_A Capture/Compare Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR4 CCR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCTL0 (TAxCCTL0)

Timer_A Capture/Compare Control Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL0 CCTL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCTL[%s] (TAxCCTL[4])

Timer_A Capture/Compare Control Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL[%s] CCTL[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


EX0 (TAxEX0)

TimerAx Expansion 0 Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EX0 EX0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAIDEX

TAIDEX : Input divider expansion
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0 : TAIDEX_0

Divide by 1

1 : TAIDEX_1

Divide by 2

2 : TAIDEX_2

Divide by 3

3 : TAIDEX_3

Divide by 4

4 : TAIDEX_4

Divide by 5

5 : TAIDEX_5

Divide by 6

6 : TAIDEX_6

Divide by 7

7 : TAIDEX_7

Divide by 8

End of enumeration elements list.


CCR[%s] (TAxCCR[0])

Timer_A Capture/Compare Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR[%s] CCR[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


IV (TAxIV)

TimerAx Interrupt Vector Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IV IV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAIV

TAIV : TimerA interrupt vector value
bits : 0 - 15 (16 bit)
access : read-only

Enumeration: TAIV_enum_read ( read )

0 : TAIV_0

No interrupt pending

2 : TAIV_2

Interrupt Source: Capture/compare 1 Interrupt Flag: TAxCCR1 CCIFG Interrupt Priority: Highest

4 : TAIV_4

Interrupt Source: Capture/compare 2 Interrupt Flag: TAxCCR2 CCIFG

6 : TAIV_6

Interrupt Source: Capture/compare 3 Interrupt Flag: TAxCCR3 CCIFG

8 : TAIV_8

Interrupt Source: Capture/compare 4 Interrupt Flag: TAxCCR4 CCIFG

10 : TAIV_10

Interrupt Source: Capture/compare 5 Interrupt Flag: TAxCCR5 CCIFG

12 : TAIV_12

Interrupt Source: Capture/compare 6 Interrupt Flag: TAxCCR6 CCIFG

14 : TAIV_14

Interrupt Source: Timer overflow Interrupt Flag: TAxCTL TAIFG Interrupt Priority: Lowest

End of enumeration elements list.


CCR[%s] (TAxCCR[1])

Timer_A Capture/Compare Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR[%s] CCR[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCTL[%s] (TAxCCTL[0])

Timer_A Capture/Compare Control Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL[%s] CCTL[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCTL1 (TAxCCTL1)

Timer_A Capture/Compare Control Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL1 CCTL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCR[%s] (TAxCCR[2])

Timer_A Capture/Compare Register
address_offset : 0x4E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR[%s] CCR[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCTL2 (TAxCCTL2)

Timer_A Capture/Compare Control Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL2 CCTL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCR[%s] (TAxCCR[3])

Timer_A Capture/Compare Register
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR[%s] CCR[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCTL[%s] (TAxCCTL[1])

Timer_A Capture/Compare Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL[%s] CCTL[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCTL3 (TAxCCTL3)

Timer_A Capture/Compare Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL3 CCTL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCR[%s] (TAxCCR[4])

Timer_A Capture/Compare Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR[%s] CCR[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAxR

TAxR : TimerA register
bits : 0 - 15 (16 bit)
access : read-write


CCTL4 (TAxCCTL4)

Timer_A Capture/Compare Control Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL4 CCTL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.


CCTL[%s] (TAxCCTL[2])

Timer_A Capture/Compare Control Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCTL[%s] CCTL[%s] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCIFG COV OUT CCI CCIE OUTMOD CAP SCCI SCS CCIS CM

CCIFG : Capture/compare interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : CCIFG_0

No interrupt pending

1 : CCIFG_1

Interrupt pending

End of enumeration elements list.

COV : Capture overflow
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : COV_0

No capture overflow occurred

1 : COV_1

Capture overflow occurred

End of enumeration elements list.

OUT : Output
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : OUT_0

Output low

1 : OUT_1

Output high

End of enumeration elements list.

CCI : Capture/compare input
bits : 3 - 3 (1 bit)
access : read-only

CCIE : Capture/compare interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : CCIE_0

Interrupt disabled

1 : CCIE_1

Interrupt enabled

End of enumeration elements list.

OUTMOD : Output mode
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : OUTMOD_0

OUT bit value

1 : OUTMOD_1

Set

2 : OUTMOD_2

Toggle/reset

3 : OUTMOD_3

Set/reset

4 : OUTMOD_4

Toggle

5 : OUTMOD_5

Reset

6 : OUTMOD_6

Toggle/set

7 : OUTMOD_7

Reset/set

End of enumeration elements list.

CAP : Capture mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : CAP_0

Compare mode

1 : CAP_1

Capture mode

End of enumeration elements list.

SCCI : Synchronized capture/compare input
bits : 10 - 10 (1 bit)
access : read-write

SCS : Synchronize capture source
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : SCS_0

Asynchronous capture

1 : SCS_1

Synchronous capture

End of enumeration elements list.

CCIS : Capture/compare input select
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : CCIS_0

CCIxA

1 : CCIS_1

CCIxB

2 : CCIS_2

GND

3 : CCIS_3

VCC

End of enumeration elements list.

CM : Capture mode
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : CM_0

No capture

1 : CM_1

Capture on rising edge

2 : CM_2

Capture on falling edge

3 : CM_3

Capture on both rising and falling edges

End of enumeration elements list.



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