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EUSCI_A3

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTLW0 (UCAxCTLW0)

ABCTL (UCAxABCTL)

IRCTL (UCAxIRCTL)

IE (UCAxIE)

IFG (UCAxIFG)

IV (UCAxIV)

CTLW1 (UCAxCTLW1)

BRW (UCAxBRW)

MCTLW (UCAxMCTLW)

STATW (UCAxSTATW)

RXBUF (UCAxRXBUF)

TXBUF (UCAxTXBUF)


CTLW0 (UCAxCTLW0)

eUSCI_Ax Control Word Register 0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLW0 CTLW0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCSWRST UCTXBRK UCTXADDR UCDORM UCBRKIE UCRXEIE UCSSEL UCSYNC UCMODE UCSPB UC7BIT UCMSB UCPAR UCPEN

UCSWRST : Software reset enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UCSWRST_0

Disabled. eUSCI_A reset released for operation

1 : UCSWRST_1

Enabled. eUSCI_A logic held in reset state

End of enumeration elements list.

UCTXBRK : Transmit break
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : UCTXBRK_0

Next frame transmitted is not a break

1 : UCTXBRK_1

Next frame transmitted is a break or a break/synch

End of enumeration elements list.

UCTXADDR : Transmit address
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : UCTXADDR_0

Next frame transmitted is data

1 : UCTXADDR_1

Next frame transmitted is an address

End of enumeration elements list.

UCDORM : Dormant
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : UCDORM_0

Not dormant. All received characters set UCRXIFG.

1 : UCDORM_1

Dormant. Only characters that are preceded by an idle-line or with address bit set UCRXIFG. In UART mode with automatic baud-rate detection, only the combination of a break and synch field sets UCRXIFG.

End of enumeration elements list.

UCBRKIE : Receive break character interrupt enable
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : UCBRKIE_0

Received break characters do not set UCRXIFG

1 : UCBRKIE_1

Received break characters set UCRXIFG

End of enumeration elements list.

UCRXEIE : Receive erroneous-character interrupt enable
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : UCRXEIE_0

Erroneous characters rejected and UCRXIFG is not set

1 : UCRXEIE_1

Erroneous characters received set UCRXIFG

End of enumeration elements list.

UCSSEL : eUSCI_A clock source select
bits : 6 - 7 (2 bit)
access : read-write

Enumeration:

0 : UCSSEL_0

UCLK

1 : UCSSEL_1

ACLK

2 : UCSSEL_2

SMCLK

End of enumeration elements list.

UCSYNC : Synchronous mode enable
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : UCSYNC_0

Asynchronous mode

1 : UCSYNC_1

Synchronous mode

End of enumeration elements list.

UCMODE : eUSCI_A mode
bits : 9 - 10 (2 bit)
access : read-write

Enumeration:

0 : UCMODE_0

UART mode

1 : UCMODE_1

Idle-line multiprocessor mode

2 : UCMODE_2

Address-bit multiprocessor mode

3 : UCMODE_3

UART mode with automatic baud-rate detection

End of enumeration elements list.

UCSPB : Stop bit select
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

0 : UCSPB_0

One stop bit

1 : UCSPB_1

Two stop bits

End of enumeration elements list.

UC7BIT : Character length
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : UC7BIT_0

8-bit data

1 : UC7BIT_1

7-bit data

End of enumeration elements list.

UCMSB : MSB first select
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

0 : UCMSB_0

LSB first

1 : UCMSB_1

MSB first

End of enumeration elements list.

UCPAR : Parity select
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

0 : UCPAR_0

Odd parity

1 : UCPAR_1

Even parity

End of enumeration elements list.

UCPEN : Parity enable
bits : 15 - 15 (1 bit)
access : read-write

Enumeration:

0 : UCPEN_0

Parity disabled

1 : UCPEN_1

Parity enabled. Parity bit is generated (UCAxTXD) and expected (UCAxRXD). In address-bit multiprocessor mode, the address bit is included in the parity calculation.

End of enumeration elements list.


ABCTL (UCAxABCTL)

eUSCI_Ax Auto Baud Rate Control Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ABCTL ABCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCABDEN UCBTOE UCSTOE UCDELIM

UCABDEN : Automatic baud-rate detect enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UCABDEN_0

Baud-rate detection disabled. Length of break and synch field is not measured.

1 : UCABDEN_1

Baud-rate detection enabled. Length of break and synch field is measured and baud-rate settings are changed accordingly.

End of enumeration elements list.

UCBTOE : Break time out error
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : UCBTOE_0

No error

1 : UCBTOE_1

Length of break field exceeded 22 bit times

End of enumeration elements list.

UCSTOE : Synch field time out error
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : UCSTOE_0

No error

1 : UCSTOE_1

Length of synch field exceeded measurable time

End of enumeration elements list.

UCDELIM : Break/synch delimiter length
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : UCDELIM_0

1 bit time

1 : UCDELIM_1

2 bit times

2 : UCDELIM_2

3 bit times

3 : UCDELIM_3

4 bit times

End of enumeration elements list.


IRCTL (UCAxIRCTL)

eUSCI_Ax IrDA Control Word Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRCTL IRCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCIREN UCIRTXCLK UCIRTXPL UCIRRXFE UCIRRXPL UCIRRXFL

UCIREN : IrDA encoder/decoder enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UCIREN_0

IrDA encoder/decoder disabled

1 : UCIREN_1

IrDA encoder/decoder enabled

End of enumeration elements list.

UCIRTXCLK : IrDA transmit pulse clock select
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : UCIRTXCLK_0

BRCLK

1 : UCIRTXCLK_1

BITCLK16 when UCOS16 = 1. Otherwise, BRCLK.

End of enumeration elements list.

UCIRTXPL : Transmit pulse length
bits : 2 - 7 (6 bit)
access : read-write

UCIRRXFE : IrDA receive filter enabled
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : UCIRRXFE_0

Receive filter disabled

1 : UCIRRXFE_1

Receive filter enabled

End of enumeration elements list.

UCIRRXPL : IrDA receive input UCAxRXD polarity
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

0 : UCIRRXPL_0

IrDA transceiver delivers a high pulse when a light pulse is seen

1 : UCIRRXPL_1

IrDA transceiver delivers a low pulse when a light pulse is seen

End of enumeration elements list.

UCIRRXFL : Receive filter length
bits : 10 - 13 (4 bit)
access : read-write


IE (UCAxIE)

eUSCI_Ax Interrupt Enable Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCRXIE UCTXIE UCSTTIE UCTXCPTIE

UCRXIE : Receive interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UCRXIE_0

Interrupt disabled

1 : UCRXIE_1

Interrupt enabled

End of enumeration elements list.

UCTXIE : Transmit interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : UCTXIE_0

Interrupt disabled

1 : UCTXIE_1

Interrupt enabled

End of enumeration elements list.

UCSTTIE : Start bit interrupt enable
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : UCSTTIE_0

Interrupt disabled

1 : UCSTTIE_1

Interrupt enabled

End of enumeration elements list.

UCTXCPTIE : Transmit complete interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : UCTXCPTIE_0

Interrupt disabled

1 : UCTXCPTIE_1

Interrupt enabled

End of enumeration elements list.


IFG (UCAxIFG)

eUSCI_Ax Interrupt Flag Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IFG IFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCRXIFG UCTXIFG UCSTTIFG UCTXCPTIFG

UCRXIFG : Receive interrupt flag
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UCRXIFG_0

No interrupt pending

1 : UCRXIFG_1

Interrupt pending

End of enumeration elements list.

UCTXIFG : Transmit interrupt flag
bits : 1 - 1 (1 bit)
access : read-write

Enumeration:

0 : UCTXIFG_0

No interrupt pending

1 : UCTXIFG_1

Interrupt pending

End of enumeration elements list.

UCSTTIFG : Start bit interrupt flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : UCSTTIFG_0

No interrupt pending

1 : UCSTTIFG_1

Interrupt pending

End of enumeration elements list.

UCTXCPTIFG : Transmit ready interrupt enable
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : UCTXCPTIFG_0

No interrupt pending

1 : UCTXCPTIFG_1

Interrupt pending

End of enumeration elements list.


IV (UCAxIV)

eUSCI_Ax Interrupt Vector Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IV IV read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCIV

UCIV : eUSCI_A interrupt vector value
bits : 0 - 15 (16 bit)
access : read-only

Enumeration: UCIV_enum_read ( read )

0 : UCIV_0

No interrupt pending

2 : UCIV_2

Interrupt Source: Receive buffer full Interrupt Flag: UCRXIFG Interrupt Priority: Highest

4 : UCIV_4

Interrupt Source: Transmit buffer empty Interrupt Flag: UCTXIFG

6 : UCIV_6

Interrupt Source: Start bit received Interrupt Flag: UCSTTIFG

8 : UCIV_8

Interrupt Source: Transmit complete Interrupt Flag: UCTXCPTIFG Interrupt Priority: Lowest

End of enumeration elements list.


CTLW1 (UCAxCTLW1)

eUSCI_Ax Control Word Register 1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLW1 CTLW1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCGLIT

UCGLIT : Deglitch time
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : UCGLIT_0

Approximately 2 ns (equivalent of 1 delay element)

1 : UCGLIT_1

Approximately 50 ns

2 : UCGLIT_2

Approximately 100 ns

3 : UCGLIT_3

Approximately 200 ns

End of enumeration elements list.


BRW (UCAxBRW)

eUSCI_Ax Baud Rate Control Word Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BRW BRW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCBR

UCBR : Clock prescaler setting of the Baud rate generator
bits : 0 - 15 (16 bit)
access : read-write


MCTLW (UCAxMCTLW)

eUSCI_Ax Modulation Control Word Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCTLW MCTLW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCOS16 UCBRF UCBRS

UCOS16 : Oversampling mode enabled
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : UCOS16_0

Disabled

1 : UCOS16_1

Enabled

End of enumeration elements list.

UCBRF : First modulation stage select
bits : 4 - 7 (4 bit)
access : read-write

UCBRS : Second modulation stage select
bits : 8 - 15 (8 bit)
access : read-write


STATW (UCAxSTATW)

eUSCI_Ax Status Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATW STATW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCBUSY UCADDR_UCIDLE UCRXERR UCBRK UCPE UCOE UCFE UCLISTEN

UCBUSY : eUSCI_A busy
bits : 0 - 0 (1 bit)
access : read-only

Enumeration: UCBUSY_enum_read ( read )

0 : UCBUSY_0

eUSCI_A inactive

1 : UCBUSY_1

eUSCI_A transmitting or receiving

End of enumeration elements list.

UCADDR_UCIDLE : Address received / Idle line detected
bits : 1 - 1 (1 bit)
access : read-write

UCRXERR : Receive error flag
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

0 : UCRXERR_0

No receive errors detected

1 : UCRXERR_1

Receive error detected

End of enumeration elements list.

UCBRK : Break detect flag
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0 : UCBRK_0

No break condition

1 : UCBRK_1

Break condition occurred

End of enumeration elements list.

UCPE : Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0 : UCPE_0

No error

1 : UCPE_1

Character received with parity error

End of enumeration elements list.

UCOE : Overrun error flag
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

0 : UCOE_0

No error

1 : UCOE_1

Overrun error occurred

End of enumeration elements list.

UCFE : Framing error flag
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0 : UCFE_0

No error

1 : UCFE_1

Character received with low stop bit

End of enumeration elements list.

UCLISTEN : Listen enable
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : UCLISTEN_0

Disabled

1 : UCLISTEN_1

Enabled. UCAxTXD is internally fed back to the receiver

End of enumeration elements list.


RXBUF (UCAxRXBUF)

eUSCI_Ax Receive Buffer Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RXBUF RXBUF read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCRXBUF

UCRXBUF : Receive data buffer
bits : 0 - 7 (8 bit)
access : read-only


TXBUF (UCAxTXBUF)

eUSCI_Ax Transmit Buffer Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBUF TXBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UCTXBUF

UCTXBUF : Transmit data buffer
bits : 0 - 7 (8 bit)
access : read-write



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