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WATCHDOG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WATCHDOG0LOAD

LOAD

WATCHDOG0RIS

RIS

WATCHDOG0MIS

MIS

WATCHDOG0VALUE

VALUE

WATCHDOG0TEST

TEST

WATCHDOG0CTL

CTL

WATCHDOG0ICR

ICR

WATCHDOG0LOCK

LOCK


WATCHDOG0LOAD

Watchdog Load
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0LOAD WATCHDOG0LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_LOAD

WDT_LOAD : Watchdog Load Value
bits : 0 - 31 (32 bit)


LOAD

Watchdog Load
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOAD LOAD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_LOAD

WDT_LOAD : Watchdog Load Value
bits : 0 - 31 (32 bit)


WATCHDOG0RIS

Watchdog Raw Interrupt Status
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0RIS WATCHDOG0RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_RIS_WDTRIS

WDT_RIS_WDTRIS : Watchdog Raw Interrupt Status
bits : 0 - 0 (1 bit)


RIS

Watchdog Raw Interrupt Status
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_RIS_WDTRIS

WDT_RIS_WDTRIS : Watchdog Raw Interrupt Status
bits : 0 - 0 (1 bit)


WATCHDOG0MIS

Watchdog Masked Interrupt Status
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0MIS WATCHDOG0MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_MIS_WDTMIS

WDT_MIS_WDTMIS : Watchdog Masked Interrupt Status
bits : 0 - 0 (1 bit)


MIS

Watchdog Masked Interrupt Status
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_MIS_WDTMIS

WDT_MIS_WDTMIS : Watchdog Masked Interrupt Status
bits : 0 - 0 (1 bit)


WATCHDOG0VALUE

Watchdog Value
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0VALUE WATCHDOG0VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_VALUE

WDT_VALUE : Watchdog Value
bits : 0 - 31 (32 bit)


VALUE

Watchdog Value
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VALUE VALUE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_VALUE

WDT_VALUE : Watchdog Value
bits : 0 - 31 (32 bit)


WATCHDOG0TEST

Watchdog Test
address_offset : 0x418 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0TEST WATCHDOG0TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_TEST_STALL

WDT_TEST_STALL : Watchdog Stall Enable
bits : 8 - 16 (9 bit)


TEST

Watchdog Test
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST TEST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_TEST_STALL

WDT_TEST_STALL : Watchdog Stall Enable
bits : 8 - 16 (9 bit)


WATCHDOG0CTL

Watchdog Control
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0CTL WATCHDOG0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_CTL_INTEN WDT_CTL_RESEN WDT_CTL_INTTYPE WDT_CTL_WRC

WDT_CTL_INTEN : Watchdog Interrupt Enable
bits : 0 - 0 (1 bit)

WDT_CTL_RESEN : Watchdog Reset Enable
bits : 1 - 2 (2 bit)

WDT_CTL_INTTYPE : Watchdog Interrupt Type
bits : 2 - 4 (3 bit)

WDT_CTL_WRC : Write Complete
bits : 31 - 62 (32 bit)


CTL

Watchdog Control
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_CTL_INTEN WDT_CTL_RESEN WDT_CTL_INTTYPE WDT_CTL_WRC

WDT_CTL_INTEN : Watchdog Interrupt Enable
bits : 0 - 0 (1 bit)

WDT_CTL_RESEN : Watchdog Reset Enable
bits : 1 - 2 (2 bit)

WDT_CTL_INTTYPE : Watchdog Interrupt Type
bits : 2 - 4 (3 bit)

WDT_CTL_WRC : Write Complete
bits : 31 - 62 (32 bit)


WATCHDOG0ICR

Watchdog Interrupt Clear
address_offset : 0xC Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0ICR WATCHDOG0ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_ICR

WDT_ICR : Watchdog Interrupt Clear
bits : 0 - 31 (32 bit)
access : write-only


ICR

Watchdog Interrupt Clear
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_ICR

WDT_ICR : Watchdog Interrupt Clear
bits : 0 - 31 (32 bit)
access : write-only


WATCHDOG0LOCK

Watchdog Lock
address_offset : 0xC00 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WATCHDOG0LOCK WATCHDOG0LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_LOCK

WDT_LOCK : Watchdog Lock
bits : 0 - 31 (32 bit)

Enumeration:

0x0 : WDT_LOCK_UNLOCKED

Unlocked

0x1 : WDT_LOCK_LOCKED

Locked

0x1acce551 : WDT_LOCK_UNLOCK

Unlocks the watchdog timer

End of enumeration elements list.


LOCK

Watchdog Lock
address_offset : 0xC00 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDT_LOCK

WDT_LOCK : Watchdog Lock
bits : 0 - 31 (32 bit)

Enumeration:

0x0 : WDT_LOCK_UNLOCKED

Unlocked

0x1 : WDT_LOCK_LOCKED

Locked

0x1acce551 : WDT_LOCK_UNLOCK

Unlocks the watchdog timer

End of enumeration elements list.



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