Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
USB Device Functional Address
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FADDR : Function Address
bits : 0 - 6 (7 bit)
USB Device Functional Address
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FADDR : Function Address
bits : 0 - 6 (7 bit)
USB Power
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_POWER_PWRDNPHY : Power Down PHY
bits : 0 - 0 (1 bit)
USB_POWER_SUSPEND : SUSPEND Mode
bits : 1 - 2 (2 bit)
USB_POWER_RESUME : RESUME Signaling
bits : 2 - 4 (3 bit)
USB_POWER_RESET : RESET Signaling
bits : 3 - 6 (4 bit)
USB_POWER_SOFTCONN : Soft Connect/Disconnect
bits : 6 - 12 (7 bit)
USB_POWER_ISOUP : Isochronous Update
bits : 7 - 14 (8 bit)
USB Power
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_POWER_PWRDNPHY : Power Down PHY
bits : 0 - 0 (1 bit)
USB_POWER_SUSPEND : SUSPEND Mode
bits : 1 - 2 (2 bit)
USB_POWER_RESUME : RESUME Signaling
bits : 2 - 4 (3 bit)
USB_POWER_RESET : RESET Signaling
bits : 3 - 6 (4 bit)
USB_POWER_SOFTCONN : Soft Connect/Disconnect
bits : 6 - 12 (7 bit)
USB_POWER_ISOUP : Isochronous Update
bits : 7 - 14 (8 bit)
USB Control and Status Endpoint 0 Low
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USB_CSRL0_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
access : write-only
USB_CSRL0_TXRDY : Transmit Packet Ready
bits : 1 - 2 (2 bit)
access : write-only
USB_CSRL0_STALLED : Endpoint Stalled
bits : 2 - 4 (3 bit)
access : write-only
USB_CSRL0_DATAEND : Data End
bits : 3 - 6 (4 bit)
access : write-only
USB_CSRL0_SETEND : Setup End
bits : 4 - 8 (5 bit)
access : write-only
USB_CSRL0_STALL : Send Stall
bits : 5 - 10 (6 bit)
access : write-only
USB_CSRL0_RXRDYC : RXRDY Clear
bits : 6 - 12 (7 bit)
access : write-only
USB_CSRL0_SETENDC : Setup End Clear
bits : 7 - 14 (8 bit)
access : write-only
USB Control and Status Endpoint 0 Low
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USB_CSRL0_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
access : write-only
USB_CSRL0_TXRDY : Transmit Packet Ready
bits : 1 - 2 (2 bit)
access : write-only
USB_CSRL0_STALLED : Endpoint Stalled
bits : 2 - 4 (3 bit)
access : write-only
USB_CSRL0_DATAEND : Data End
bits : 3 - 6 (4 bit)
access : write-only
USB_CSRL0_SETEND : Setup End
bits : 4 - 8 (5 bit)
access : write-only
USB_CSRL0_STALL : Send Stall
bits : 5 - 10 (6 bit)
access : write-only
USB_CSRL0_RXRDYC : RXRDY Clear
bits : 6 - 12 (7 bit)
access : write-only
USB_CSRL0_SETENDC : Setup End Clear
bits : 7 - 14 (8 bit)
access : write-only
USB Control and Status Endpoint 0 High
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USB_CSRH0_FLUSH : Flush FIFO
bits : 0 - 0 (1 bit)
access : write-only
USB Control and Status Endpoint 0 High
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USB_CSRH0_FLUSH : Flush FIFO
bits : 0 - 0 (1 bit)
access : write-only
USB Receive Byte Count Endpoint 0
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_COUNT0_COUNT : FIFO Count
bits : 0 - 6 (7 bit)
USB Receive Byte Count Endpoint 0
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_COUNT0_COUNT : FIFO Count
bits : 0 - 6 (7 bit)
USB Maximum Transmit Data Endpoint 1
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 1
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 1 Low
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL1_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL1_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL1_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL1_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL1_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 1 Low
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL1_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL1_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL1_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL1_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL1_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL1_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL1_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 1 High
address_offset : 0x113 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH1_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH1_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH1_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH1_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH1_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH1_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 1 High
address_offset : 0x113 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH1_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH1_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH1_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH1_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH1_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH1_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 1
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 1
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 1 Low
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL1_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL1_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL1_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL1_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL1_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL1_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL1_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL1_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 1 Low
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL1_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL1_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL1_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL1_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL1_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL1_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL1_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL1_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 1 High
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH1_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH1_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH1_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH1_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 1 High
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH1_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH1_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH1_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH1_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH1_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH1_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 1
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT1_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 1
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT1_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Maximum Transmit Data Endpoint 2
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 2
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 2 Low
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL2_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL2_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL2_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL2_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL2_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 2 Low
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL2_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL2_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL2_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL2_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL2_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL2_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL2_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 2 High
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH2_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH2_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH2_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH2_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH2_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH2_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 2 High
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH2_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH2_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH2_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH2_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH2_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH2_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 2
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 2
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 2 Low
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL2_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL2_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL2_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL2_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL2_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL2_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL2_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL2_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 2 Low
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL2_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL2_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL2_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL2_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL2_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL2_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL2_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL2_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 2 High
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH2_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH2_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH2_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH2_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 2 High
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH2_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH2_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH2_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH2_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH2_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH2_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 2
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT2_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 2
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT2_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Maximum Transmit Data Endpoint 3
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 3
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 3 Low
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL3_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL3_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL3_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL3_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL3_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 3 Low
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL3_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL3_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL3_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL3_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL3_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL3_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL3_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 3 High
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH3_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH3_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH3_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH3_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH3_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH3_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 3 High
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH3_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH3_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH3_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH3_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH3_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH3_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 3
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 3
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 3 Low
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL3_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL3_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL3_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL3_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL3_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL3_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL3_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL3_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 3 Low
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL3_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL3_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL3_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL3_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL3_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL3_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL3_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL3_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 3 High
address_offset : 0x137 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH3_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH3_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH3_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH3_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 3 High
address_offset : 0x137 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH3_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH3_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH3_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH3_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH3_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH3_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 3
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT3_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 3
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT3_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Maximum Transmit Data Endpoint 4
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 4
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 4 Low
address_offset : 0x142 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL4_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL4_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL4_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL4_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL4_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 4 Low
address_offset : 0x142 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL4_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL4_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL4_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL4_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL4_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL4_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL4_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 4 High
address_offset : 0x143 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH4_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH4_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH4_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH4_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH4_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH4_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 4 High
address_offset : 0x143 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH4_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH4_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH4_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH4_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH4_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH4_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 4
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 4
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 4 Low
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL4_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL4_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL4_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL4_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL4_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL4_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL4_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL4_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 4 Low
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL4_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL4_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL4_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL4_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL4_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL4_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL4_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL4_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 4 High
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH4_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH4_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH4_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH4_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 4 High
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH4_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH4_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH4_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH4_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH4_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH4_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 4
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT4_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 4
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT4_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Maximum Transmit Data Endpoint 5
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 5
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 5 Low
address_offset : 0x152 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL5_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL5_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL5_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL5_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL5_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 5 Low
address_offset : 0x152 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL5_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL5_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL5_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL5_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL5_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL5_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL5_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 5 High
address_offset : 0x153 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH5_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH5_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH5_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH5_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH5_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH5_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 5 High
address_offset : 0x153 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH5_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH5_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH5_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH5_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH5_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH5_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 5
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 5
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 5 Low
address_offset : 0x156 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL5_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL5_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL5_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL5_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL5_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL5_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL5_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL5_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 5 Low
address_offset : 0x156 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL5_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL5_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL5_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL5_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL5_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL5_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL5_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL5_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 5 High
address_offset : 0x157 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH5_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH5_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH5_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH5_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 5 High
address_offset : 0x157 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH5_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH5_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH5_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH5_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH5_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH5_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 5
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT5_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 5
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT5_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Maximum Transmit Data Endpoint 6
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 6
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 6 Low
address_offset : 0x162 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL6_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL6_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL6_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL6_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL6_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 6 Low
address_offset : 0x162 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL6_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL6_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL6_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL6_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL6_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL6_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL6_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 6 High
address_offset : 0x163 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH6_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH6_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH6_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH6_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH6_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH6_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 6 High
address_offset : 0x163 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH6_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH6_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH6_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH6_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH6_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH6_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 6
address_offset : 0x164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 6
address_offset : 0x164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 6 Low
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL6_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL6_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL6_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL6_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL6_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL6_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL6_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL6_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 6 Low
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL6_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL6_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL6_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL6_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL6_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL6_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL6_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL6_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 6 High
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH6_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH6_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH6_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH6_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 6 High
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH6_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH6_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH6_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH6_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH6_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH6_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 6
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT6_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 6
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT6_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Maximum Transmit Data Endpoint 7
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Transmit Data Endpoint 7
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Transmit Control and Status Endpoint 7 Low
address_offset : 0x172 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL7_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL7_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL7_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL7_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL7_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 7 Low
address_offset : 0x172 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRL7_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)
USB_TXCSRL7_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)
USB_TXCSRL7_UNDRN : Underrun
bits : 2 - 4 (3 bit)
USB_TXCSRL7_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)
USB_TXCSRL7_STALL : Send STALL
bits : 4 - 8 (5 bit)
USB_TXCSRL7_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)
USB_TXCSRL7_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)
USB Transmit Control and Status Endpoint 7 High
address_offset : 0x173 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH7_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH7_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH7_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH7_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH7_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH7_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Transmit Control and Status Endpoint 7 High
address_offset : 0x173 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXCSRH7_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)
USB_TXCSRH7_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)
USB_TXCSRH7_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)
USB_TXCSRH7_MODE : Mode
bits : 5 - 10 (6 bit)
USB_TXCSRH7_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_TXCSRH7_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)
USB Maximum Receive Data Endpoint 7
address_offset : 0x174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Maximum Receive Data Endpoint 7
address_offset : 0x174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)
USB Receive Control and Status Endpoint 7 Low
address_offset : 0x176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL7_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL7_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL7_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL7_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL7_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL7_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL7_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL7_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 7 Low
address_offset : 0x176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRL7_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
USB_RXCSRL7_FULL : FIFO Full
bits : 1 - 2 (2 bit)
USB_RXCSRL7_OVER : Overrun
bits : 2 - 4 (3 bit)
USB_RXCSRL7_DATAERR : Data Error
bits : 3 - 6 (4 bit)
USB_RXCSRL7_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)
USB_RXCSRL7_STALL : Send STALL
bits : 5 - 10 (6 bit)
USB_RXCSRL7_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)
USB_RXCSRL7_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 7 High
address_offset : 0x177 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH7_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH7_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH7_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH7_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Control and Status Endpoint 7 High
address_offset : 0x177 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCSRH7_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)
USB_RXCSRH7_PIDERR : PID Error
bits : 4 - 8 (5 bit)
USB_RXCSRH7_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)
USB_RXCSRH7_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)
USB_RXCSRH7_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)
USB_RXCSRH7_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)
USB Receive Byte Count Endpoint 7
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT7_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Receive Byte Count Endpoint 7
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXCOUNT7_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)
USB Transmit Interrupt Status
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXIS_EP0 : TX and RX Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)
USB_TXIS_EP1 : TX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)
USB_TXIS_EP2 : TX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)
USB_TXIS_EP3 : TX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)
USB_TXIS_EP4 : TX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)
USB_TXIS_EP5 : TX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)
USB_TXIS_EP6 : TX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)
USB_TXIS_EP7 : TX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)
USB Transmit Interrupt Status
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXIS_EP0 : TX and RX Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)
USB_TXIS_EP1 : TX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)
USB_TXIS_EP2 : TX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)
USB_TXIS_EP3 : TX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)
USB_TXIS_EP4 : TX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)
USB_TXIS_EP5 : TX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)
USB_TXIS_EP6 : TX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)
USB_TXIS_EP7 : TX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)
USB FIFO Endpoint 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO0_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO0_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO1_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO1_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO2_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 2
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO2_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO3_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 3
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO3_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO4_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 4
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO4_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 5
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO5_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 5
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO5_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB Receive Double Packet Buffer Disable
address_offset : 0x340 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXDPKTBUFDIS_EP1 : EP1 RX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)
USB_RXDPKTBUFDIS_EP2 : EP2 RX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)
USB_RXDPKTBUFDIS_EP3 : EP3 RX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)
USB_RXDPKTBUFDIS_EP4 : EP4 RX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)
USB_RXDPKTBUFDIS_EP5 : EP5 RX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)
USB_RXDPKTBUFDIS_EP6 : EP6 RX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)
USB_RXDPKTBUFDIS_EP7 : EP7 RX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)
USB Receive Double Packet Buffer Disable
address_offset : 0x340 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXDPKTBUFDIS_EP1 : EP1 RX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)
USB_RXDPKTBUFDIS_EP2 : EP2 RX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)
USB_RXDPKTBUFDIS_EP3 : EP3 RX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)
USB_RXDPKTBUFDIS_EP4 : EP4 RX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)
USB_RXDPKTBUFDIS_EP5 : EP5 RX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)
USB_RXDPKTBUFDIS_EP6 : EP6 RX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)
USB_RXDPKTBUFDIS_EP7 : EP7 RX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)
USB Transmit Double Packet Buffer Disable
address_offset : 0x342 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXDPKTBUFDIS_EP1 : EP1 TX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)
USB_TXDPKTBUFDIS_EP2 : EP2 TX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)
USB_TXDPKTBUFDIS_EP3 : EP3 TX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)
USB_TXDPKTBUFDIS_EP4 : EP4 TX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)
USB_TXDPKTBUFDIS_EP5 : EP5 TX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)
USB_TXDPKTBUFDIS_EP6 : EP6 TX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)
USB_TXDPKTBUFDIS_EP7 : EP7 TX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)
USB Transmit Double Packet Buffer Disable
address_offset : 0x342 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXDPKTBUFDIS_EP1 : EP1 TX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)
USB_TXDPKTBUFDIS_EP2 : EP2 TX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)
USB_TXDPKTBUFDIS_EP3 : EP3 TX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)
USB_TXDPKTBUFDIS_EP4 : EP4 TX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)
USB_TXDPKTBUFDIS_EP5 : EP5 TX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)
USB_TXDPKTBUFDIS_EP6 : EP6 TX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)
USB_TXDPKTBUFDIS_EP7 : EP7 TX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)
USB FIFO Endpoint 6
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO6_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 6
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO6_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 7
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO7_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB FIFO Endpoint 7
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FIFO7_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)
USB Receive Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXIS_EP1 : RX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)
USB_RXIS_EP2 : RX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)
USB_RXIS_EP3 : RX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)
USB_RXIS_EP4 : RX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)
USB_RXIS_EP5 : RX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)
USB_RXIS_EP6 : RX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)
USB_RXIS_EP7 : RX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)
USB Receive Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXIS_EP1 : RX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)
USB_RXIS_EP2 : RX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)
USB_RXIS_EP3 : RX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)
USB_RXIS_EP4 : RX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)
USB_RXIS_EP5 : RX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)
USB_RXIS_EP6 : RX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)
USB_RXIS_EP7 : RX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)
USB Device RESUME Raw Interrupt Status
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_DRRIS_RESUME : RESUME Interrupt Status
bits : 0 - 0 (1 bit)
USB Device RESUME Raw Interrupt Status
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_DRRIS_RESUME : RESUME Interrupt Status
bits : 0 - 0 (1 bit)
USB Device RESUME Interrupt Mask
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_DRIM_RESUME : RESUME Interrupt Mask
bits : 0 - 0 (1 bit)
USB Device RESUME Interrupt Mask
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_DRIM_RESUME : RESUME Interrupt Mask
bits : 0 - 0 (1 bit)
USB Device RESUME Interrupt Status and Clear
address_offset : 0x418 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USB_DRISC_RESUME : RESUME Interrupt Status and Clear
bits : 0 - 0 (1 bit)
access : write-only
USB Device RESUME Interrupt Status and Clear
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
USB_DRISC_RESUME : RESUME Interrupt Status and Clear
bits : 0 - 0 (1 bit)
access : write-only
USB DMA Select
address_offset : 0x450 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_DMASEL_DMAARX : DMA A RX Select
bits : 0 - 3 (4 bit)
USB_DMASEL_DMAATX : DMA A TX Select
bits : 4 - 11 (8 bit)
USB_DMASEL_DMABRX : DMA B RX Select
bits : 8 - 19 (12 bit)
USB_DMASEL_DMABTX : DMA B TX Select
bits : 12 - 27 (16 bit)
USB_DMASEL_DMACRX : DMA C RX Select
bits : 16 - 35 (20 bit)
USB_DMASEL_DMACTX : DMA C TX Select
bits : 20 - 43 (24 bit)
USB DMA Select
address_offset : 0x450 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_DMASEL_DMAARX : DMA A RX Select
bits : 0 - 3 (4 bit)
USB_DMASEL_DMAATX : DMA A TX Select
bits : 4 - 11 (8 bit)
USB_DMASEL_DMABRX : DMA B RX Select
bits : 8 - 19 (12 bit)
USB_DMASEL_DMABTX : DMA B TX Select
bits : 12 - 27 (16 bit)
USB_DMASEL_DMACRX : DMA C RX Select
bits : 16 - 35 (20 bit)
USB_DMASEL_DMACTX : DMA C TX Select
bits : 20 - 43 (24 bit)
USB Transmit Interrupt Enable
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXIE_EP0 : TX and RX Endpoint 0 Interrupt Enable
bits : 0 - 0 (1 bit)
USB_TXIE_EP1 : TX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)
USB_TXIE_EP2 : TX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)
USB_TXIE_EP3 : TX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)
USB_TXIE_EP4 : TX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)
USB_TXIE_EP5 : TX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)
USB_TXIE_EP6 : TX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)
USB_TXIE_EP7 : TX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)
USB Transmit Interrupt Enable
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXIE_EP0 : TX and RX Endpoint 0 Interrupt Enable
bits : 0 - 0 (1 bit)
USB_TXIE_EP1 : TX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)
USB_TXIE_EP2 : TX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)
USB_TXIE_EP3 : TX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)
USB_TXIE_EP4 : TX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)
USB_TXIE_EP5 : TX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)
USB_TXIE_EP6 : TX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)
USB_TXIE_EP7 : TX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)
USB Transmit Dynamic FIFO Sizing
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : USB_TXFIFOSZ_SIZE_8
8
0x1 : USB_TXFIFOSZ_SIZE_16
16
0x2 : USB_TXFIFOSZ_SIZE_32
32
0x3 : USB_TXFIFOSZ_SIZE_64
64
0x4 : USB_TXFIFOSZ_SIZE_128
128
0x5 : USB_TXFIFOSZ_SIZE_256
256
0x6 : USB_TXFIFOSZ_SIZE_512
512
0x7 : USB_TXFIFOSZ_SIZE_1024
1024
0x8 : USB_TXFIFOSZ_SIZE_2048
2048
End of enumeration elements list.
USB_TXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)
USB Transmit Dynamic FIFO Sizing
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : USB_TXFIFOSZ_SIZE_8
8
0x1 : USB_TXFIFOSZ_SIZE_16
16
0x2 : USB_TXFIFOSZ_SIZE_32
32
0x3 : USB_TXFIFOSZ_SIZE_64
64
0x4 : USB_TXFIFOSZ_SIZE_128
128
0x5 : USB_TXFIFOSZ_SIZE_256
256
0x6 : USB_TXFIFOSZ_SIZE_512
512
0x7 : USB_TXFIFOSZ_SIZE_1024
1024
0x8 : USB_TXFIFOSZ_SIZE_2048
2048
End of enumeration elements list.
USB_TXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)
USB Receive Dynamic FIFO Sizing
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : USB_RXFIFOSZ_SIZE_8
8
0x1 : USB_RXFIFOSZ_SIZE_16
16
0x2 : USB_RXFIFOSZ_SIZE_32
32
0x3 : USB_RXFIFOSZ_SIZE_64
64
0x4 : USB_RXFIFOSZ_SIZE_128
128
0x5 : USB_RXFIFOSZ_SIZE_256
256
0x6 : USB_RXFIFOSZ_SIZE_512
512
0x7 : USB_RXFIFOSZ_SIZE_1024
1024
0x8 : USB_RXFIFOSZ_SIZE_2048
2048
End of enumeration elements list.
USB_RXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)
USB Receive Dynamic FIFO Sizing
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : USB_RXFIFOSZ_SIZE_8
8
0x1 : USB_RXFIFOSZ_SIZE_16
16
0x2 : USB_RXFIFOSZ_SIZE_32
32
0x3 : USB_RXFIFOSZ_SIZE_64
64
0x4 : USB_RXFIFOSZ_SIZE_128
128
0x5 : USB_RXFIFOSZ_SIZE_256
256
0x6 : USB_RXFIFOSZ_SIZE_512
512
0x7 : USB_RXFIFOSZ_SIZE_1024
1024
0x8 : USB_RXFIFOSZ_SIZE_2048
2048
End of enumeration elements list.
USB_RXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)
USB Transmit FIFO Start Address
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)
USB Transmit FIFO Start Address
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)
USB Receive FIFO Start Address
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)
USB Receive FIFO Start Address
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)
USB Connect Timing
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_CONTIM_WTID : Wait ID
bits : 0 - 3 (4 bit)
USB_CONTIM_WTCON : Connect Wait
bits : 4 - 11 (8 bit)
USB Connect Timing
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_CONTIM_WTID : Wait ID
bits : 0 - 3 (4 bit)
USB_CONTIM_WTCON : Connect Wait
bits : 4 - 11 (8 bit)
USB Full-Speed Last Transaction to End of Frame Timing
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FSEOF_FSEOFG : Full-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)
USB Full-Speed Last Transaction to End of Frame Timing
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FSEOF_FSEOFG : Full-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)
USB Low-Speed Last Transaction to End of Frame Timing
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_LSEOF_LSEOFG : Low-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)
USB Low-Speed Last Transaction to End of Frame Timing
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_LSEOF_LSEOFG : Low-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)
USB Receive Interrupt Enable
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXIE_EP1 : RX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)
USB_RXIE_EP2 : RX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)
USB_RXIE_EP3 : RX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)
USB_RXIE_EP4 : RX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)
USB_RXIE_EP5 : RX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)
USB_RXIE_EP6 : RX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)
USB_RXIE_EP7 : RX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)
USB Receive Interrupt Enable
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_RXIE_EP1 : RX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)
USB_RXIE_EP2 : RX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)
USB_RXIE_EP3 : RX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)
USB_RXIE_EP4 : RX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)
USB_RXIE_EP5 : RX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)
USB_RXIE_EP6 : RX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)
USB_RXIE_EP7 : RX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)
USB General Interrupt Status
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_IS_SUSPEND : SUSPEND Signaling Detected
bits : 0 - 0 (1 bit)
USB_IS_RESUME : RESUME Signaling Detected
bits : 1 - 2 (2 bit)
USB_IS_SOF : Start of Frame
bits : 3 - 6 (4 bit)
USB General Interrupt Status
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_IS_SUSPEND : SUSPEND Signaling Detected
bits : 0 - 0 (1 bit)
USB_IS_RESUME : RESUME Signaling Detected
bits : 1 - 2 (2 bit)
USB_IS_RESET : RESET Signaling Detected
bits : 2 - 4 (3 bit)
USB_IS_SOF : Start of Frame
bits : 3 - 6 (4 bit)
USB Interrupt Enable
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_IE_SUSPND : Enable SUSPEND Interrupt
bits : 0 - 0 (1 bit)
USB_IE_RESUME : Enable RESUME Interrupt
bits : 1 - 2 (2 bit)
USB_IE_SOF : Enable Start-of-Frame Interrupt
bits : 3 - 6 (4 bit)
USB_IE_DISCON : Enable Disconnect Interrupt
bits : 5 - 10 (6 bit)
USB Interrupt Enable
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_IE_SUSPND : Enable SUSPEND Interrupt
bits : 0 - 0 (1 bit)
USB_IE_RESUME : Enable RESUME Interrupt
bits : 1 - 2 (2 bit)
USB_IE_RESET : Enable RESET Interrupt
bits : 2 - 4 (3 bit)
USB_IE_SOF : Enable Start-of-Frame Interrupt
bits : 3 - 6 (4 bit)
USB_IE_DISCON : Enable Disconnect Interrupt
bits : 5 - 10 (6 bit)
USB Frame Value
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FRAME : Frame Number
bits : 0 - 10 (11 bit)
USB Frame Value
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_FRAME : Frame Number
bits : 0 - 10 (11 bit)
USB Endpoint Index
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_EPIDX_EPIDX : Endpoint Index
bits : 0 - 3 (4 bit)
USB Endpoint Index
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_EPIDX_EPIDX : Endpoint Index
bits : 0 - 3 (4 bit)
USB Test Mode
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TEST_FORCEFS : Force Full-Speed Mode
bits : 5 - 10 (6 bit)
USB_TEST_FIFOACC : FIFO Access
bits : 6 - 12 (7 bit)
USB Test Mode
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_TEST_FORCEFS : Force Full-Speed Mode
bits : 5 - 10 (6 bit)
USB_TEST_FIFOACC : FIFO Access
bits : 6 - 12 (7 bit)
USB Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_PP_TYPE : Controller Type
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : USB_PP_TYPE_0
The first-generation USB controller
End of enumeration elements list.
USB_PP_PHY : PHY Present
bits : 4 - 8 (5 bit)
USB_PP_USB : USB Capability
bits : 6 - 13 (8 bit)
Enumeration:
0x1 : USB_PP_USB_DEVICE
DEVICE
0x2 : USB_PP_USB_HOSTDEVICE
HOST
0x3 : USB_PP_USB_OTG
OTG
End of enumeration elements list.
USB_PP_ECNT : Endpoint Count
bits : 8 - 23 (16 bit)
USB Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_PP_TYPE : Controller Type
bits : 0 - 3 (4 bit)
Enumeration:
0x0 : USB_PP_TYPE_0
The first-generation USB controller
End of enumeration elements list.
USB_PP_PHY : PHY Present
bits : 4 - 8 (5 bit)
USB_PP_USB : USB Capability
bits : 6 - 13 (8 bit)
Enumeration:
0x1 : USB_PP_USB_DEVICE
DEVICE
0x2 : USB_PP_USB_HOSTDEVICE
HOST
0x3 : USB_PP_USB_OTG
OTG
End of enumeration elements list.
USB_PP_ECNT : Endpoint Count
bits : 8 - 23 (16 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.