\n

HIB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HIBRTCC

RTCC

HIBCTL

CTL

HIBIM

IM

HIBRIS

RIS

HIBMIS

MIS

HIBIC

IC

HIBRTCT

RTCT

HIBRTCSS

RTCSS

HIBDATA

DATA

HIBRTCM0

RTCM0

HIBRTCLD

RTCLD


HIBRTCC

Hibernation RTC Counter
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRTCC HIBRTCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCC

HIB_RTCC : RTC Counter
bits : 0 - 31 (32 bit)


RTCC

Hibernation RTC Counter
address_offset : 0x0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCC RTCC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCC

HIB_RTCC : RTC Counter
bits : 0 - 31 (32 bit)


HIBCTL

Hibernation Control
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBCTL HIBCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_CTL_RTCEN HIB_CTL_HIBREQ HIB_CTL_RTCWEN HIB_CTL_PINWEN HIB_CTL_CLK32EN HIB_CTL_VABORT HIB_CTL_VDD3ON HIB_CTL_BATWKEN HIB_CTL_BATCHK HIB_CTL_VBATSEL HIB_CTL_OSCBYP HIB_CTL_OSCDRV HIB_CTL_WRC

HIB_CTL_RTCEN : RTC Timer Enable
bits : 0 - 0 (1 bit)

HIB_CTL_HIBREQ : Hibernation Request
bits : 1 - 2 (2 bit)

HIB_CTL_RTCWEN : RTC Wake-up Enable
bits : 3 - 6 (4 bit)

HIB_CTL_PINWEN : External Wake Pin Enable
bits : 4 - 8 (5 bit)

HIB_CTL_CLK32EN : Clocking Enable
bits : 6 - 12 (7 bit)

HIB_CTL_VABORT : Power Cut Abort Enable
bits : 7 - 14 (8 bit)

HIB_CTL_VDD3ON : VDD Powered
bits : 8 - 16 (9 bit)

HIB_CTL_BATWKEN : Wake on Low Battery
bits : 9 - 18 (10 bit)

HIB_CTL_BATCHK : Check Battery Status
bits : 10 - 20 (11 bit)

HIB_CTL_VBATSEL : Select for Low-Battery Comparator
bits : 13 - 27 (15 bit)

Enumeration:

0x0 : HIB_CTL_VBATSEL_1_9V

1.9 Volts

0x1 : HIB_CTL_VBATSEL_2_1V

2.1 Volts (default)

0x2 : HIB_CTL_VBATSEL_2_3V

2.3 Volts

0x3 : HIB_CTL_VBATSEL_2_5V

2.5 Volts

End of enumeration elements list.

HIB_CTL_OSCBYP : Oscillator Bypass
bits : 16 - 32 (17 bit)

HIB_CTL_OSCDRV : Oscillator Drive Capability
bits : 17 - 34 (18 bit)

HIB_CTL_WRC : Write Complete/Capable
bits : 31 - 62 (32 bit)


CTL

Hibernation Control
address_offset : 0x10 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_CTL_RTCEN HIB_CTL_HIBREQ HIB_CTL_RTCWEN HIB_CTL_PINWEN HIB_CTL_CLK32EN HIB_CTL_VABORT HIB_CTL_VDD3ON HIB_CTL_BATWKEN HIB_CTL_BATCHK HIB_CTL_VBATSEL HIB_CTL_OSCBYP HIB_CTL_OSCDRV HIB_CTL_WRC

HIB_CTL_RTCEN : RTC Timer Enable
bits : 0 - 0 (1 bit)

HIB_CTL_HIBREQ : Hibernation Request
bits : 1 - 2 (2 bit)

HIB_CTL_RTCWEN : RTC Wake-up Enable
bits : 3 - 6 (4 bit)

HIB_CTL_PINWEN : External Wake Pin Enable
bits : 4 - 8 (5 bit)

HIB_CTL_CLK32EN : Clocking Enable
bits : 6 - 12 (7 bit)

HIB_CTL_VABORT : Power Cut Abort Enable
bits : 7 - 14 (8 bit)

HIB_CTL_VDD3ON : VDD Powered
bits : 8 - 16 (9 bit)

HIB_CTL_BATWKEN : Wake on Low Battery
bits : 9 - 18 (10 bit)

HIB_CTL_BATCHK : Check Battery Status
bits : 10 - 20 (11 bit)

HIB_CTL_VBATSEL : Select for Low-Battery Comparator
bits : 13 - 27 (15 bit)

Enumeration:

0x0 : HIB_CTL_VBATSEL_1_9V

1.9 Volts

0x1 : HIB_CTL_VBATSEL_2_1V

2.1 Volts (default)

0x2 : HIB_CTL_VBATSEL_2_3V

2.3 Volts

0x3 : HIB_CTL_VBATSEL_2_5V

2.5 Volts

End of enumeration elements list.

HIB_CTL_OSCBYP : Oscillator Bypass
bits : 16 - 32 (17 bit)

HIB_CTL_OSCDRV : Oscillator Drive Capability
bits : 17 - 34 (18 bit)

HIB_CTL_WRC : Write Complete/Capable
bits : 31 - 62 (32 bit)


HIBIM

Hibernation Interrupt Mask
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBIM HIBIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_IM_RTCALT0 HIB_IM_LOWBAT HIB_IM_EXTW HIB_IM_WC

HIB_IM_RTCALT0 : RTC Alert 0 Interrupt Mask
bits : 0 - 0 (1 bit)

HIB_IM_LOWBAT : Low Battery Voltage Interrupt Mask
bits : 2 - 4 (3 bit)

HIB_IM_EXTW : External Wake-Up Interrupt Mask
bits : 3 - 6 (4 bit)

HIB_IM_WC : External Write Complete/Capable Interrupt Mask
bits : 4 - 8 (5 bit)


IM

Hibernation Interrupt Mask
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IM IM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_IM_RTCALT0 HIB_IM_LOWBAT HIB_IM_EXTW HIB_IM_WC

HIB_IM_RTCALT0 : RTC Alert 0 Interrupt Mask
bits : 0 - 0 (1 bit)

HIB_IM_LOWBAT : Low Battery Voltage Interrupt Mask
bits : 2 - 4 (3 bit)

HIB_IM_EXTW : External Wake-Up Interrupt Mask
bits : 3 - 6 (4 bit)

HIB_IM_WC : External Write Complete/Capable Interrupt Mask
bits : 4 - 8 (5 bit)


HIBRIS

Hibernation Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRIS HIBRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RIS_RTCALT0 HIB_RIS_LOWBAT HIB_RIS_EXTW HIB_RIS_WC

HIB_RIS_RTCALT0 : RTC Alert 0 Raw Interrupt Status
bits : 0 - 0 (1 bit)

HIB_RIS_LOWBAT : Low Battery Voltage Raw Interrupt Status
bits : 2 - 4 (3 bit)

HIB_RIS_EXTW : External Wake-Up Raw Interrupt Status
bits : 3 - 6 (4 bit)

HIB_RIS_WC : Write Complete/Capable Raw Interrupt Status
bits : 4 - 8 (5 bit)


RIS

Hibernation Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RIS_RTCALT0 HIB_RIS_LOWBAT HIB_RIS_EXTW HIB_RIS_WC

HIB_RIS_RTCALT0 : RTC Alert 0 Raw Interrupt Status
bits : 0 - 0 (1 bit)

HIB_RIS_LOWBAT : Low Battery Voltage Raw Interrupt Status
bits : 2 - 4 (3 bit)

HIB_RIS_EXTW : External Wake-Up Raw Interrupt Status
bits : 3 - 6 (4 bit)

HIB_RIS_WC : Write Complete/Capable Raw Interrupt Status
bits : 4 - 8 (5 bit)


HIBMIS

Hibernation Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBMIS HIBMIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_MIS_RTCALT0 HIB_MIS_LOWBAT HIB_MIS_EXTW HIB_MIS_WC

HIB_MIS_RTCALT0 : RTC Alert 0 Masked Interrupt Status
bits : 0 - 0 (1 bit)

HIB_MIS_LOWBAT : Low Battery Voltage Masked Interrupt Status
bits : 2 - 4 (3 bit)

HIB_MIS_EXTW : External Wake-Up Masked Interrupt Status
bits : 3 - 6 (4 bit)

HIB_MIS_WC : Write Complete/Capable Masked Interrupt Status
bits : 4 - 8 (5 bit)


MIS

Hibernation Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_MIS_RTCALT0 HIB_MIS_LOWBAT HIB_MIS_EXTW HIB_MIS_WC

HIB_MIS_RTCALT0 : RTC Alert 0 Masked Interrupt Status
bits : 0 - 0 (1 bit)

HIB_MIS_LOWBAT : Low Battery Voltage Masked Interrupt Status
bits : 2 - 4 (3 bit)

HIB_MIS_EXTW : External Wake-Up Masked Interrupt Status
bits : 3 - 6 (4 bit)

HIB_MIS_WC : Write Complete/Capable Masked Interrupt Status
bits : 4 - 8 (5 bit)


HIBIC

Hibernation Interrupt Clear
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBIC HIBIC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_IC_RTCALT0 HIB_IC_LOWBAT HIB_IC_EXTW HIB_IC_WC

HIB_IC_RTCALT0 : RTC Alert0 Masked Interrupt Clear
bits : 0 - 0 (1 bit)

HIB_IC_LOWBAT : Low Battery Voltage Interrupt Clear
bits : 2 - 4 (3 bit)

HIB_IC_EXTW : External Wake-Up Interrupt Clear
bits : 3 - 6 (4 bit)

HIB_IC_WC : Write Complete/Capable Interrupt Clear
bits : 4 - 8 (5 bit)


IC

Hibernation Interrupt Clear
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IC IC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_IC_RTCALT0 HIB_IC_LOWBAT HIB_IC_EXTW HIB_IC_WC

HIB_IC_RTCALT0 : RTC Alert0 Masked Interrupt Clear
bits : 0 - 0 (1 bit)

HIB_IC_LOWBAT : Low Battery Voltage Interrupt Clear
bits : 2 - 4 (3 bit)

HIB_IC_EXTW : External Wake-Up Interrupt Clear
bits : 3 - 6 (4 bit)

HIB_IC_WC : Write Complete/Capable Interrupt Clear
bits : 4 - 8 (5 bit)


HIBRTCT

Hibernation RTC Trim
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRTCT HIBRTCT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCT_TRIM

HIB_RTCT_TRIM : RTC Trim Value
bits : 0 - 15 (16 bit)


RTCT

Hibernation RTC Trim
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCT RTCT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCT_TRIM

HIB_RTCT_TRIM : RTC Trim Value
bits : 0 - 15 (16 bit)


HIBRTCSS

Hibernation RTC Sub Seconds
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRTCSS HIBRTCSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCSS_RTCSSC HIB_RTCSS_RTCSSM

HIB_RTCSS_RTCSSC : RTC Sub Seconds Count
bits : 0 - 14 (15 bit)

HIB_RTCSS_RTCSSM : RTC Sub Seconds Match
bits : 16 - 46 (31 bit)


RTCSS

Hibernation RTC Sub Seconds
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCSS RTCSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCSS_RTCSSC HIB_RTCSS_RTCSSM

HIB_RTCSS_RTCSSC : RTC Sub Seconds Count
bits : 0 - 14 (15 bit)

HIB_RTCSS_RTCSSM : RTC Sub Seconds Match
bits : 16 - 46 (31 bit)


HIBDATA

Hibernation Data
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBDATA HIBDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_DATA_RTD

HIB_DATA_RTD : Hibernation Module NV Data
bits : 0 - 31 (32 bit)


DATA

Hibernation Data
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_DATA_RTD

HIB_DATA_RTD : Hibernation Module NV Data
bits : 0 - 31 (32 bit)


HIBRTCM0

Hibernation RTC Match 0
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRTCM0 HIBRTCM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCM0

HIB_RTCM0 : RTC Match 0
bits : 0 - 31 (32 bit)


RTCM0

Hibernation RTC Match 0
address_offset : 0x4 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCM0 RTCM0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCM0

HIB_RTCM0 : RTC Match 0
bits : 0 - 31 (32 bit)


HIBRTCLD

Hibernation RTC Load
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIBRTCLD HIBRTCLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCLD

HIB_RTCLD : RTC Load
bits : 0 - 31 (32 bit)


RTCLD

Hibernation RTC Load
address_offset : 0xC Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTCLD RTCLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIB_RTCLD

HIB_RTCLD : RTC Load
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.