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USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

USB0FADDR

FADDR

USB0POWER

POWER

USB0CSRL0

CSRL0

USB0CSRH0

CSRH0

USB0COUNT0

COUNT0

USB0TYPE0

TYPE0

USB0NAKLMT

NAKLMT

USB0TXMAXP1

TXMAXP1

USB0TXCSRL1

TXCSRL1

USB0TXCSRH1

TXCSRH1

USB0RXMAXP1

RXMAXP1

USB0RXCSRL1

RXCSRL1

USB0RXCSRH1

RXCSRH1

USB0RXCOUNT1

RXCOUNT1

USB0TXTYPE1

TXTYPE1

USB0TXINTERVAL1

TXINTERVAL1

USB0RXTYPE1

RXTYPE1

USB0RXINTERVAL1

RXINTERVAL1

USB0TXMAXP2

TXMAXP2

USB0TXCSRL2

TXCSRL2

USB0TXCSRH2

TXCSRH2

USB0RXMAXP2

RXMAXP2

USB0RXCSRL2

RXCSRL2

USB0RXCSRH2

RXCSRH2

USB0RXCOUNT2

RXCOUNT2

USB0TXTYPE2

TXTYPE2

USB0TXINTERVAL2

TXINTERVAL2

USB0RXTYPE2

RXTYPE2

USB0RXINTERVAL2

RXINTERVAL2

USB0TXMAXP3

TXMAXP3

USB0TXCSRL3

TXCSRL3

USB0TXCSRH3

TXCSRH3

USB0RXMAXP3

RXMAXP3

USB0RXCSRL3

RXCSRL3

USB0RXCSRH3

RXCSRH3

USB0RXCOUNT3

RXCOUNT3

USB0TXTYPE3

TXTYPE3

USB0TXINTERVAL3

TXINTERVAL3

USB0RXTYPE3

RXTYPE3

USB0RXINTERVAL3

RXINTERVAL3

USB0TXMAXP4

TXMAXP4

USB0TXCSRL4

TXCSRL4

USB0TXCSRH4

TXCSRH4

USB0RXMAXP4

RXMAXP4

USB0RXCSRL4

RXCSRL4

USB0RXCSRH4

RXCSRH4

USB0RXCOUNT4

RXCOUNT4

USB0TXTYPE4

TXTYPE4

USB0TXINTERVAL4

TXINTERVAL4

USB0RXTYPE4

RXTYPE4

USB0RXINTERVAL4

RXINTERVAL4

USB0TXMAXP5

TXMAXP5

USB0TXCSRL5

TXCSRL5

USB0TXCSRH5

TXCSRH5

USB0RXMAXP5

RXMAXP5

USB0RXCSRL5

RXCSRL5

USB0RXCSRH5

RXCSRH5

USB0RXCOUNT5

RXCOUNT5

USB0TXTYPE5

TXTYPE5

USB0TXINTERVAL5

TXINTERVAL5

USB0RXTYPE5

RXTYPE5

USB0RXINTERVAL5

RXINTERVAL5

USB0TXMAXP6

TXMAXP6

USB0TXCSRL6

TXCSRL6

USB0TXCSRH6

TXCSRH6

USB0RXMAXP6

RXMAXP6

USB0RXCSRL6

RXCSRL6

USB0RXCSRH6

RXCSRH6

USB0RXCOUNT6

RXCOUNT6

USB0TXTYPE6

TXTYPE6

USB0TXINTERVAL6

TXINTERVAL6

USB0RXTYPE6

RXTYPE6

USB0RXINTERVAL6

RXINTERVAL6

USB0TXMAXP7

TXMAXP7

USB0TXCSRL7

TXCSRL7

USB0TXCSRH7

TXCSRH7

USB0RXMAXP7

RXMAXP7

USB0RXCSRL7

RXCSRL7

USB0RXCSRH7

RXCSRH7

USB0RXCOUNT7

RXCOUNT7

USB0TXTYPE7

TXTYPE7

USB0TXINTERVAL7

TXINTERVAL7

USB0RXTYPE7

RXTYPE7

USB0RXINTERVAL7

RXINTERVAL7

USB0TXIS

TXIS

USB0FIFO0

FIFO0

USB0FIFO1

FIFO1

USB0FIFO2

FIFO2

USB0FIFO3

FIFO3

USB0FIFO4

FIFO4

USB0RQPKTCOUNT1

RQPKTCOUNT1

USB0RQPKTCOUNT2

RQPKTCOUNT2

USB0RQPKTCOUNT3

RQPKTCOUNT3

USB0RQPKTCOUNT4

RQPKTCOUNT4

USB0RQPKTCOUNT5

RQPKTCOUNT5

USB0RQPKTCOUNT6

RQPKTCOUNT6

USB0RQPKTCOUNT7

RQPKTCOUNT7

USB0FIFO5

FIFO5

USB0RXDPKTBUFDIS

RXDPKTBUFDIS

USB0TXDPKTBUFDIS

TXDPKTBUFDIS

USB0FIFO6

FIFO6

USB0FIFO7

FIFO7

USB0RXIS

RXIS

USB0EPC

EPC

USB0EPCRIS

EPCRIS

USB0EPCIM

EPCIM

USB0EPCISC

EPCISC

USB0DRRIS

DRRIS

USB0DRIM

DRIM

USB0DRISC

DRISC

USB0GPCS

GPCS

USB0VDC

VDC

USB0VDCRIS

VDCRIS

USB0VDCIM

VDCIM

USB0VDCISC

VDCISC

USB0IDVRIS

IDVRIS

USB0IDVIM

IDVIM

USB0IDVISC

IDVISC

USB0DMASEL

DMASEL

USB0TXIE

TXIE

USB0DEVCTL

DEVCTL

USB0TXFIFOSZ

TXFIFOSZ

USB0RXFIFOSZ

RXFIFOSZ

USB0TXFIFOADD

TXFIFOADD

USB0RXFIFOADD

RXFIFOADD

USB0CONTIM

CONTIM

USB0VPLEN

VPLEN

USB0FSEOF

FSEOF

USB0LSEOF

LSEOF

USB0RXIE

RXIE

USB0TXFUNCADDR0

TXFUNCADDR0

USB0TXHUBADDR0

TXHUBADDR0

USB0TXHUBPORT0

TXHUBPORT0

USB0TXFUNCADDR1

TXFUNCADDR1

USB0TXHUBADDR1

TXHUBADDR1

USB0TXHUBPORT1

TXHUBPORT1

USB0RXFUNCADDR1

RXFUNCADDR1

USB0RXHUBADDR1

RXHUBADDR1

USB0RXHUBPORT1

RXHUBPORT1

USB0TXFUNCADDR2

TXFUNCADDR2

USB0TXHUBADDR2

TXHUBADDR2

USB0TXHUBPORT2

TXHUBPORT2

USB0RXFUNCADDR2

RXFUNCADDR2

USB0RXHUBADDR2

RXHUBADDR2

USB0RXHUBPORT2

RXHUBPORT2

USB0TXFUNCADDR3

TXFUNCADDR3

USB0TXHUBADDR3

TXHUBADDR3

USB0TXHUBPORT3

TXHUBPORT3

USB0RXFUNCADDR3

RXFUNCADDR3

USB0RXHUBADDR3

RXHUBADDR3

USB0RXHUBPORT3

RXHUBPORT3

USB0IS

IS

USB0TXFUNCADDR4

TXFUNCADDR4

USB0TXHUBADDR4

TXHUBADDR4

USB0TXHUBPORT4

TXHUBPORT4

USB0RXFUNCADDR4

RXFUNCADDR4

USB0RXHUBADDR4

RXHUBADDR4

USB0RXHUBPORT4

RXHUBPORT4

USB0TXFUNCADDR5

TXFUNCADDR5

USB0TXHUBADDR5

TXHUBADDR5

USB0TXHUBPORT5

TXHUBPORT5

USB0RXFUNCADDR5

RXFUNCADDR5

USB0RXHUBADDR5

RXHUBADDR5

USB0RXHUBPORT5

RXHUBPORT5

USB0IE

IE

USB0TXFUNCADDR6

TXFUNCADDR6

USB0TXHUBADDR6

TXHUBADDR6

USB0TXHUBPORT6

TXHUBPORT6

USB0RXFUNCADDR6

RXFUNCADDR6

USB0RXHUBADDR6

RXHUBADDR6

USB0RXHUBPORT6

RXHUBPORT6

USB0TXFUNCADDR7

TXFUNCADDR7

USB0TXHUBADDR7

TXHUBADDR7

USB0TXHUBPORT7

TXHUBPORT7

USB0RXFUNCADDR7

RXFUNCADDR7

USB0RXHUBADDR7

RXHUBADDR7

USB0RXHUBPORT7

RXHUBPORT7

USB0FRAME

FRAME

USB0EPIDX

EPIDX

USB0TEST

TEST

USB0PP

PP


USB0FADDR

USB Device Functional Address
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FADDR USB0FADDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_FADDR

USB_FADDR : Function Address
bits : 0 - 6 (7 bit)


FADDR

USB Device Functional Address
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FADDR FADDR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_FADDR

USB_FADDR : Function Address
bits : 0 - 6 (7 bit)


USB0POWER

USB Power
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0POWER USB0POWER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_POWER_PWRDNPHY USB_POWER_SUSPEND USB_POWER_RESUME USB_POWER_RESET USB_POWER_SOFTCONN USB_POWER_ISOUP

USB_POWER_PWRDNPHY : Power Down PHY
bits : 0 - 0 (1 bit)

USB_POWER_SUSPEND : SUSPEND Mode
bits : 1 - 2 (2 bit)

USB_POWER_RESUME : RESUME Signaling
bits : 2 - 4 (3 bit)

USB_POWER_RESET : RESET Signaling
bits : 3 - 6 (4 bit)

USB_POWER_SOFTCONN : Soft Connect/Disconnect
bits : 6 - 12 (7 bit)

USB_POWER_ISOUP : Isochronous Update
bits : 7 - 14 (8 bit)


POWER

USB Power
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POWER POWER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_POWER_PWRDNPHY USB_POWER_SUSPEND USB_POWER_RESUME USB_POWER_RESET USB_POWER_SOFTCONN USB_POWER_ISOUP

USB_POWER_PWRDNPHY : Power Down PHY
bits : 0 - 0 (1 bit)

USB_POWER_SUSPEND : SUSPEND Mode
bits : 1 - 2 (2 bit)

USB_POWER_RESUME : RESUME Signaling
bits : 2 - 4 (3 bit)

USB_POWER_RESET : RESET Signaling
bits : 3 - 6 (4 bit)

USB_POWER_SOFTCONN : Soft Connect/Disconnect
bits : 6 - 12 (7 bit)

USB_POWER_ISOUP : Isochronous Update
bits : 7 - 14 (8 bit)


USB0CSRL0

USB Control and Status Endpoint 0 Low
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USB0CSRL0 USB0CSRL0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_CSRL0_RXRDY USB_CSRL0_TXRDY USB_CSRL0_STALLED USB_CSRL0_DATAEND USB_CSRL0_SETEND USB_CSRL0_STALL USB_CSRL0_RXRDYC USB_CSRL0_SETENDC

USB_CSRL0_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
access : write-only

USB_CSRL0_TXRDY : Transmit Packet Ready
bits : 1 - 2 (2 bit)
access : write-only

USB_CSRL0_STALLED : Endpoint Stalled
bits : 2 - 4 (3 bit)
access : write-only

USB_CSRL0_DATAEND : Data End
bits : 3 - 6 (4 bit)
access : write-only

USB_CSRL0_SETEND : Setup End
bits : 4 - 8 (5 bit)
access : write-only

USB_CSRL0_STALL : Send Stall
bits : 5 - 10 (6 bit)
access : write-only

USB_CSRL0_RXRDYC : RXRDY Clear
bits : 6 - 12 (7 bit)
access : write-only

USB_CSRL0_SETENDC : Setup End Clear
bits : 7 - 14 (8 bit)
access : write-only


CSRL0

USB Control and Status Endpoint 0 Low
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CSRL0 CSRL0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_CSRL0_RXRDY USB_CSRL0_TXRDY USB_CSRL0_STALLED USB_CSRL0_DATAEND USB_CSRL0_SETUP USB_CSRL0_SETEND USB_CSRL0_ERROR USB_CSRL0_STALL USB_CSRL0_REQPKT USB_CSRL0_RXRDYC USB_CSRL0_STATUS USB_CSRL0_SETENDC USB_CSRL0_NAKTO

USB_CSRL0_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)
access : write-only

USB_CSRL0_TXRDY : Transmit Packet Ready
bits : 1 - 2 (2 bit)
access : write-only

USB_CSRL0_STALLED : Endpoint Stalled
bits : 2 - 4 (3 bit)
access : write-only

USB_CSRL0_DATAEND : Data End
bits : 3 - 6 (4 bit)
access : write-only

USB_CSRL0_SETUP : Setup Packet
bits : 3 - 6 (4 bit)
access : write-only

USB_CSRL0_SETEND : Setup End
bits : 4 - 8 (5 bit)
access : write-only

USB_CSRL0_ERROR : Error
bits : 4 - 8 (5 bit)
access : write-only

USB_CSRL0_STALL : Send Stall
bits : 5 - 10 (6 bit)
access : write-only

USB_CSRL0_REQPKT : Request Packet
bits : 5 - 10 (6 bit)
access : write-only

USB_CSRL0_RXRDYC : RXRDY Clear
bits : 6 - 12 (7 bit)
access : write-only

USB_CSRL0_STATUS : STATUS Packet
bits : 6 - 12 (7 bit)
access : write-only

USB_CSRL0_SETENDC : Setup End Clear
bits : 7 - 14 (8 bit)
access : write-only

USB_CSRL0_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)
access : write-only


USB0CSRH0

USB Control and Status Endpoint 0 High
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USB0CSRH0 USB0CSRH0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_CSRH0_FLUSH USB_CSRH0_DT USB_CSRH0_DTWE

USB_CSRH0_FLUSH : Flush FIFO
bits : 0 - 0 (1 bit)
access : write-only

USB_CSRH0_DT : Data Toggle
bits : 1 - 2 (2 bit)
access : write-only

USB_CSRH0_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)
access : write-only


CSRH0

USB Control and Status Endpoint 0 High
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CSRH0 CSRH0 write-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_CSRH0_FLUSH USB_CSRH0_DT USB_CSRH0_DTWE

USB_CSRH0_FLUSH : Flush FIFO
bits : 0 - 0 (1 bit)
access : write-only

USB_CSRH0_DT : Data Toggle
bits : 1 - 2 (2 bit)
access : write-only

USB_CSRH0_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)
access : write-only


USB0COUNT0

USB Receive Byte Count Endpoint 0
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0COUNT0 USB0COUNT0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_COUNT0_COUNT

USB_COUNT0_COUNT : FIFO Count
bits : 0 - 6 (7 bit)


COUNT0

USB Receive Byte Count Endpoint 0
address_offset : 0x108 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COUNT0 COUNT0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_COUNT0_COUNT

USB_COUNT0_COUNT : FIFO Count
bits : 0 - 6 (7 bit)


USB0TYPE0

USB Type Endpoint 0
address_offset : 0x10A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TYPE0 USB0TYPE0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TYPE0_SPEED

USB_TYPE0_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x2 : USB_TYPE0_SPEED_FULL

Full

0x3 : USB_TYPE0_SPEED_LOW

Low

End of enumeration elements list.


TYPE0

USB Type Endpoint 0
address_offset : 0x10A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TYPE0 TYPE0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TYPE0_SPEED

USB_TYPE0_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x2 : USB_TYPE0_SPEED_FULL

Full

0x3 : USB_TYPE0_SPEED_LOW

Low

End of enumeration elements list.


USB0NAKLMT

USB NAK Limit
address_offset : 0x10B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0NAKLMT USB0NAKLMT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_NAKLMT_NAKLMT

USB_NAKLMT_NAKLMT : EP0 NAK Limit
bits : 0 - 4 (5 bit)


NAKLMT

USB NAK Limit
address_offset : 0x10B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NAKLMT NAKLMT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_NAKLMT_NAKLMT

USB_NAKLMT_NAKLMT : EP0 NAK Limit
bits : 0 - 4 (5 bit)


USB0TXMAXP1

USB Maximum Transmit Data Endpoint 1
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP1 USB0TXMAXP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP1_MAXLOAD

USB_TXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP1

USB Maximum Transmit Data Endpoint 1
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP1 TXMAXP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP1_MAXLOAD

USB_TXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL1

USB Transmit Control and Status Endpoint 1 Low
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL1 USB0TXCSRL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL1_TXRDY USB_TXCSRL1_FIFONE USB_TXCSRL1_ERROR USB_TXCSRL1_FLUSH USB_TXCSRL1_SETUP USB_TXCSRL1_STALLED USB_TXCSRL1_CLRDT USB_TXCSRL1_NAKTO

USB_TXCSRL1_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL1_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL1_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL1_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL1_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL1_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL1_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL1_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL1

USB Transmit Control and Status Endpoint 1 Low
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL1 TXCSRL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL1_TXRDY USB_TXCSRL1_FIFONE USB_TXCSRL1_ERROR USB_TXCSRL1_UNDRN USB_TXCSRL1_FLUSH USB_TXCSRL1_SETUP USB_TXCSRL1_STALL USB_TXCSRL1_STALLED USB_TXCSRL1_CLRDT USB_TXCSRL1_NAKTO

USB_TXCSRL1_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL1_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL1_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL1_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL1_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL1_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL1_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL1_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL1_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL1_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH1

USB Transmit Control and Status Endpoint 1 High
address_offset : 0x113 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH1 USB0TXCSRH1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH1_DT USB_TXCSRH1_DTWE USB_TXCSRH1_DMAMOD USB_TXCSRH1_FDT USB_TXCSRH1_DMAEN USB_TXCSRH1_MODE USB_TXCSRH1_ISO USB_TXCSRH1_AUTOSET

USB_TXCSRH1_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH1_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH1_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH1_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH1_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH1_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH1_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH1_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH1

USB Transmit Control and Status Endpoint 1 High
address_offset : 0x113 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH1 TXCSRH1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH1_DT USB_TXCSRH1_DTWE USB_TXCSRH1_DMAMOD USB_TXCSRH1_FDT USB_TXCSRH1_DMAEN USB_TXCSRH1_MODE USB_TXCSRH1_ISO USB_TXCSRH1_AUTOSET

USB_TXCSRH1_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH1_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH1_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH1_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH1_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH1_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH1_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH1_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP1

USB Maximum Receive Data Endpoint 1
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP1 USB0RXMAXP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP1_MAXLOAD

USB_RXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP1

USB Maximum Receive Data Endpoint 1
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP1 RXMAXP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP1_MAXLOAD

USB_RXMAXP1_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL1

USB Receive Control and Status Endpoint 1 Low
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL1 USB0RXCSRL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL1_RXRDY USB_RXCSRL1_FULL USB_RXCSRL1_OVER USB_RXCSRL1_DATAERR USB_RXCSRL1_FLUSH USB_RXCSRL1_STALL USB_RXCSRL1_STALLED USB_RXCSRL1_CLRDT

USB_RXCSRL1_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL1_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL1_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL1_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL1_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL1_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL1_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL1_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL1

USB Receive Control and Status Endpoint 1 Low
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL1 RXCSRL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL1_RXRDY USB_RXCSRL1_FULL USB_RXCSRL1_OVER USB_RXCSRL1_ERROR USB_RXCSRL1_DATAERR USB_RXCSRL1_NAKTO USB_RXCSRL1_FLUSH USB_RXCSRL1_STALL USB_RXCSRL1_REQPKT USB_RXCSRL1_STALLED USB_RXCSRL1_CLRDT

USB_RXCSRL1_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL1_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL1_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL1_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL1_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL1_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL1_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL1_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL1_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL1_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL1_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH1

USB Receive Control and Status Endpoint 1 High
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH1 USB0RXCSRH1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH1_DT USB_RXCSRH1_DTWE USB_RXCSRH1_DMAMOD USB_RXCSRH1_PIDERR USB_RXCSRH1_DMAEN USB_RXCSRH1_AUTORQ USB_RXCSRH1_AUTOCL

USB_RXCSRH1_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH1_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH1_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH1_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH1_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH1_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH1_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH1

USB Receive Control and Status Endpoint 1 High
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH1 RXCSRH1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH1_DT USB_RXCSRH1_DTWE USB_RXCSRH1_DMAMOD USB_RXCSRH1_PIDERR USB_RXCSRH1_DISNYET USB_RXCSRH1_DMAEN USB_RXCSRH1_AUTORQ USB_RXCSRH1_ISO USB_RXCSRH1_AUTOCL

USB_RXCSRH1_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH1_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH1_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH1_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH1_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH1_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH1_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH1_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH1_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT1

USB Receive Byte Count Endpoint 1
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT1 USB0RXCOUNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT1_COUNT

USB_RXCOUNT1_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT1

USB Receive Byte Count Endpoint 1
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT1 RXCOUNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT1_COUNT

USB_RXCOUNT1_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE1

USB Host Transmit Configure Type Endpoint 1
address_offset : 0x11A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE1 USB0TXTYPE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE1_TEP USB_TXTYPE1_PROTO USB_TXTYPE1_SPEED

USB_TXTYPE1_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE1_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE1_PROTO_CTRL

Control

0x1 : USB_TXTYPE1_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE1_PROTO_BULK

Bulk

0x3 : USB_TXTYPE1_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE1_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE1_SPEED_DFLT

Default

0x2 : USB_TXTYPE1_SPEED_FULL

Full

0x3 : USB_TXTYPE1_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE1

USB Host Transmit Configure Type Endpoint 1
address_offset : 0x11A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE1 TXTYPE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE1_TEP USB_TXTYPE1_PROTO USB_TXTYPE1_SPEED

USB_TXTYPE1_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE1_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE1_PROTO_CTRL

Control

0x1 : USB_TXTYPE1_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE1_PROTO_BULK

Bulk

0x3 : USB_TXTYPE1_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE1_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE1_SPEED_DFLT

Default

0x2 : USB_TXTYPE1_SPEED_FULL

Full

0x3 : USB_TXTYPE1_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL1

USB Host Transmit Interval Endpoint 1
address_offset : 0x11B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL1 USB0TXINTERVAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL1_TXPOLL

USB_TXINTERVAL1_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL1

USB Host Transmit Interval Endpoint 1
address_offset : 0x11B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL1 TXINTERVAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL1_TXPOLL USB_TXINTERVAL1_NAKLMT

USB_TXINTERVAL1_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL1_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE1

USB Host Configure Receive Type Endpoint 1
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE1 USB0RXTYPE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE1_TEP USB_RXTYPE1_PROTO USB_RXTYPE1_SPEED

USB_RXTYPE1_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE1_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE1_PROTO_CTRL

Control

0x1 : USB_RXTYPE1_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE1_PROTO_BULK

Bulk

0x3 : USB_RXTYPE1_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE1_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE1_SPEED_DFLT

Default

0x2 : USB_RXTYPE1_SPEED_FULL

Full

0x3 : USB_RXTYPE1_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE1

USB Host Configure Receive Type Endpoint 1
address_offset : 0x11C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE1 RXTYPE1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE1_TEP USB_RXTYPE1_PROTO USB_RXTYPE1_SPEED

USB_RXTYPE1_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE1_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE1_PROTO_CTRL

Control

0x1 : USB_RXTYPE1_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE1_PROTO_BULK

Bulk

0x3 : USB_RXTYPE1_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE1_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE1_SPEED_DFLT

Default

0x2 : USB_RXTYPE1_SPEED_FULL

Full

0x3 : USB_RXTYPE1_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL1

USB Host Receive Polling Interval Endpoint 1
address_offset : 0x11D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL1 USB0RXINTERVAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL1_TXPOLL

USB_RXINTERVAL1_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL1

USB Host Receive Polling Interval Endpoint 1
address_offset : 0x11D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL1 RXINTERVAL1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL1_TXPOLL USB_RXINTERVAL1_NAKLMT

USB_RXINTERVAL1_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL1_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXMAXP2

USB Maximum Transmit Data Endpoint 2
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP2 USB0TXMAXP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP2_MAXLOAD

USB_TXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP2

USB Maximum Transmit Data Endpoint 2
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP2 TXMAXP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP2_MAXLOAD

USB_TXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL2

USB Transmit Control and Status Endpoint 2 Low
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL2 USB0TXCSRL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL2_TXRDY USB_TXCSRL2_FIFONE USB_TXCSRL2_ERROR USB_TXCSRL2_FLUSH USB_TXCSRL2_SETUP USB_TXCSRL2_STALLED USB_TXCSRL2_CLRDT USB_TXCSRL2_NAKTO

USB_TXCSRL2_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL2_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL2_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL2_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL2_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL2_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL2_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL2_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL2

USB Transmit Control and Status Endpoint 2 Low
address_offset : 0x122 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL2 TXCSRL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL2_TXRDY USB_TXCSRL2_FIFONE USB_TXCSRL2_ERROR USB_TXCSRL2_UNDRN USB_TXCSRL2_FLUSH USB_TXCSRL2_SETUP USB_TXCSRL2_STALL USB_TXCSRL2_STALLED USB_TXCSRL2_CLRDT USB_TXCSRL2_NAKTO

USB_TXCSRL2_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL2_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL2_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL2_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL2_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL2_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL2_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL2_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL2_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL2_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH2

USB Transmit Control and Status Endpoint 2 High
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH2 USB0TXCSRH2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH2_DT USB_TXCSRH2_DTWE USB_TXCSRH2_DMAMOD USB_TXCSRH2_FDT USB_TXCSRH2_DMAEN USB_TXCSRH2_MODE USB_TXCSRH2_ISO USB_TXCSRH2_AUTOSET

USB_TXCSRH2_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH2_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH2_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH2_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH2_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH2_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH2_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH2_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH2

USB Transmit Control and Status Endpoint 2 High
address_offset : 0x123 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH2 TXCSRH2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH2_DT USB_TXCSRH2_DTWE USB_TXCSRH2_DMAMOD USB_TXCSRH2_FDT USB_TXCSRH2_DMAEN USB_TXCSRH2_MODE USB_TXCSRH2_ISO USB_TXCSRH2_AUTOSET

USB_TXCSRH2_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH2_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH2_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH2_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH2_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH2_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH2_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH2_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP2

USB Maximum Receive Data Endpoint 2
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP2 USB0RXMAXP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP2_MAXLOAD

USB_RXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP2

USB Maximum Receive Data Endpoint 2
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP2 RXMAXP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP2_MAXLOAD

USB_RXMAXP2_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL2

USB Receive Control and Status Endpoint 2 Low
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL2 USB0RXCSRL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL2_RXRDY USB_RXCSRL2_FULL USB_RXCSRL2_OVER USB_RXCSRL2_DATAERR USB_RXCSRL2_FLUSH USB_RXCSRL2_STALL USB_RXCSRL2_STALLED USB_RXCSRL2_CLRDT

USB_RXCSRL2_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL2_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL2_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL2_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL2_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL2_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL2_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL2_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL2

USB Receive Control and Status Endpoint 2 Low
address_offset : 0x126 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL2 RXCSRL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL2_RXRDY USB_RXCSRL2_FULL USB_RXCSRL2_OVER USB_RXCSRL2_ERROR USB_RXCSRL2_DATAERR USB_RXCSRL2_NAKTO USB_RXCSRL2_FLUSH USB_RXCSRL2_STALL USB_RXCSRL2_REQPKT USB_RXCSRL2_STALLED USB_RXCSRL2_CLRDT

USB_RXCSRL2_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL2_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL2_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL2_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL2_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL2_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL2_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL2_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL2_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL2_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL2_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH2

USB Receive Control and Status Endpoint 2 High
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH2 USB0RXCSRH2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH2_DT USB_RXCSRH2_DTWE USB_RXCSRH2_DMAMOD USB_RXCSRH2_PIDERR USB_RXCSRH2_DMAEN USB_RXCSRH2_AUTORQ USB_RXCSRH2_AUTOCL

USB_RXCSRH2_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH2_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH2_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH2_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH2_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH2_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH2_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH2

USB Receive Control and Status Endpoint 2 High
address_offset : 0x127 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH2 RXCSRH2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH2_DT USB_RXCSRH2_DTWE USB_RXCSRH2_DMAMOD USB_RXCSRH2_PIDERR USB_RXCSRH2_DISNYET USB_RXCSRH2_DMAEN USB_RXCSRH2_AUTORQ USB_RXCSRH2_ISO USB_RXCSRH2_AUTOCL

USB_RXCSRH2_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH2_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH2_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH2_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH2_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH2_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH2_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH2_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH2_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT2

USB Receive Byte Count Endpoint 2
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT2 USB0RXCOUNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT2_COUNT

USB_RXCOUNT2_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT2

USB Receive Byte Count Endpoint 2
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT2 RXCOUNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT2_COUNT

USB_RXCOUNT2_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE2

USB Host Transmit Configure Type Endpoint 2
address_offset : 0x12A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE2 USB0TXTYPE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE2_TEP USB_TXTYPE2_PROTO USB_TXTYPE2_SPEED

USB_TXTYPE2_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE2_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE2_PROTO_CTRL

Control

0x1 : USB_TXTYPE2_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE2_PROTO_BULK

Bulk

0x3 : USB_TXTYPE2_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE2_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE2_SPEED_DFLT

Default

0x2 : USB_TXTYPE2_SPEED_FULL

Full

0x3 : USB_TXTYPE2_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE2

USB Host Transmit Configure Type Endpoint 2
address_offset : 0x12A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE2 TXTYPE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE2_TEP USB_TXTYPE2_PROTO USB_TXTYPE2_SPEED

USB_TXTYPE2_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE2_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE2_PROTO_CTRL

Control

0x1 : USB_TXTYPE2_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE2_PROTO_BULK

Bulk

0x3 : USB_TXTYPE2_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE2_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE2_SPEED_DFLT

Default

0x2 : USB_TXTYPE2_SPEED_FULL

Full

0x3 : USB_TXTYPE2_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL2

USB Host Transmit Interval Endpoint 2
address_offset : 0x12B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL2 USB0TXINTERVAL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL2_TXPOLL

USB_TXINTERVAL2_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL2

USB Host Transmit Interval Endpoint 2
address_offset : 0x12B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL2 TXINTERVAL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL2_TXPOLL USB_TXINTERVAL2_NAKLMT

USB_TXINTERVAL2_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL2_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE2

USB Host Configure Receive Type Endpoint 2
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE2 USB0RXTYPE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE2_TEP USB_RXTYPE2_PROTO USB_RXTYPE2_SPEED

USB_RXTYPE2_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE2_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE2_PROTO_CTRL

Control

0x1 : USB_RXTYPE2_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE2_PROTO_BULK

Bulk

0x3 : USB_RXTYPE2_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE2_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE2_SPEED_DFLT

Default

0x2 : USB_RXTYPE2_SPEED_FULL

Full

0x3 : USB_RXTYPE2_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE2

USB Host Configure Receive Type Endpoint 2
address_offset : 0x12C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE2 RXTYPE2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE2_TEP USB_RXTYPE2_PROTO USB_RXTYPE2_SPEED

USB_RXTYPE2_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE2_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE2_PROTO_CTRL

Control

0x1 : USB_RXTYPE2_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE2_PROTO_BULK

Bulk

0x3 : USB_RXTYPE2_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE2_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE2_SPEED_DFLT

Default

0x2 : USB_RXTYPE2_SPEED_FULL

Full

0x3 : USB_RXTYPE2_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL2

USB Host Receive Polling Interval Endpoint 2
address_offset : 0x12D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL2 USB0RXINTERVAL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL2_TXPOLL

USB_RXINTERVAL2_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL2

USB Host Receive Polling Interval Endpoint 2
address_offset : 0x12D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL2 RXINTERVAL2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL2_TXPOLL USB_RXINTERVAL2_NAKLMT

USB_RXINTERVAL2_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL2_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXMAXP3

USB Maximum Transmit Data Endpoint 3
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP3 USB0TXMAXP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP3_MAXLOAD

USB_TXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP3

USB Maximum Transmit Data Endpoint 3
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP3 TXMAXP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP3_MAXLOAD

USB_TXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL3

USB Transmit Control and Status Endpoint 3 Low
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL3 USB0TXCSRL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL3_TXRDY USB_TXCSRL3_FIFONE USB_TXCSRL3_ERROR USB_TXCSRL3_FLUSH USB_TXCSRL3_SETUP USB_TXCSRL3_STALLED USB_TXCSRL3_CLRDT USB_TXCSRL3_NAKTO

USB_TXCSRL3_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL3_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL3_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL3_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL3_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL3_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL3_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL3_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL3

USB Transmit Control and Status Endpoint 3 Low
address_offset : 0x132 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL3 TXCSRL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL3_TXRDY USB_TXCSRL3_FIFONE USB_TXCSRL3_ERROR USB_TXCSRL3_UNDRN USB_TXCSRL3_FLUSH USB_TXCSRL3_SETUP USB_TXCSRL3_STALL USB_TXCSRL3_STALLED USB_TXCSRL3_CLRDT USB_TXCSRL3_NAKTO

USB_TXCSRL3_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL3_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL3_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL3_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL3_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL3_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL3_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL3_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL3_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL3_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH3

USB Transmit Control and Status Endpoint 3 High
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH3 USB0TXCSRH3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH3_DT USB_TXCSRH3_DTWE USB_TXCSRH3_DMAMOD USB_TXCSRH3_FDT USB_TXCSRH3_DMAEN USB_TXCSRH3_MODE USB_TXCSRH3_ISO USB_TXCSRH3_AUTOSET

USB_TXCSRH3_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH3_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH3_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH3_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH3_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH3_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH3_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH3_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH3

USB Transmit Control and Status Endpoint 3 High
address_offset : 0x133 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH3 TXCSRH3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH3_DT USB_TXCSRH3_DTWE USB_TXCSRH3_DMAMOD USB_TXCSRH3_FDT USB_TXCSRH3_DMAEN USB_TXCSRH3_MODE USB_TXCSRH3_ISO USB_TXCSRH3_AUTOSET

USB_TXCSRH3_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH3_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH3_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH3_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH3_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH3_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH3_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH3_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP3

USB Maximum Receive Data Endpoint 3
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP3 USB0RXMAXP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP3_MAXLOAD

USB_RXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP3

USB Maximum Receive Data Endpoint 3
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP3 RXMAXP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP3_MAXLOAD

USB_RXMAXP3_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL3

USB Receive Control and Status Endpoint 3 Low
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL3 USB0RXCSRL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL3_RXRDY USB_RXCSRL3_FULL USB_RXCSRL3_OVER USB_RXCSRL3_DATAERR USB_RXCSRL3_FLUSH USB_RXCSRL3_STALL USB_RXCSRL3_STALLED USB_RXCSRL3_CLRDT

USB_RXCSRL3_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL3_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL3_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL3_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL3_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL3_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL3_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL3_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL3

USB Receive Control and Status Endpoint 3 Low
address_offset : 0x136 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL3 RXCSRL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL3_RXRDY USB_RXCSRL3_FULL USB_RXCSRL3_OVER USB_RXCSRL3_ERROR USB_RXCSRL3_DATAERR USB_RXCSRL3_NAKTO USB_RXCSRL3_FLUSH USB_RXCSRL3_STALL USB_RXCSRL3_REQPKT USB_RXCSRL3_STALLED USB_RXCSRL3_CLRDT

USB_RXCSRL3_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL3_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL3_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL3_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL3_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL3_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL3_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL3_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL3_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL3_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL3_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH3

USB Receive Control and Status Endpoint 3 High
address_offset : 0x137 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH3 USB0RXCSRH3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH3_DT USB_RXCSRH3_DTWE USB_RXCSRH3_DMAMOD USB_RXCSRH3_PIDERR USB_RXCSRH3_DMAEN USB_RXCSRH3_AUTORQ USB_RXCSRH3_AUTOCL

USB_RXCSRH3_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH3_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH3_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH3_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH3_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH3_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH3_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH3

USB Receive Control and Status Endpoint 3 High
address_offset : 0x137 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH3 RXCSRH3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH3_DT USB_RXCSRH3_DTWE USB_RXCSRH3_DMAMOD USB_RXCSRH3_PIDERR USB_RXCSRH3_DISNYET USB_RXCSRH3_DMAEN USB_RXCSRH3_AUTORQ USB_RXCSRH3_ISO USB_RXCSRH3_AUTOCL

USB_RXCSRH3_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH3_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH3_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH3_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH3_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH3_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH3_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH3_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH3_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT3

USB Receive Byte Count Endpoint 3
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT3 USB0RXCOUNT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT3_COUNT

USB_RXCOUNT3_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT3

USB Receive Byte Count Endpoint 3
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT3 RXCOUNT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT3_COUNT

USB_RXCOUNT3_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE3

USB Host Transmit Configure Type Endpoint 3
address_offset : 0x13A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE3 USB0TXTYPE3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE3_TEP USB_TXTYPE3_PROTO USB_TXTYPE3_SPEED

USB_TXTYPE3_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE3_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE3_PROTO_CTRL

Control

0x1 : USB_TXTYPE3_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE3_PROTO_BULK

Bulk

0x3 : USB_TXTYPE3_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE3_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE3_SPEED_DFLT

Default

0x2 : USB_TXTYPE3_SPEED_FULL

Full

0x3 : USB_TXTYPE3_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE3

USB Host Transmit Configure Type Endpoint 3
address_offset : 0x13A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE3 TXTYPE3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE3_TEP USB_TXTYPE3_PROTO USB_TXTYPE3_SPEED

USB_TXTYPE3_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE3_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE3_PROTO_CTRL

Control

0x1 : USB_TXTYPE3_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE3_PROTO_BULK

Bulk

0x3 : USB_TXTYPE3_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE3_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE3_SPEED_DFLT

Default

0x2 : USB_TXTYPE3_SPEED_FULL

Full

0x3 : USB_TXTYPE3_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL3

USB Host Transmit Interval Endpoint 3
address_offset : 0x13B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL3 USB0TXINTERVAL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL3_TXPOLL

USB_TXINTERVAL3_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL3

USB Host Transmit Interval Endpoint 3
address_offset : 0x13B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL3 TXINTERVAL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL3_TXPOLL USB_TXINTERVAL3_NAKLMT

USB_TXINTERVAL3_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL3_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE3

USB Host Configure Receive Type Endpoint 3
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE3 USB0RXTYPE3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE3_TEP USB_RXTYPE3_PROTO USB_RXTYPE3_SPEED

USB_RXTYPE3_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE3_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE3_PROTO_CTRL

Control

0x1 : USB_RXTYPE3_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE3_PROTO_BULK

Bulk

0x3 : USB_RXTYPE3_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE3_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE3_SPEED_DFLT

Default

0x2 : USB_RXTYPE3_SPEED_FULL

Full

0x3 : USB_RXTYPE3_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE3

USB Host Configure Receive Type Endpoint 3
address_offset : 0x13C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE3 RXTYPE3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE3_TEP USB_RXTYPE3_PROTO USB_RXTYPE3_SPEED

USB_RXTYPE3_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE3_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE3_PROTO_CTRL

Control

0x1 : USB_RXTYPE3_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE3_PROTO_BULK

Bulk

0x3 : USB_RXTYPE3_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE3_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE3_SPEED_DFLT

Default

0x2 : USB_RXTYPE3_SPEED_FULL

Full

0x3 : USB_RXTYPE3_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL3

USB Host Receive Polling Interval Endpoint 3
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL3 USB0RXINTERVAL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL3_TXPOLL

USB_RXINTERVAL3_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL3

USB Host Receive Polling Interval Endpoint 3
address_offset : 0x13D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL3 RXINTERVAL3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL3_TXPOLL USB_RXINTERVAL3_NAKLMT

USB_RXINTERVAL3_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL3_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXMAXP4

USB Maximum Transmit Data Endpoint 4
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP4 USB0TXMAXP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP4_MAXLOAD

USB_TXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP4

USB Maximum Transmit Data Endpoint 4
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP4 TXMAXP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP4_MAXLOAD

USB_TXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL4

USB Transmit Control and Status Endpoint 4 Low
address_offset : 0x142 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL4 USB0TXCSRL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL4_TXRDY USB_TXCSRL4_FIFONE USB_TXCSRL4_ERROR USB_TXCSRL4_FLUSH USB_TXCSRL4_SETUP USB_TXCSRL4_STALLED USB_TXCSRL4_CLRDT USB_TXCSRL4_NAKTO

USB_TXCSRL4_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL4_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL4_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL4_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL4_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL4_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL4_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL4_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL4

USB Transmit Control and Status Endpoint 4 Low
address_offset : 0x142 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL4 TXCSRL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL4_TXRDY USB_TXCSRL4_FIFONE USB_TXCSRL4_ERROR USB_TXCSRL4_UNDRN USB_TXCSRL4_FLUSH USB_TXCSRL4_SETUP USB_TXCSRL4_STALL USB_TXCSRL4_STALLED USB_TXCSRL4_CLRDT USB_TXCSRL4_NAKTO

USB_TXCSRL4_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL4_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL4_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL4_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL4_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL4_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL4_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL4_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL4_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL4_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH4

USB Transmit Control and Status Endpoint 4 High
address_offset : 0x143 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH4 USB0TXCSRH4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH4_DT USB_TXCSRH4_DTWE USB_TXCSRH4_DMAMOD USB_TXCSRH4_FDT USB_TXCSRH4_DMAEN USB_TXCSRH4_MODE USB_TXCSRH4_ISO USB_TXCSRH4_AUTOSET

USB_TXCSRH4_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH4_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH4_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH4_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH4_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH4_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH4_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH4_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH4

USB Transmit Control and Status Endpoint 4 High
address_offset : 0x143 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH4 TXCSRH4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH4_DT USB_TXCSRH4_DTWE USB_TXCSRH4_DMAMOD USB_TXCSRH4_FDT USB_TXCSRH4_DMAEN USB_TXCSRH4_MODE USB_TXCSRH4_ISO USB_TXCSRH4_AUTOSET

USB_TXCSRH4_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH4_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH4_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH4_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH4_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH4_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH4_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH4_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP4

USB Maximum Receive Data Endpoint 4
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP4 USB0RXMAXP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP4_MAXLOAD

USB_RXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP4

USB Maximum Receive Data Endpoint 4
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP4 RXMAXP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP4_MAXLOAD

USB_RXMAXP4_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL4

USB Receive Control and Status Endpoint 4 Low
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL4 USB0RXCSRL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL4_RXRDY USB_RXCSRL4_FULL USB_RXCSRL4_OVER USB_RXCSRL4_DATAERR USB_RXCSRL4_FLUSH USB_RXCSRL4_STALL USB_RXCSRL4_STALLED USB_RXCSRL4_CLRDT

USB_RXCSRL4_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL4_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL4_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL4_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL4_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL4_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL4_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL4_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL4

USB Receive Control and Status Endpoint 4 Low
address_offset : 0x146 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL4 RXCSRL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL4_RXRDY USB_RXCSRL4_FULL USB_RXCSRL4_OVER USB_RXCSRL4_ERROR USB_RXCSRL4_DATAERR USB_RXCSRL4_NAKTO USB_RXCSRL4_FLUSH USB_RXCSRL4_STALL USB_RXCSRL4_REQPKT USB_RXCSRL4_STALLED USB_RXCSRL4_CLRDT

USB_RXCSRL4_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL4_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL4_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL4_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL4_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL4_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL4_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL4_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL4_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL4_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL4_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH4

USB Receive Control and Status Endpoint 4 High
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH4 USB0RXCSRH4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH4_DT USB_RXCSRH4_DTWE USB_RXCSRH4_DMAMOD USB_RXCSRH4_PIDERR USB_RXCSRH4_DMAEN USB_RXCSRH4_AUTORQ USB_RXCSRH4_AUTOCL

USB_RXCSRH4_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH4_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH4_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH4_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH4_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH4_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH4_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH4

USB Receive Control and Status Endpoint 4 High
address_offset : 0x147 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH4 RXCSRH4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH4_DT USB_RXCSRH4_DTWE USB_RXCSRH4_DMAMOD USB_RXCSRH4_PIDERR USB_RXCSRH4_DISNYET USB_RXCSRH4_DMAEN USB_RXCSRH4_AUTORQ USB_RXCSRH4_ISO USB_RXCSRH4_AUTOCL

USB_RXCSRH4_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH4_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH4_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH4_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH4_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH4_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH4_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH4_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH4_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT4

USB Receive Byte Count Endpoint 4
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT4 USB0RXCOUNT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT4_COUNT

USB_RXCOUNT4_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT4

USB Receive Byte Count Endpoint 4
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT4 RXCOUNT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT4_COUNT

USB_RXCOUNT4_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE4

USB Host Transmit Configure Type Endpoint 4
address_offset : 0x14A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE4 USB0TXTYPE4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE4_TEP USB_TXTYPE4_PROTO USB_TXTYPE4_SPEED

USB_TXTYPE4_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE4_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE4_PROTO_CTRL

Control

0x1 : USB_TXTYPE4_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE4_PROTO_BULK

Bulk

0x3 : USB_TXTYPE4_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE4_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE4_SPEED_DFLT

Default

0x2 : USB_TXTYPE4_SPEED_FULL

Full

0x3 : USB_TXTYPE4_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE4

USB Host Transmit Configure Type Endpoint 4
address_offset : 0x14A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE4 TXTYPE4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE4_TEP USB_TXTYPE4_PROTO USB_TXTYPE4_SPEED

USB_TXTYPE4_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE4_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE4_PROTO_CTRL

Control

0x1 : USB_TXTYPE4_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE4_PROTO_BULK

Bulk

0x3 : USB_TXTYPE4_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE4_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE4_SPEED_DFLT

Default

0x2 : USB_TXTYPE4_SPEED_FULL

Full

0x3 : USB_TXTYPE4_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL4

USB Host Transmit Interval Endpoint 4
address_offset : 0x14B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL4 USB0TXINTERVAL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL4_TXPOLL

USB_TXINTERVAL4_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL4

USB Host Transmit Interval Endpoint 4
address_offset : 0x14B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL4 TXINTERVAL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL4_TXPOLL USB_TXINTERVAL4_NAKLMT

USB_TXINTERVAL4_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL4_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE4

USB Host Configure Receive Type Endpoint 4
address_offset : 0x14C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE4 USB0RXTYPE4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE4_TEP USB_RXTYPE4_PROTO USB_RXTYPE4_SPEED

USB_RXTYPE4_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE4_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE4_PROTO_CTRL

Control

0x1 : USB_RXTYPE4_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE4_PROTO_BULK

Bulk

0x3 : USB_RXTYPE4_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE4_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE4_SPEED_DFLT

Default

0x2 : USB_RXTYPE4_SPEED_FULL

Full

0x3 : USB_RXTYPE4_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE4

USB Host Configure Receive Type Endpoint 4
address_offset : 0x14C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE4 RXTYPE4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE4_TEP USB_RXTYPE4_PROTO USB_RXTYPE4_SPEED

USB_RXTYPE4_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE4_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE4_PROTO_CTRL

Control

0x1 : USB_RXTYPE4_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE4_PROTO_BULK

Bulk

0x3 : USB_RXTYPE4_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE4_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE4_SPEED_DFLT

Default

0x2 : USB_RXTYPE4_SPEED_FULL

Full

0x3 : USB_RXTYPE4_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL4

USB Host Receive Polling Interval Endpoint 4
address_offset : 0x14D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL4 USB0RXINTERVAL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL4_TXPOLL

USB_RXINTERVAL4_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL4

USB Host Receive Polling Interval Endpoint 4
address_offset : 0x14D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL4 RXINTERVAL4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL4_TXPOLL USB_RXINTERVAL4_NAKLMT

USB_RXINTERVAL4_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL4_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXMAXP5

USB Maximum Transmit Data Endpoint 5
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP5 USB0TXMAXP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP5_MAXLOAD

USB_TXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP5

USB Maximum Transmit Data Endpoint 5
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP5 TXMAXP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP5_MAXLOAD

USB_TXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL5

USB Transmit Control and Status Endpoint 5 Low
address_offset : 0x152 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL5 USB0TXCSRL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL5_TXRDY USB_TXCSRL5_FIFONE USB_TXCSRL5_ERROR USB_TXCSRL5_FLUSH USB_TXCSRL5_SETUP USB_TXCSRL5_STALLED USB_TXCSRL5_CLRDT USB_TXCSRL5_NAKTO

USB_TXCSRL5_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL5_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL5_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL5_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL5_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL5_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL5_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL5_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL5

USB Transmit Control and Status Endpoint 5 Low
address_offset : 0x152 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL5 TXCSRL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL5_TXRDY USB_TXCSRL5_FIFONE USB_TXCSRL5_ERROR USB_TXCSRL5_UNDRN USB_TXCSRL5_FLUSH USB_TXCSRL5_SETUP USB_TXCSRL5_STALL USB_TXCSRL5_STALLED USB_TXCSRL5_CLRDT USB_TXCSRL5_NAKTO

USB_TXCSRL5_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL5_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL5_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL5_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL5_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL5_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL5_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL5_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL5_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL5_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH5

USB Transmit Control and Status Endpoint 5 High
address_offset : 0x153 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH5 USB0TXCSRH5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH5_DT USB_TXCSRH5_DTWE USB_TXCSRH5_DMAMOD USB_TXCSRH5_FDT USB_TXCSRH5_DMAEN USB_TXCSRH5_MODE USB_TXCSRH5_ISO USB_TXCSRH5_AUTOSET

USB_TXCSRH5_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH5_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH5_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH5_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH5_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH5_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH5_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH5_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH5

USB Transmit Control and Status Endpoint 5 High
address_offset : 0x153 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH5 TXCSRH5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH5_DT USB_TXCSRH5_DTWE USB_TXCSRH5_DMAMOD USB_TXCSRH5_FDT USB_TXCSRH5_DMAEN USB_TXCSRH5_MODE USB_TXCSRH5_ISO USB_TXCSRH5_AUTOSET

USB_TXCSRH5_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH5_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH5_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH5_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH5_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH5_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH5_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH5_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP5

USB Maximum Receive Data Endpoint 5
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP5 USB0RXMAXP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP5_MAXLOAD

USB_RXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP5

USB Maximum Receive Data Endpoint 5
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP5 RXMAXP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP5_MAXLOAD

USB_RXMAXP5_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL5

USB Receive Control and Status Endpoint 5 Low
address_offset : 0x156 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL5 USB0RXCSRL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL5_RXRDY USB_RXCSRL5_FULL USB_RXCSRL5_OVER USB_RXCSRL5_DATAERR USB_RXCSRL5_FLUSH USB_RXCSRL5_STALL USB_RXCSRL5_STALLED USB_RXCSRL5_CLRDT

USB_RXCSRL5_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL5_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL5_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL5_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL5_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL5_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL5_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL5_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL5

USB Receive Control and Status Endpoint 5 Low
address_offset : 0x156 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL5 RXCSRL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL5_RXRDY USB_RXCSRL5_FULL USB_RXCSRL5_OVER USB_RXCSRL5_ERROR USB_RXCSRL5_DATAERR USB_RXCSRL5_NAKTO USB_RXCSRL5_FLUSH USB_RXCSRL5_STALL USB_RXCSRL5_REQPKT USB_RXCSRL5_STALLED USB_RXCSRL5_CLRDT

USB_RXCSRL5_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL5_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL5_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL5_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL5_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL5_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL5_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL5_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL5_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL5_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL5_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH5

USB Receive Control and Status Endpoint 5 High
address_offset : 0x157 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH5 USB0RXCSRH5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH5_DT USB_RXCSRH5_DTWE USB_RXCSRH5_DMAMOD USB_RXCSRH5_PIDERR USB_RXCSRH5_DMAEN USB_RXCSRH5_AUTORQ USB_RXCSRH5_AUTOCL

USB_RXCSRH5_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH5_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH5_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH5_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH5_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH5_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH5_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH5

USB Receive Control and Status Endpoint 5 High
address_offset : 0x157 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH5 RXCSRH5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH5_DT USB_RXCSRH5_DTWE USB_RXCSRH5_DMAMOD USB_RXCSRH5_PIDERR USB_RXCSRH5_DISNYET USB_RXCSRH5_DMAEN USB_RXCSRH5_AUTORQ USB_RXCSRH5_ISO USB_RXCSRH5_AUTOCL

USB_RXCSRH5_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH5_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH5_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH5_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH5_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH5_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH5_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH5_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH5_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT5

USB Receive Byte Count Endpoint 5
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT5 USB0RXCOUNT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT5_COUNT

USB_RXCOUNT5_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT5

USB Receive Byte Count Endpoint 5
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT5 RXCOUNT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT5_COUNT

USB_RXCOUNT5_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE5

USB Host Transmit Configure Type Endpoint 5
address_offset : 0x15A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE5 USB0TXTYPE5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE5_TEP USB_TXTYPE5_PROTO USB_TXTYPE5_SPEED

USB_TXTYPE5_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE5_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE5_PROTO_CTRL

Control

0x1 : USB_TXTYPE5_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE5_PROTO_BULK

Bulk

0x3 : USB_TXTYPE5_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE5_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE5_SPEED_DFLT

Default

0x2 : USB_TXTYPE5_SPEED_FULL

Full

0x3 : USB_TXTYPE5_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE5

USB Host Transmit Configure Type Endpoint 5
address_offset : 0x15A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE5 TXTYPE5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE5_TEP USB_TXTYPE5_PROTO USB_TXTYPE5_SPEED

USB_TXTYPE5_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE5_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE5_PROTO_CTRL

Control

0x1 : USB_TXTYPE5_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE5_PROTO_BULK

Bulk

0x3 : USB_TXTYPE5_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE5_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE5_SPEED_DFLT

Default

0x2 : USB_TXTYPE5_SPEED_FULL

Full

0x3 : USB_TXTYPE5_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL5

USB Host Transmit Interval Endpoint 5
address_offset : 0x15B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL5 USB0TXINTERVAL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL5_TXPOLL

USB_TXINTERVAL5_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL5

USB Host Transmit Interval Endpoint 5
address_offset : 0x15B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL5 TXINTERVAL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL5_TXPOLL USB_TXINTERVAL5_NAKLMT

USB_TXINTERVAL5_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL5_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE5

USB Host Configure Receive Type Endpoint 5
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE5 USB0RXTYPE5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE5_TEP USB_RXTYPE5_PROTO USB_RXTYPE5_SPEED

USB_RXTYPE5_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE5_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE5_PROTO_CTRL

Control

0x1 : USB_RXTYPE5_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE5_PROTO_BULK

Bulk

0x3 : USB_RXTYPE5_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE5_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE5_SPEED_DFLT

Default

0x2 : USB_RXTYPE5_SPEED_FULL

Full

0x3 : USB_RXTYPE5_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE5

USB Host Configure Receive Type Endpoint 5
address_offset : 0x15C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE5 RXTYPE5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE5_TEP USB_RXTYPE5_PROTO USB_RXTYPE5_SPEED

USB_RXTYPE5_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE5_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE5_PROTO_CTRL

Control

0x1 : USB_RXTYPE5_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE5_PROTO_BULK

Bulk

0x3 : USB_RXTYPE5_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE5_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE5_SPEED_DFLT

Default

0x2 : USB_RXTYPE5_SPEED_FULL

Full

0x3 : USB_RXTYPE5_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL5

USB Host Receive Polling Interval Endpoint 5
address_offset : 0x15D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL5 USB0RXINTERVAL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL5_TXPOLL

USB_RXINTERVAL5_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL5

USB Host Receive Polling Interval Endpoint 5
address_offset : 0x15D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL5 RXINTERVAL5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL5_TXPOLL USB_RXINTERVAL5_NAKLMT

USB_RXINTERVAL5_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL5_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXMAXP6

USB Maximum Transmit Data Endpoint 6
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP6 USB0TXMAXP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP6_MAXLOAD

USB_TXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP6

USB Maximum Transmit Data Endpoint 6
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP6 TXMAXP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP6_MAXLOAD

USB_TXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL6

USB Transmit Control and Status Endpoint 6 Low
address_offset : 0x162 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL6 USB0TXCSRL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL6_TXRDY USB_TXCSRL6_FIFONE USB_TXCSRL6_ERROR USB_TXCSRL6_FLUSH USB_TXCSRL6_SETUP USB_TXCSRL6_STALLED USB_TXCSRL6_CLRDT USB_TXCSRL6_NAKTO

USB_TXCSRL6_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL6_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL6_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL6_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL6_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL6_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL6_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL6_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL6

USB Transmit Control and Status Endpoint 6 Low
address_offset : 0x162 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL6 TXCSRL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL6_TXRDY USB_TXCSRL6_FIFONE USB_TXCSRL6_ERROR USB_TXCSRL6_UNDRN USB_TXCSRL6_FLUSH USB_TXCSRL6_SETUP USB_TXCSRL6_STALL USB_TXCSRL6_STALLED USB_TXCSRL6_CLRDT USB_TXCSRL6_NAKTO

USB_TXCSRL6_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL6_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL6_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL6_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL6_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL6_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL6_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL6_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL6_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL6_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH6

USB Transmit Control and Status Endpoint 6 High
address_offset : 0x163 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH6 USB0TXCSRH6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH6_DT USB_TXCSRH6_DTWE USB_TXCSRH6_DMAMOD USB_TXCSRH6_FDT USB_TXCSRH6_DMAEN USB_TXCSRH6_MODE USB_TXCSRH6_ISO USB_TXCSRH6_AUTOSET

USB_TXCSRH6_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH6_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH6_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH6_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH6_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH6_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH6_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH6_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH6

USB Transmit Control and Status Endpoint 6 High
address_offset : 0x163 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH6 TXCSRH6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH6_DT USB_TXCSRH6_DTWE USB_TXCSRH6_DMAMOD USB_TXCSRH6_FDT USB_TXCSRH6_DMAEN USB_TXCSRH6_MODE USB_TXCSRH6_ISO USB_TXCSRH6_AUTOSET

USB_TXCSRH6_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH6_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH6_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH6_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH6_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH6_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH6_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH6_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP6

USB Maximum Receive Data Endpoint 6
address_offset : 0x164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP6 USB0RXMAXP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP6_MAXLOAD

USB_RXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP6

USB Maximum Receive Data Endpoint 6
address_offset : 0x164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP6 RXMAXP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP6_MAXLOAD

USB_RXMAXP6_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL6

USB Receive Control and Status Endpoint 6 Low
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL6 USB0RXCSRL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL6_RXRDY USB_RXCSRL6_FULL USB_RXCSRL6_OVER USB_RXCSRL6_DATAERR USB_RXCSRL6_FLUSH USB_RXCSRL6_STALL USB_RXCSRL6_STALLED USB_RXCSRL6_CLRDT

USB_RXCSRL6_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL6_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL6_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL6_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL6_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL6_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL6_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL6_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL6

USB Receive Control and Status Endpoint 6 Low
address_offset : 0x166 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL6 RXCSRL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL6_RXRDY USB_RXCSRL6_FULL USB_RXCSRL6_OVER USB_RXCSRL6_ERROR USB_RXCSRL6_DATAERR USB_RXCSRL6_NAKTO USB_RXCSRL6_FLUSH USB_RXCSRL6_STALL USB_RXCSRL6_REQPKT USB_RXCSRL6_STALLED USB_RXCSRL6_CLRDT

USB_RXCSRL6_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL6_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL6_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL6_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL6_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL6_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL6_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL6_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL6_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL6_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL6_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH6

USB Receive Control and Status Endpoint 6 High
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH6 USB0RXCSRH6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH6_DT USB_RXCSRH6_DTWE USB_RXCSRH6_DMAMOD USB_RXCSRH6_PIDERR USB_RXCSRH6_DMAEN USB_RXCSRH6_AUTORQ USB_RXCSRH6_AUTOCL

USB_RXCSRH6_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH6_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH6_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH6_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH6_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH6_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH6_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH6

USB Receive Control and Status Endpoint 6 High
address_offset : 0x167 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH6 RXCSRH6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH6_DT USB_RXCSRH6_DTWE USB_RXCSRH6_DMAMOD USB_RXCSRH6_PIDERR USB_RXCSRH6_DISNYET USB_RXCSRH6_DMAEN USB_RXCSRH6_AUTORQ USB_RXCSRH6_ISO USB_RXCSRH6_AUTOCL

USB_RXCSRH6_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH6_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH6_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH6_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH6_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH6_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH6_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH6_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH6_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT6

USB Receive Byte Count Endpoint 6
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT6 USB0RXCOUNT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT6_COUNT

USB_RXCOUNT6_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT6

USB Receive Byte Count Endpoint 6
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT6 RXCOUNT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT6_COUNT

USB_RXCOUNT6_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE6

USB Host Transmit Configure Type Endpoint 6
address_offset : 0x16A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE6 USB0TXTYPE6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE6_TEP USB_TXTYPE6_PROTO USB_TXTYPE6_SPEED

USB_TXTYPE6_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE6_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE6_PROTO_CTRL

Control

0x1 : USB_TXTYPE6_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE6_PROTO_BULK

Bulk

0x3 : USB_TXTYPE6_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE6_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE6_SPEED_DFLT

Default

0x2 : USB_TXTYPE6_SPEED_FULL

Full

0x3 : USB_TXTYPE6_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE6

USB Host Transmit Configure Type Endpoint 6
address_offset : 0x16A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE6 TXTYPE6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE6_TEP USB_TXTYPE6_PROTO USB_TXTYPE6_SPEED

USB_TXTYPE6_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE6_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE6_PROTO_CTRL

Control

0x1 : USB_TXTYPE6_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE6_PROTO_BULK

Bulk

0x3 : USB_TXTYPE6_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE6_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE6_SPEED_DFLT

Default

0x2 : USB_TXTYPE6_SPEED_FULL

Full

0x3 : USB_TXTYPE6_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL6

USB Host Transmit Interval Endpoint 6
address_offset : 0x16B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL6 USB0TXINTERVAL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL6_TXPOLL

USB_TXINTERVAL6_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL6

USB Host Transmit Interval Endpoint 6
address_offset : 0x16B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL6 TXINTERVAL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL6_TXPOLL USB_TXINTERVAL6_NAKLMT

USB_TXINTERVAL6_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL6_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE6

USB Host Configure Receive Type Endpoint 6
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE6 USB0RXTYPE6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE6_TEP USB_RXTYPE6_PROTO USB_RXTYPE6_SPEED

USB_RXTYPE6_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE6_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE6_PROTO_CTRL

Control

0x1 : USB_RXTYPE6_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE6_PROTO_BULK

Bulk

0x3 : USB_RXTYPE6_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE6_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE6_SPEED_DFLT

Default

0x2 : USB_RXTYPE6_SPEED_FULL

Full

0x3 : USB_RXTYPE6_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE6

USB Host Configure Receive Type Endpoint 6
address_offset : 0x16C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE6 RXTYPE6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE6_TEP USB_RXTYPE6_PROTO USB_RXTYPE6_SPEED

USB_RXTYPE6_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE6_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE6_PROTO_CTRL

Control

0x1 : USB_RXTYPE6_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE6_PROTO_BULK

Bulk

0x3 : USB_RXTYPE6_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE6_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE6_SPEED_DFLT

Default

0x2 : USB_RXTYPE6_SPEED_FULL

Full

0x3 : USB_RXTYPE6_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL6

USB Host Receive Polling Interval Endpoint 6
address_offset : 0x16D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL6 USB0RXINTERVAL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL6_TXPOLL

USB_RXINTERVAL6_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL6

USB Host Receive Polling Interval Endpoint 6
address_offset : 0x16D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL6 RXINTERVAL6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL6_TXPOLL USB_RXINTERVAL6_NAKLMT

USB_RXINTERVAL6_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL6_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXMAXP7

USB Maximum Transmit Data Endpoint 7
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXMAXP7 USB0TXMAXP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP7_MAXLOAD

USB_TXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


TXMAXP7

USB Maximum Transmit Data Endpoint 7
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXMAXP7 TXMAXP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXMAXP7_MAXLOAD

USB_TXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0TXCSRL7

USB Transmit Control and Status Endpoint 7 Low
address_offset : 0x172 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRL7 USB0TXCSRL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL7_TXRDY USB_TXCSRL7_FIFONE USB_TXCSRL7_ERROR USB_TXCSRL7_FLUSH USB_TXCSRL7_SETUP USB_TXCSRL7_STALLED USB_TXCSRL7_CLRDT USB_TXCSRL7_NAKTO

USB_TXCSRL7_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL7_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL7_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL7_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL7_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL7_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL7_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL7_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


TXCSRL7

USB Transmit Control and Status Endpoint 7 Low
address_offset : 0x172 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRL7 TXCSRL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRL7_TXRDY USB_TXCSRL7_FIFONE USB_TXCSRL7_ERROR USB_TXCSRL7_UNDRN USB_TXCSRL7_FLUSH USB_TXCSRL7_SETUP USB_TXCSRL7_STALL USB_TXCSRL7_STALLED USB_TXCSRL7_CLRDT USB_TXCSRL7_NAKTO

USB_TXCSRL7_TXRDY : Transmit Packet Ready
bits : 0 - 0 (1 bit)

USB_TXCSRL7_FIFONE : FIFO Not Empty
bits : 1 - 2 (2 bit)

USB_TXCSRL7_ERROR : Error
bits : 2 - 4 (3 bit)

USB_TXCSRL7_UNDRN : Underrun
bits : 2 - 4 (3 bit)

USB_TXCSRL7_FLUSH : Flush FIFO
bits : 3 - 6 (4 bit)

USB_TXCSRL7_SETUP : Setup Packet
bits : 4 - 8 (5 bit)

USB_TXCSRL7_STALL : Send STALL
bits : 4 - 8 (5 bit)

USB_TXCSRL7_STALLED : Endpoint Stalled
bits : 5 - 10 (6 bit)

USB_TXCSRL7_CLRDT : Clear Data Toggle
bits : 6 - 12 (7 bit)

USB_TXCSRL7_NAKTO : NAK Timeout
bits : 7 - 14 (8 bit)


USB0TXCSRH7

USB Transmit Control and Status Endpoint 7 High
address_offset : 0x173 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXCSRH7 USB0TXCSRH7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH7_DT USB_TXCSRH7_DTWE USB_TXCSRH7_DMAMOD USB_TXCSRH7_FDT USB_TXCSRH7_DMAEN USB_TXCSRH7_MODE USB_TXCSRH7_ISO USB_TXCSRH7_AUTOSET

USB_TXCSRH7_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH7_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH7_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH7_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH7_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH7_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH7_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH7_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


TXCSRH7

USB Transmit Control and Status Endpoint 7 High
address_offset : 0x173 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXCSRH7 TXCSRH7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXCSRH7_DT USB_TXCSRH7_DTWE USB_TXCSRH7_DMAMOD USB_TXCSRH7_FDT USB_TXCSRH7_DMAEN USB_TXCSRH7_MODE USB_TXCSRH7_ISO USB_TXCSRH7_AUTOSET

USB_TXCSRH7_DT : Data Toggle
bits : 0 - 0 (1 bit)

USB_TXCSRH7_DTWE : Data Toggle Write Enable
bits : 1 - 2 (2 bit)

USB_TXCSRH7_DMAMOD : DMA Request Mode
bits : 2 - 4 (3 bit)

USB_TXCSRH7_FDT : Force Data Toggle
bits : 3 - 6 (4 bit)

USB_TXCSRH7_DMAEN : DMA Request Enable
bits : 4 - 8 (5 bit)

USB_TXCSRH7_MODE : Mode
bits : 5 - 10 (6 bit)

USB_TXCSRH7_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_TXCSRH7_AUTOSET : Auto Set
bits : 7 - 14 (8 bit)


USB0RXMAXP7

USB Maximum Receive Data Endpoint 7
address_offset : 0x174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXMAXP7 USB0RXMAXP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP7_MAXLOAD

USB_RXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


RXMAXP7

USB Maximum Receive Data Endpoint 7
address_offset : 0x174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXMAXP7 RXMAXP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXMAXP7_MAXLOAD

USB_RXMAXP7_MAXLOAD : Maximum Payload
bits : 0 - 10 (11 bit)


USB0RXCSRL7

USB Receive Control and Status Endpoint 7 Low
address_offset : 0x176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRL7 USB0RXCSRL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL7_RXRDY USB_RXCSRL7_FULL USB_RXCSRL7_OVER USB_RXCSRL7_DATAERR USB_RXCSRL7_FLUSH USB_RXCSRL7_STALL USB_RXCSRL7_STALLED USB_RXCSRL7_CLRDT

USB_RXCSRL7_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL7_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL7_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL7_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL7_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL7_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL7_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL7_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


RXCSRL7

USB Receive Control and Status Endpoint 7 Low
address_offset : 0x176 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRL7 RXCSRL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRL7_RXRDY USB_RXCSRL7_FULL USB_RXCSRL7_OVER USB_RXCSRL7_ERROR USB_RXCSRL7_DATAERR USB_RXCSRL7_NAKTO USB_RXCSRL7_FLUSH USB_RXCSRL7_STALL USB_RXCSRL7_REQPKT USB_RXCSRL7_STALLED USB_RXCSRL7_CLRDT

USB_RXCSRL7_RXRDY : Receive Packet Ready
bits : 0 - 0 (1 bit)

USB_RXCSRL7_FULL : FIFO Full
bits : 1 - 2 (2 bit)

USB_RXCSRL7_OVER : Overrun
bits : 2 - 4 (3 bit)

USB_RXCSRL7_ERROR : Error
bits : 2 - 4 (3 bit)

USB_RXCSRL7_DATAERR : Data Error
bits : 3 - 6 (4 bit)

USB_RXCSRL7_NAKTO : NAK Timeout
bits : 3 - 6 (4 bit)

USB_RXCSRL7_FLUSH : Flush FIFO
bits : 4 - 8 (5 bit)

USB_RXCSRL7_STALL : Send STALL
bits : 5 - 10 (6 bit)

USB_RXCSRL7_REQPKT : Request Packet
bits : 5 - 10 (6 bit)

USB_RXCSRL7_STALLED : Endpoint Stalled
bits : 6 - 12 (7 bit)

USB_RXCSRL7_CLRDT : Clear Data Toggle
bits : 7 - 14 (8 bit)


USB0RXCSRH7

USB Receive Control and Status Endpoint 7 High
address_offset : 0x177 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCSRH7 USB0RXCSRH7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH7_DT USB_RXCSRH7_DTWE USB_RXCSRH7_DMAMOD USB_RXCSRH7_PIDERR USB_RXCSRH7_DMAEN USB_RXCSRH7_AUTORQ USB_RXCSRH7_AUTOCL

USB_RXCSRH7_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH7_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH7_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH7_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH7_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH7_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH7_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


RXCSRH7

USB Receive Control and Status Endpoint 7 High
address_offset : 0x177 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCSRH7 RXCSRH7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXCSRH7_DT USB_RXCSRH7_DTWE USB_RXCSRH7_DMAMOD USB_RXCSRH7_PIDERR USB_RXCSRH7_DISNYET USB_RXCSRH7_DMAEN USB_RXCSRH7_AUTORQ USB_RXCSRH7_ISO USB_RXCSRH7_AUTOCL

USB_RXCSRH7_DT : Data Toggle
bits : 1 - 2 (2 bit)

USB_RXCSRH7_DTWE : Data Toggle Write Enable
bits : 2 - 4 (3 bit)

USB_RXCSRH7_DMAMOD : DMA Request Mode
bits : 3 - 6 (4 bit)

USB_RXCSRH7_PIDERR : PID Error
bits : 4 - 8 (5 bit)

USB_RXCSRH7_DISNYET : Disable NYET
bits : 4 - 8 (5 bit)

USB_RXCSRH7_DMAEN : DMA Request Enable
bits : 5 - 10 (6 bit)

USB_RXCSRH7_AUTORQ : Auto Request
bits : 6 - 12 (7 bit)

USB_RXCSRH7_ISO : Isochronous Transfers
bits : 6 - 12 (7 bit)

USB_RXCSRH7_AUTOCL : Auto Clear
bits : 7 - 14 (8 bit)


USB0RXCOUNT7

USB Receive Byte Count Endpoint 7
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXCOUNT7 USB0RXCOUNT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT7_COUNT

USB_RXCOUNT7_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


RXCOUNT7

USB Receive Byte Count Endpoint 7
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXCOUNT7 RXCOUNT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXCOUNT7_COUNT

USB_RXCOUNT7_COUNT : Receive Packet Count
bits : 0 - 12 (13 bit)


USB0TXTYPE7

USB Host Transmit Configure Type Endpoint 7
address_offset : 0x17A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXTYPE7 USB0TXTYPE7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE7_TEP USB_TXTYPE7_PROTO USB_TXTYPE7_SPEED

USB_TXTYPE7_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE7_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE7_PROTO_CTRL

Control

0x1 : USB_TXTYPE7_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE7_PROTO_BULK

Bulk

0x3 : USB_TXTYPE7_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE7_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE7_SPEED_DFLT

Default

0x2 : USB_TXTYPE7_SPEED_FULL

Full

0x3 : USB_TXTYPE7_SPEED_LOW

Low

End of enumeration elements list.


TXTYPE7

USB Host Transmit Configure Type Endpoint 7
address_offset : 0x17A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXTYPE7 TXTYPE7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXTYPE7_TEP USB_TXTYPE7_PROTO USB_TXTYPE7_SPEED

USB_TXTYPE7_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_TXTYPE7_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_TXTYPE7_PROTO_CTRL

Control

0x1 : USB_TXTYPE7_PROTO_ISOC

Isochronous

0x2 : USB_TXTYPE7_PROTO_BULK

Bulk

0x3 : USB_TXTYPE7_PROTO_INT

Interrupt

End of enumeration elements list.

USB_TXTYPE7_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_TXTYPE7_SPEED_DFLT

Default

0x2 : USB_TXTYPE7_SPEED_FULL

Full

0x3 : USB_TXTYPE7_SPEED_LOW

Low

End of enumeration elements list.


USB0TXINTERVAL7

USB Host Transmit Interval Endpoint 7
address_offset : 0x17B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXINTERVAL7 USB0TXINTERVAL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL7_TXPOLL

USB_TXINTERVAL7_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)


TXINTERVAL7

USB Host Transmit Interval Endpoint 7
address_offset : 0x17B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXINTERVAL7 TXINTERVAL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXINTERVAL7_TXPOLL USB_TXINTERVAL7_NAKLMT

USB_TXINTERVAL7_TXPOLL : TX Polling
bits : 0 - 7 (8 bit)

USB_TXINTERVAL7_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0RXTYPE7

USB Host Configure Receive Type Endpoint 7
address_offset : 0x17C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXTYPE7 USB0RXTYPE7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE7_TEP USB_RXTYPE7_PROTO USB_RXTYPE7_SPEED

USB_RXTYPE7_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE7_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE7_PROTO_CTRL

Control

0x1 : USB_RXTYPE7_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE7_PROTO_BULK

Bulk

0x3 : USB_RXTYPE7_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE7_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE7_SPEED_DFLT

Default

0x2 : USB_RXTYPE7_SPEED_FULL

Full

0x3 : USB_RXTYPE7_SPEED_LOW

Low

End of enumeration elements list.


RXTYPE7

USB Host Configure Receive Type Endpoint 7
address_offset : 0x17C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXTYPE7 RXTYPE7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXTYPE7_TEP USB_RXTYPE7_PROTO USB_RXTYPE7_SPEED

USB_RXTYPE7_TEP : Target Endpoint Number
bits : 0 - 3 (4 bit)

USB_RXTYPE7_PROTO : Protocol
bits : 4 - 9 (6 bit)

Enumeration:

0x0 : USB_RXTYPE7_PROTO_CTRL

Control

0x1 : USB_RXTYPE7_PROTO_ISOC

Isochronous

0x2 : USB_RXTYPE7_PROTO_BULK

Bulk

0x3 : USB_RXTYPE7_PROTO_INT

Interrupt

End of enumeration elements list.

USB_RXTYPE7_SPEED : Operating Speed
bits : 6 - 13 (8 bit)

Enumeration:

0x0 : USB_RXTYPE7_SPEED_DFLT

Default

0x2 : USB_RXTYPE7_SPEED_FULL

Full

0x3 : USB_RXTYPE7_SPEED_LOW

Low

End of enumeration elements list.


USB0RXINTERVAL7

USB Host Receive Polling Interval Endpoint 7
address_offset : 0x17D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXINTERVAL7 USB0RXINTERVAL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL7_TXPOLL

USB_RXINTERVAL7_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)


RXINTERVAL7

USB Host Receive Polling Interval Endpoint 7
address_offset : 0x17D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXINTERVAL7 RXINTERVAL7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXINTERVAL7_TXPOLL USB_RXINTERVAL7_NAKLMT

USB_RXINTERVAL7_TXPOLL : RX Polling
bits : 0 - 7 (8 bit)

USB_RXINTERVAL7_NAKLMT : NAK Limit
bits : 0 - 7 (8 bit)


USB0TXIS

USB Transmit Interrupt Status
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXIS USB0TXIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXIS_EP0 USB_TXIS_EP1 USB_TXIS_EP2 USB_TXIS_EP3 USB_TXIS_EP4 USB_TXIS_EP5 USB_TXIS_EP6 USB_TXIS_EP7

USB_TXIS_EP0 : TX and RX Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)

USB_TXIS_EP1 : TX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)

USB_TXIS_EP2 : TX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)

USB_TXIS_EP3 : TX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)

USB_TXIS_EP4 : TX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)

USB_TXIS_EP5 : TX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)

USB_TXIS_EP6 : TX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)

USB_TXIS_EP7 : TX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)


TXIS

USB Transmit Interrupt Status
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXIS TXIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXIS_EP0 USB_TXIS_EP1 USB_TXIS_EP2 USB_TXIS_EP3 USB_TXIS_EP4 USB_TXIS_EP5 USB_TXIS_EP6 USB_TXIS_EP7

USB_TXIS_EP0 : TX and RX Endpoint 0 Interrupt
bits : 0 - 0 (1 bit)

USB_TXIS_EP1 : TX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)

USB_TXIS_EP2 : TX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)

USB_TXIS_EP3 : TX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)

USB_TXIS_EP4 : TX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)

USB_TXIS_EP5 : TX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)

USB_TXIS_EP6 : TX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)

USB_TXIS_EP7 : TX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)


USB0FIFO0

USB FIFO Endpoint 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO0 USB0FIFO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO0_EPDATA

USB_FIFO0_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO0

USB FIFO Endpoint 0
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO0 FIFO0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO0_EPDATA

USB_FIFO0_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0FIFO1

USB FIFO Endpoint 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO1 USB0FIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO1_EPDATA

USB_FIFO1_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO1

USB FIFO Endpoint 1
address_offset : 0x24 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO1 FIFO1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO1_EPDATA

USB_FIFO1_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0FIFO2

USB FIFO Endpoint 2
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO2 USB0FIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO2_EPDATA

USB_FIFO2_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO2

USB FIFO Endpoint 2
address_offset : 0x28 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO2 FIFO2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO2_EPDATA

USB_FIFO2_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0FIFO3

USB FIFO Endpoint 3
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO3 USB0FIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO3_EPDATA

USB_FIFO3_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO3

USB FIFO Endpoint 3
address_offset : 0x2C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO3 FIFO3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO3_EPDATA

USB_FIFO3_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0FIFO4

USB FIFO Endpoint 4
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO4 USB0FIFO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO4_EPDATA

USB_FIFO4_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO4

USB FIFO Endpoint 4
address_offset : 0x30 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO4 FIFO4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO4_EPDATA

USB_FIFO4_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0RQPKTCOUNT1

USB Request Packet Count in Block Transfer Endpoint 1
address_offset : 0x304 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT1 USB0RQPKTCOUNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT1

USB_RQPKTCOUNT1 : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT1

USB Request Packet Count in Block Transfer Endpoint 1
address_offset : 0x304 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT1 RQPKTCOUNT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT1

USB_RQPKTCOUNT1 : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0RQPKTCOUNT2

USB Request Packet Count in Block Transfer Endpoint 2
address_offset : 0x308 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT2 USB0RQPKTCOUNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT2

USB_RQPKTCOUNT2 : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT2

USB Request Packet Count in Block Transfer Endpoint 2
address_offset : 0x308 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT2 RQPKTCOUNT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT2

USB_RQPKTCOUNT2 : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0RQPKTCOUNT3

USB Request Packet Count in Block Transfer Endpoint 3
address_offset : 0x30C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT3 USB0RQPKTCOUNT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT3

USB_RQPKTCOUNT3 : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT3

USB Request Packet Count in Block Transfer Endpoint 3
address_offset : 0x30C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT3 RQPKTCOUNT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT3

USB_RQPKTCOUNT3 : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0RQPKTCOUNT4

USB Request Packet Count in Block Transfer Endpoint 4
address_offset : 0x310 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT4 USB0RQPKTCOUNT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT4_COUNT

USB_RQPKTCOUNT4_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT4

USB Request Packet Count in Block Transfer Endpoint 4
address_offset : 0x310 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT4 RQPKTCOUNT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT4_COUNT

USB_RQPKTCOUNT4_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0RQPKTCOUNT5

USB Request Packet Count in Block Transfer Endpoint 5
address_offset : 0x314 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT5 USB0RQPKTCOUNT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT5_COUNT

USB_RQPKTCOUNT5_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT5

USB Request Packet Count in Block Transfer Endpoint 5
address_offset : 0x314 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT5 RQPKTCOUNT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT5_COUNT

USB_RQPKTCOUNT5_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0RQPKTCOUNT6

USB Request Packet Count in Block Transfer Endpoint 6
address_offset : 0x318 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT6 USB0RQPKTCOUNT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT6_COUNT

USB_RQPKTCOUNT6_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT6

USB Request Packet Count in Block Transfer Endpoint 6
address_offset : 0x318 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT6 RQPKTCOUNT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT6_COUNT

USB_RQPKTCOUNT6_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0RQPKTCOUNT7

USB Request Packet Count in Block Transfer Endpoint 7
address_offset : 0x31C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RQPKTCOUNT7 USB0RQPKTCOUNT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT7_COUNT

USB_RQPKTCOUNT7_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


RQPKTCOUNT7

USB Request Packet Count in Block Transfer Endpoint 7
address_offset : 0x31C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RQPKTCOUNT7 RQPKTCOUNT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RQPKTCOUNT7_COUNT

USB_RQPKTCOUNT7_COUNT : Block Transfer Packet Count
bits : 0 - 15 (16 bit)


USB0FIFO5

USB FIFO Endpoint 5
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO5 USB0FIFO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO5_EPDATA

USB_FIFO5_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO5

USB FIFO Endpoint 5
address_offset : 0x34 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO5 FIFO5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO5_EPDATA

USB_FIFO5_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0RXDPKTBUFDIS

USB Receive Double Packet Buffer Disable
address_offset : 0x340 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXDPKTBUFDIS USB0RXDPKTBUFDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXDPKTBUFDIS_EP1 USB_RXDPKTBUFDIS_EP2 USB_RXDPKTBUFDIS_EP3 USB_RXDPKTBUFDIS_EP4 USB_RXDPKTBUFDIS_EP5 USB_RXDPKTBUFDIS_EP6 USB_RXDPKTBUFDIS_EP7

USB_RXDPKTBUFDIS_EP1 : EP1 RX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)

USB_RXDPKTBUFDIS_EP2 : EP2 RX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)

USB_RXDPKTBUFDIS_EP3 : EP3 RX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)

USB_RXDPKTBUFDIS_EP4 : EP4 RX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)

USB_RXDPKTBUFDIS_EP5 : EP5 RX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)

USB_RXDPKTBUFDIS_EP6 : EP6 RX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)

USB_RXDPKTBUFDIS_EP7 : EP7 RX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)


RXDPKTBUFDIS

USB Receive Double Packet Buffer Disable
address_offset : 0x340 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXDPKTBUFDIS RXDPKTBUFDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXDPKTBUFDIS_EP1 USB_RXDPKTBUFDIS_EP2 USB_RXDPKTBUFDIS_EP3 USB_RXDPKTBUFDIS_EP4 USB_RXDPKTBUFDIS_EP5 USB_RXDPKTBUFDIS_EP6 USB_RXDPKTBUFDIS_EP7

USB_RXDPKTBUFDIS_EP1 : EP1 RX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)

USB_RXDPKTBUFDIS_EP2 : EP2 RX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)

USB_RXDPKTBUFDIS_EP3 : EP3 RX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)

USB_RXDPKTBUFDIS_EP4 : EP4 RX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)

USB_RXDPKTBUFDIS_EP5 : EP5 RX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)

USB_RXDPKTBUFDIS_EP6 : EP6 RX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)

USB_RXDPKTBUFDIS_EP7 : EP7 RX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)


USB0TXDPKTBUFDIS

USB Transmit Double Packet Buffer Disable
address_offset : 0x342 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXDPKTBUFDIS USB0TXDPKTBUFDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXDPKTBUFDIS_EP1 USB_TXDPKTBUFDIS_EP2 USB_TXDPKTBUFDIS_EP3 USB_TXDPKTBUFDIS_EP4 USB_TXDPKTBUFDIS_EP5 USB_TXDPKTBUFDIS_EP6 USB_TXDPKTBUFDIS_EP7

USB_TXDPKTBUFDIS_EP1 : EP1 TX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)

USB_TXDPKTBUFDIS_EP2 : EP2 TX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)

USB_TXDPKTBUFDIS_EP3 : EP3 TX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)

USB_TXDPKTBUFDIS_EP4 : EP4 TX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)

USB_TXDPKTBUFDIS_EP5 : EP5 TX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)

USB_TXDPKTBUFDIS_EP6 : EP6 TX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)

USB_TXDPKTBUFDIS_EP7 : EP7 TX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)


TXDPKTBUFDIS

USB Transmit Double Packet Buffer Disable
address_offset : 0x342 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXDPKTBUFDIS TXDPKTBUFDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXDPKTBUFDIS_EP1 USB_TXDPKTBUFDIS_EP2 USB_TXDPKTBUFDIS_EP3 USB_TXDPKTBUFDIS_EP4 USB_TXDPKTBUFDIS_EP5 USB_TXDPKTBUFDIS_EP6 USB_TXDPKTBUFDIS_EP7

USB_TXDPKTBUFDIS_EP1 : EP1 TX Double-Packet Buffer Disable
bits : 1 - 2 (2 bit)

USB_TXDPKTBUFDIS_EP2 : EP2 TX Double-Packet Buffer Disable
bits : 2 - 4 (3 bit)

USB_TXDPKTBUFDIS_EP3 : EP3 TX Double-Packet Buffer Disable
bits : 3 - 6 (4 bit)

USB_TXDPKTBUFDIS_EP4 : EP4 TX Double-Packet Buffer Disable
bits : 4 - 8 (5 bit)

USB_TXDPKTBUFDIS_EP5 : EP5 TX Double-Packet Buffer Disable
bits : 5 - 10 (6 bit)

USB_TXDPKTBUFDIS_EP6 : EP6 TX Double-Packet Buffer Disable
bits : 6 - 12 (7 bit)

USB_TXDPKTBUFDIS_EP7 : EP7 TX Double-Packet Buffer Disable
bits : 7 - 14 (8 bit)


USB0FIFO6

USB FIFO Endpoint 6
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO6 USB0FIFO6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO6_EPDATA

USB_FIFO6_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO6

USB FIFO Endpoint 6
address_offset : 0x38 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO6 FIFO6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO6_EPDATA

USB_FIFO6_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0FIFO7

USB FIFO Endpoint 7
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FIFO7 USB0FIFO7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO7_EPDATA

USB_FIFO7_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


FIFO7

USB FIFO Endpoint 7
address_offset : 0x3C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO7 FIFO7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FIFO7_EPDATA

USB_FIFO7_EPDATA : Endpoint Data
bits : 0 - 31 (32 bit)


USB0RXIS

USB Receive Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXIS USB0RXIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXIS_EP1 USB_RXIS_EP2 USB_RXIS_EP3 USB_RXIS_EP4 USB_RXIS_EP5 USB_RXIS_EP6 USB_RXIS_EP7

USB_RXIS_EP1 : RX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)

USB_RXIS_EP2 : RX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)

USB_RXIS_EP3 : RX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)

USB_RXIS_EP4 : RX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)

USB_RXIS_EP5 : RX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)

USB_RXIS_EP6 : RX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)

USB_RXIS_EP7 : RX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)


RXIS

USB Receive Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXIS RXIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXIS_EP1 USB_RXIS_EP2 USB_RXIS_EP3 USB_RXIS_EP4 USB_RXIS_EP5 USB_RXIS_EP6 USB_RXIS_EP7

USB_RXIS_EP1 : RX Endpoint 1 Interrupt
bits : 1 - 2 (2 bit)

USB_RXIS_EP2 : RX Endpoint 2 Interrupt
bits : 2 - 4 (3 bit)

USB_RXIS_EP3 : RX Endpoint 3 Interrupt
bits : 3 - 6 (4 bit)

USB_RXIS_EP4 : RX Endpoint 4 Interrupt
bits : 4 - 8 (5 bit)

USB_RXIS_EP5 : RX Endpoint 5 Interrupt
bits : 5 - 10 (6 bit)

USB_RXIS_EP6 : RX Endpoint 6 Interrupt
bits : 6 - 12 (7 bit)

USB_RXIS_EP7 : RX Endpoint 7 Interrupt
bits : 7 - 14 (8 bit)


USB0EPC

USB External Power Control
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0EPC USB0EPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPC_EPEN USB_EPC_EPENDE USB_EPC_PFLTEN USB_EPC_PFLTSEN_HIGH USB_EPC_PFLTAEN USB_EPC_PFLTACT

USB_EPC_EPEN : External Power Supply Enable Configuration
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : USB_EPC_EPEN_LOW

Power Enable Active Low

0x1 : USB_EPC_EPEN_HIGH

Power Enable Active High

0x2 : USB_EPC_EPEN_VBLOW

Power Enable High if VBUS Low (OTG only)

0x3 : USB_EPC_EPEN_VBHIGH

Power Enable High if VBUS High (OTG only)

End of enumeration elements list.

USB_EPC_EPENDE : EPEN Drive Enable
bits : 2 - 4 (3 bit)

USB_EPC_PFLTEN : Power Fault Input Enable
bits : 4 - 8 (5 bit)

USB_EPC_PFLTSEN_HIGH : Power Fault Sense
bits : 5 - 10 (6 bit)

USB_EPC_PFLTAEN : Power Fault Action Enable
bits : 6 - 12 (7 bit)

USB_EPC_PFLTACT : Power Fault Action
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : USB_EPC_PFLTACT_UNCHG

Unchanged

0x1 : USB_EPC_PFLTACT_TRIS

Tristate

0x2 : USB_EPC_PFLTACT_LOW

Low

0x3 : USB_EPC_PFLTACT_HIGH

High

End of enumeration elements list.


EPC

USB External Power Control
address_offset : 0x400 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPC EPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPC_EPEN USB_EPC_EPENDE USB_EPC_PFLTEN USB_EPC_PFLTSEN_HIGH USB_EPC_PFLTAEN USB_EPC_PFLTACT

USB_EPC_EPEN : External Power Supply Enable Configuration
bits : 0 - 1 (2 bit)

Enumeration:

0x0 : USB_EPC_EPEN_LOW

Power Enable Active Low

0x1 : USB_EPC_EPEN_HIGH

Power Enable Active High

0x2 : USB_EPC_EPEN_VBLOW

Power Enable High if VBUS Low (OTG only)

0x3 : USB_EPC_EPEN_VBHIGH

Power Enable High if VBUS High (OTG only)

End of enumeration elements list.

USB_EPC_EPENDE : EPEN Drive Enable
bits : 2 - 4 (3 bit)

USB_EPC_PFLTEN : Power Fault Input Enable
bits : 4 - 8 (5 bit)

USB_EPC_PFLTSEN_HIGH : Power Fault Sense
bits : 5 - 10 (6 bit)

USB_EPC_PFLTAEN : Power Fault Action Enable
bits : 6 - 12 (7 bit)

USB_EPC_PFLTACT : Power Fault Action
bits : 8 - 17 (10 bit)

Enumeration:

0x0 : USB_EPC_PFLTACT_UNCHG

Unchanged

0x1 : USB_EPC_PFLTACT_TRIS

Tristate

0x2 : USB_EPC_PFLTACT_LOW

Low

0x3 : USB_EPC_PFLTACT_HIGH

High

End of enumeration elements list.


USB0EPCRIS

USB External Power Control Raw Interrupt Status
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0EPCRIS USB0EPCRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPCRIS_PF

USB_EPCRIS_PF : USB Power Fault Interrupt Status
bits : 0 - 0 (1 bit)


EPCRIS

USB External Power Control Raw Interrupt Status
address_offset : 0x404 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCRIS EPCRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPCRIS_PF

USB_EPCRIS_PF : USB Power Fault Interrupt Status
bits : 0 - 0 (1 bit)


USB0EPCIM

USB External Power Control Interrupt Mask
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0EPCIM USB0EPCIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPCIM_PF

USB_EPCIM_PF : USB Power Fault Interrupt Mask
bits : 0 - 0 (1 bit)


EPCIM

USB External Power Control Interrupt Mask
address_offset : 0x408 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCIM EPCIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPCIM_PF

USB_EPCIM_PF : USB Power Fault Interrupt Mask
bits : 0 - 0 (1 bit)


USB0EPCISC

USB External Power Control Interrupt Status and Clear
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0EPCISC USB0EPCISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPCISC_PF

USB_EPCISC_PF : USB Power Fault Interrupt Status and Clear
bits : 0 - 0 (1 bit)


EPCISC

USB External Power Control Interrupt Status and Clear
address_offset : 0x40C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPCISC EPCISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_EPCISC_PF

USB_EPCISC_PF : USB Power Fault Interrupt Status and Clear
bits : 0 - 0 (1 bit)


USB0DRRIS

USB Device RESUME Raw Interrupt Status
address_offset : 0x410 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0DRRIS USB0DRRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRRIS_RESUME

USB_DRRIS_RESUME : RESUME Interrupt Status
bits : 0 - 0 (1 bit)


DRRIS

USB Device RESUME Raw Interrupt Status
address_offset : 0x410 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRRIS DRRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRRIS_RESUME

USB_DRRIS_RESUME : RESUME Interrupt Status
bits : 0 - 0 (1 bit)


USB0DRIM

USB Device RESUME Interrupt Mask
address_offset : 0x414 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0DRIM USB0DRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRIM_RESUME

USB_DRIM_RESUME : RESUME Interrupt Mask
bits : 0 - 0 (1 bit)


DRIM

USB Device RESUME Interrupt Mask
address_offset : 0x414 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DRIM DRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRIM_RESUME

USB_DRIM_RESUME : RESUME Interrupt Mask
bits : 0 - 0 (1 bit)


USB0DRISC

USB Device RESUME Interrupt Status and Clear
address_offset : 0x418 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

USB0DRISC USB0DRISC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRISC_RESUME

USB_DRISC_RESUME : RESUME Interrupt Status and Clear
bits : 0 - 0 (1 bit)
access : write-only


DRISC

USB Device RESUME Interrupt Status and Clear
address_offset : 0x418 Bytes (0x0)
size : -1 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DRISC DRISC write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DRISC_RESUME

USB_DRISC_RESUME : RESUME Interrupt Status and Clear
bits : 0 - 0 (1 bit)
access : write-only


USB0GPCS

USB General-Purpose Control and Status
address_offset : 0x41C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0GPCS USB0GPCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_GPCS_DEVMOD USB_GPCS_DEVMODOTG

USB_GPCS_DEVMOD : Device Mode
bits : 0 - 0 (1 bit)

USB_GPCS_DEVMODOTG : Enable Device Mode
bits : 1 - 2 (2 bit)


GPCS

USB General-Purpose Control and Status
address_offset : 0x41C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPCS GPCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_GPCS_DEVMOD USB_GPCS_DEVMODOTG

USB_GPCS_DEVMOD : Device Mode
bits : 0 - 0 (1 bit)

USB_GPCS_DEVMODOTG : Enable Device Mode
bits : 1 - 2 (2 bit)


USB0VDC

USB VBUS Droop Control
address_offset : 0x430 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0VDC USB0VDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDC_VBDEN

USB_VDC_VBDEN : VBUS Droop Enable
bits : 0 - 0 (1 bit)


VDC

USB VBUS Droop Control
address_offset : 0x430 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDC VDC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDC_VBDEN

USB_VDC_VBDEN : VBUS Droop Enable
bits : 0 - 0 (1 bit)


USB0VDCRIS

USB VBUS Droop Control Raw Interrupt Status
address_offset : 0x434 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0VDCRIS USB0VDCRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDCRIS_VD

USB_VDCRIS_VD : VBUS Droop Raw Interrupt Status
bits : 0 - 0 (1 bit)


VDCRIS

USB VBUS Droop Control Raw Interrupt Status
address_offset : 0x434 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDCRIS VDCRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDCRIS_VD

USB_VDCRIS_VD : VBUS Droop Raw Interrupt Status
bits : 0 - 0 (1 bit)


USB0VDCIM

USB VBUS Droop Control Interrupt Mask
address_offset : 0x438 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0VDCIM USB0VDCIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDCIM_VD

USB_VDCIM_VD : VBUS Droop Interrupt Mask
bits : 0 - 0 (1 bit)


VDCIM

USB VBUS Droop Control Interrupt Mask
address_offset : 0x438 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDCIM VDCIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDCIM_VD

USB_VDCIM_VD : VBUS Droop Interrupt Mask
bits : 0 - 0 (1 bit)


USB0VDCISC

USB VBUS Droop Control Interrupt Status and Clear
address_offset : 0x43C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0VDCISC USB0VDCISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDCISC_VD

USB_VDCISC_VD : VBUS Droop Interrupt Status and Clear
bits : 0 - 0 (1 bit)


VDCISC

USB VBUS Droop Control Interrupt Status and Clear
address_offset : 0x43C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDCISC VDCISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_VDCISC_VD

USB_VDCISC_VD : VBUS Droop Interrupt Status and Clear
bits : 0 - 0 (1 bit)


USB0IDVRIS

USB ID Valid Detect Raw Interrupt Status
address_offset : 0x444 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0IDVRIS USB0IDVRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_IDVRIS_ID

USB_IDVRIS_ID : ID Valid Detect Raw Interrupt Status
bits : 0 - 0 (1 bit)


IDVRIS

USB ID Valid Detect Raw Interrupt Status
address_offset : 0x444 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDVRIS IDVRIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_IDVRIS_ID

USB_IDVRIS_ID : ID Valid Detect Raw Interrupt Status
bits : 0 - 0 (1 bit)


USB0IDVIM

USB ID Valid Detect Interrupt Mask
address_offset : 0x448 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0IDVIM USB0IDVIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_IDVIM_ID

USB_IDVIM_ID : ID Valid Detect Interrupt Mask
bits : 0 - 0 (1 bit)


IDVIM

USB ID Valid Detect Interrupt Mask
address_offset : 0x448 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDVIM IDVIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_IDVIM_ID

USB_IDVIM_ID : ID Valid Detect Interrupt Mask
bits : 0 - 0 (1 bit)


USB0IDVISC

USB ID Valid Detect Interrupt Status and Clear
address_offset : 0x44C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0IDVISC USB0IDVISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_IDVISC_ID

USB_IDVISC_ID : ID Valid Detect Interrupt Status and Clear
bits : 0 - 0 (1 bit)


IDVISC

USB ID Valid Detect Interrupt Status and Clear
address_offset : 0x44C Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDVISC IDVISC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_IDVISC_ID

USB_IDVISC_ID : ID Valid Detect Interrupt Status and Clear
bits : 0 - 0 (1 bit)


USB0DMASEL

USB DMA Select
address_offset : 0x450 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0DMASEL USB0DMASEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DMASEL_DMAARX USB_DMASEL_DMAATX USB_DMASEL_DMABRX USB_DMASEL_DMABTX USB_DMASEL_DMACRX USB_DMASEL_DMACTX

USB_DMASEL_DMAARX : DMA A RX Select
bits : 0 - 3 (4 bit)

USB_DMASEL_DMAATX : DMA A TX Select
bits : 4 - 11 (8 bit)

USB_DMASEL_DMABRX : DMA B RX Select
bits : 8 - 19 (12 bit)

USB_DMASEL_DMABTX : DMA B TX Select
bits : 12 - 27 (16 bit)

USB_DMASEL_DMACRX : DMA C RX Select
bits : 16 - 35 (20 bit)

USB_DMASEL_DMACTX : DMA C TX Select
bits : 20 - 43 (24 bit)


DMASEL

USB DMA Select
address_offset : 0x450 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMASEL DMASEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_DMASEL_DMAARX USB_DMASEL_DMAATX USB_DMASEL_DMABRX USB_DMASEL_DMABTX USB_DMASEL_DMACRX USB_DMASEL_DMACTX

USB_DMASEL_DMAARX : DMA A RX Select
bits : 0 - 3 (4 bit)

USB_DMASEL_DMAATX : DMA A TX Select
bits : 4 - 11 (8 bit)

USB_DMASEL_DMABRX : DMA B RX Select
bits : 8 - 19 (12 bit)

USB_DMASEL_DMABTX : DMA B TX Select
bits : 12 - 27 (16 bit)

USB_DMASEL_DMACRX : DMA C RX Select
bits : 16 - 35 (20 bit)

USB_DMASEL_DMACTX : DMA C TX Select
bits : 20 - 43 (24 bit)


USB0TXIE

USB Transmit Interrupt Enable
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXIE USB0TXIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXIE_EP0 USB_TXIE_EP1 USB_TXIE_EP2 USB_TXIE_EP3 USB_TXIE_EP4 USB_TXIE_EP5 USB_TXIE_EP6 USB_TXIE_EP7

USB_TXIE_EP0 : TX and RX Endpoint 0 Interrupt Enable
bits : 0 - 0 (1 bit)

USB_TXIE_EP1 : TX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)

USB_TXIE_EP2 : TX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)

USB_TXIE_EP3 : TX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)

USB_TXIE_EP4 : TX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)

USB_TXIE_EP5 : TX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)

USB_TXIE_EP6 : TX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)

USB_TXIE_EP7 : TX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)


TXIE

USB Transmit Interrupt Enable
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXIE TXIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXIE_EP0 USB_TXIE_EP1 USB_TXIE_EP2 USB_TXIE_EP3 USB_TXIE_EP4 USB_TXIE_EP5 USB_TXIE_EP6 USB_TXIE_EP7

USB_TXIE_EP0 : TX and RX Endpoint 0 Interrupt Enable
bits : 0 - 0 (1 bit)

USB_TXIE_EP1 : TX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)

USB_TXIE_EP2 : TX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)

USB_TXIE_EP3 : TX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)

USB_TXIE_EP4 : TX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)

USB_TXIE_EP5 : TX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)

USB_TXIE_EP6 : TX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)

USB_TXIE_EP7 : TX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)


USB0DEVCTL

USB Device Control
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0DEVCTL USB0DEVCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_DEVCTL_SESSION USB_DEVCTL_HOSTREQ USB_DEVCTL_HOST USB_DEVCTL_VBUS USB_DEVCTL_LSDEV USB_DEVCTL_FSDEV USB_DEVCTL_DEV

USB_DEVCTL_SESSION : Session Start/End (OTG only)
bits : 0 - 0 (1 bit)

USB_DEVCTL_HOSTREQ : Host Request (OTG only)
bits : 1 - 2 (2 bit)

USB_DEVCTL_HOST : Host Mode
bits : 2 - 4 (3 bit)

USB_DEVCTL_VBUS : VBUS Level (OTG only)
bits : 3 - 7 (5 bit)

Enumeration:

0x0 : USB_DEVCTL_VBUS_NONE

Below SessionEnd

0x1 : USB_DEVCTL_VBUS_SEND

Above SessionEnd, below AValid

0x2 : USB_DEVCTL_VBUS_AVALID

Above AValid, below VBUSValid

0x3 : USB_DEVCTL_VBUS_VALID

Above VBUSValid

End of enumeration elements list.

USB_DEVCTL_LSDEV : Low-Speed Device Detected
bits : 5 - 10 (6 bit)

USB_DEVCTL_FSDEV : Full-Speed Device Detected
bits : 6 - 12 (7 bit)

USB_DEVCTL_DEV : Device Mode (OTG only)
bits : 7 - 14 (8 bit)


DEVCTL

USB Device Control
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVCTL DEVCTL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_DEVCTL_SESSION USB_DEVCTL_HOSTREQ USB_DEVCTL_HOST USB_DEVCTL_VBUS USB_DEVCTL_LSDEV USB_DEVCTL_FSDEV USB_DEVCTL_DEV

USB_DEVCTL_SESSION : Session Start/End (OTG only)
bits : 0 - 0 (1 bit)

USB_DEVCTL_HOSTREQ : Host Request (OTG only)
bits : 1 - 2 (2 bit)

USB_DEVCTL_HOST : Host Mode
bits : 2 - 4 (3 bit)

USB_DEVCTL_VBUS : VBUS Level (OTG only)
bits : 3 - 7 (5 bit)

Enumeration:

0x0 : USB_DEVCTL_VBUS_NONE

Below SessionEnd

0x1 : USB_DEVCTL_VBUS_SEND

Above SessionEnd, below AValid

0x2 : USB_DEVCTL_VBUS_AVALID

Above AValid, below VBUSValid

0x3 : USB_DEVCTL_VBUS_VALID

Above VBUSValid

End of enumeration elements list.

USB_DEVCTL_LSDEV : Low-Speed Device Detected
bits : 5 - 10 (6 bit)

USB_DEVCTL_FSDEV : Full-Speed Device Detected
bits : 6 - 12 (7 bit)

USB_DEVCTL_DEV : Device Mode (OTG only)
bits : 7 - 14 (8 bit)


USB0TXFIFOSZ

USB Transmit Dynamic FIFO Sizing
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFIFOSZ USB0TXFIFOSZ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFIFOSZ_SIZE USB_TXFIFOSZ_DPB

USB_TXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : USB_TXFIFOSZ_SIZE_8

8

0x1 : USB_TXFIFOSZ_SIZE_16

16

0x2 : USB_TXFIFOSZ_SIZE_32

32

0x3 : USB_TXFIFOSZ_SIZE_64

64

0x4 : USB_TXFIFOSZ_SIZE_128

128

0x5 : USB_TXFIFOSZ_SIZE_256

256

0x6 : USB_TXFIFOSZ_SIZE_512

512

0x7 : USB_TXFIFOSZ_SIZE_1024

1024

0x8 : USB_TXFIFOSZ_SIZE_2048

2048

End of enumeration elements list.

USB_TXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)


TXFIFOSZ

USB Transmit Dynamic FIFO Sizing
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFOSZ TXFIFOSZ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFIFOSZ_SIZE USB_TXFIFOSZ_DPB

USB_TXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : USB_TXFIFOSZ_SIZE_8

8

0x1 : USB_TXFIFOSZ_SIZE_16

16

0x2 : USB_TXFIFOSZ_SIZE_32

32

0x3 : USB_TXFIFOSZ_SIZE_64

64

0x4 : USB_TXFIFOSZ_SIZE_128

128

0x5 : USB_TXFIFOSZ_SIZE_256

256

0x6 : USB_TXFIFOSZ_SIZE_512

512

0x7 : USB_TXFIFOSZ_SIZE_1024

1024

0x8 : USB_TXFIFOSZ_SIZE_2048

2048

End of enumeration elements list.

USB_TXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)


USB0RXFIFOSZ

USB Receive Dynamic FIFO Sizing
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFIFOSZ USB0RXFIFOSZ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFIFOSZ_SIZE USB_RXFIFOSZ_DPB

USB_RXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : USB_RXFIFOSZ_SIZE_8

8

0x1 : USB_RXFIFOSZ_SIZE_16

16

0x2 : USB_RXFIFOSZ_SIZE_32

32

0x3 : USB_RXFIFOSZ_SIZE_64

64

0x4 : USB_RXFIFOSZ_SIZE_128

128

0x5 : USB_RXFIFOSZ_SIZE_256

256

0x6 : USB_RXFIFOSZ_SIZE_512

512

0x7 : USB_RXFIFOSZ_SIZE_1024

1024

0x8 : USB_RXFIFOSZ_SIZE_2048

2048

End of enumeration elements list.

USB_RXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)


RXFIFOSZ

USB Receive Dynamic FIFO Sizing
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFOSZ RXFIFOSZ read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFIFOSZ_SIZE USB_RXFIFOSZ_DPB

USB_RXFIFOSZ_SIZE : Max Packet Size
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : USB_RXFIFOSZ_SIZE_8

8

0x1 : USB_RXFIFOSZ_SIZE_16

16

0x2 : USB_RXFIFOSZ_SIZE_32

32

0x3 : USB_RXFIFOSZ_SIZE_64

64

0x4 : USB_RXFIFOSZ_SIZE_128

128

0x5 : USB_RXFIFOSZ_SIZE_256

256

0x6 : USB_RXFIFOSZ_SIZE_512

512

0x7 : USB_RXFIFOSZ_SIZE_1024

1024

0x8 : USB_RXFIFOSZ_SIZE_2048

2048

End of enumeration elements list.

USB_RXFIFOSZ_DPB : Double Packet Buffer Support
bits : 4 - 8 (5 bit)


USB0TXFIFOADD

USB Transmit FIFO Start Address
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFIFOADD USB0TXFIFOADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXFIFOADD_ADDR

USB_TXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)


TXFIFOADD

USB Transmit FIFO Start Address
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFIFOADD TXFIFOADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_TXFIFOADD_ADDR

USB_TXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)


USB0RXFIFOADD

USB Receive FIFO Start Address
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFIFOADD USB0RXFIFOADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXFIFOADD_ADDR

USB_RXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)


RXFIFOADD

USB Receive FIFO Start Address
address_offset : 0x66 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFOADD RXFIFOADD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXFIFOADD_ADDR

USB_RXFIFOADD_ADDR : Transmit/Receive Start Address
bits : 0 - 8 (9 bit)


USB0CONTIM

USB Connect Timing
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0CONTIM USB0CONTIM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_CONTIM_WTID USB_CONTIM_WTCON

USB_CONTIM_WTID : Wait ID
bits : 0 - 3 (4 bit)

USB_CONTIM_WTCON : Connect Wait
bits : 4 - 11 (8 bit)


CONTIM

USB Connect Timing
address_offset : 0x7A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONTIM CONTIM read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_CONTIM_WTID USB_CONTIM_WTCON

USB_CONTIM_WTID : Wait ID
bits : 0 - 3 (4 bit)

USB_CONTIM_WTCON : Connect Wait
bits : 4 - 11 (8 bit)


USB0VPLEN

USB OTG VBUS Pulse Timing
address_offset : 0x7B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0VPLEN USB0VPLEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_VPLEN_VPLEN

USB_VPLEN_VPLEN : VBUS Pulse Length
bits : 0 - 7 (8 bit)


VPLEN

USB OTG VBUS Pulse Timing
address_offset : 0x7B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VPLEN VPLEN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_VPLEN_VPLEN

USB_VPLEN_VPLEN : VBUS Pulse Length
bits : 0 - 7 (8 bit)


USB0FSEOF

USB Full-Speed Last Transaction to End of Frame Timing
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FSEOF USB0FSEOF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_FSEOF_FSEOFG

USB_FSEOF_FSEOFG : Full-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)


FSEOF

USB Full-Speed Last Transaction to End of Frame Timing
address_offset : 0x7D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FSEOF FSEOF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_FSEOF_FSEOFG

USB_FSEOF_FSEOFG : Full-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)


USB0LSEOF

USB Low-Speed Last Transaction to End of Frame Timing
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0LSEOF USB0LSEOF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_LSEOF_LSEOFG

USB_LSEOF_LSEOFG : Low-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)


LSEOF

USB Low-Speed Last Transaction to End of Frame Timing
address_offset : 0x7E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSEOF LSEOF read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_LSEOF_LSEOFG

USB_LSEOF_LSEOFG : Low-Speed End-of-Frame Gap
bits : 0 - 7 (8 bit)


USB0RXIE

USB Receive Interrupt Enable
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXIE USB0RXIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXIE_EP1 USB_RXIE_EP2 USB_RXIE_EP3 USB_RXIE_EP4 USB_RXIE_EP5 USB_RXIE_EP6 USB_RXIE_EP7

USB_RXIE_EP1 : RX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)

USB_RXIE_EP2 : RX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)

USB_RXIE_EP3 : RX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)

USB_RXIE_EP4 : RX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)

USB_RXIE_EP5 : RX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)

USB_RXIE_EP6 : RX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)

USB_RXIE_EP7 : RX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)


RXIE

USB Receive Interrupt Enable
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXIE RXIE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_RXIE_EP1 USB_RXIE_EP2 USB_RXIE_EP3 USB_RXIE_EP4 USB_RXIE_EP5 USB_RXIE_EP6 USB_RXIE_EP7

USB_RXIE_EP1 : RX Endpoint 1 Interrupt Enable
bits : 1 - 2 (2 bit)

USB_RXIE_EP2 : RX Endpoint 2 Interrupt Enable
bits : 2 - 4 (3 bit)

USB_RXIE_EP3 : RX Endpoint 3 Interrupt Enable
bits : 3 - 6 (4 bit)

USB_RXIE_EP4 : RX Endpoint 4 Interrupt Enable
bits : 4 - 8 (5 bit)

USB_RXIE_EP5 : RX Endpoint 5 Interrupt Enable
bits : 5 - 10 (6 bit)

USB_RXIE_EP6 : RX Endpoint 6 Interrupt Enable
bits : 6 - 12 (7 bit)

USB_RXIE_EP7 : RX Endpoint 7 Interrupt Enable
bits : 7 - 14 (8 bit)


USB0TXFUNCADDR0

USB Transmit Functional Address Endpoint 0
address_offset : 0x80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR0 USB0TXFUNCADDR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR0_ADDR

USB_TXFUNCADDR0_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR0

USB Transmit Functional Address Endpoint 0
address_offset : 0x80 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR0 TXFUNCADDR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR0_ADDR

USB_TXFUNCADDR0_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR0

USB Transmit Hub Address Endpoint 0
address_offset : 0x82 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR0 USB0TXHUBADDR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR0_ADDR

USB_TXHUBADDR0_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR0

USB Transmit Hub Address Endpoint 0
address_offset : 0x82 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR0 TXHUBADDR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR0_ADDR

USB_TXHUBADDR0_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT0

USB Transmit Hub Port Endpoint 0
address_offset : 0x83 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT0 USB0TXHUBPORT0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT0_PORT

USB_TXHUBPORT0_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT0

USB Transmit Hub Port Endpoint 0
address_offset : 0x83 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT0 TXHUBPORT0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT0_PORT

USB_TXHUBPORT0_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0TXFUNCADDR1

USB Transmit Functional Address Endpoint 1
address_offset : 0x88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR1 USB0TXFUNCADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR1_ADDR

USB_TXFUNCADDR1_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR1

USB Transmit Functional Address Endpoint 1
address_offset : 0x88 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR1 TXFUNCADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR1_ADDR

USB_TXFUNCADDR1_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR1

USB Transmit Hub Address Endpoint 1
address_offset : 0x8A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR1 USB0TXHUBADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR1_ADDR

USB_TXHUBADDR1_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR1

USB Transmit Hub Address Endpoint 1
address_offset : 0x8A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR1 TXHUBADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR1_ADDR

USB_TXHUBADDR1_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT1

USB Transmit Hub Port Endpoint 1
address_offset : 0x8B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT1 USB0TXHUBPORT1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT1_PORT

USB_TXHUBPORT1_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT1

USB Transmit Hub Port Endpoint 1
address_offset : 0x8B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT1 TXHUBPORT1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT1_PORT

USB_TXHUBPORT1_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR1

USB Receive Functional Address Endpoint 1
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR1 USB0RXFUNCADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR1_ADDR

USB_RXFUNCADDR1_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR1

USB Receive Functional Address Endpoint 1
address_offset : 0x8C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR1 RXFUNCADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR1_ADDR

USB_RXFUNCADDR1_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR1

USB Receive Hub Address Endpoint 1
address_offset : 0x8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR1 USB0RXHUBADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR1_ADDR

USB_RXHUBADDR1_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR1

USB Receive Hub Address Endpoint 1
address_offset : 0x8E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR1 RXHUBADDR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR1_ADDR

USB_RXHUBADDR1_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT1

USB Receive Hub Port Endpoint 1
address_offset : 0x8F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT1 USB0RXHUBPORT1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT1_PORT

USB_RXHUBPORT1_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT1

USB Receive Hub Port Endpoint 1
address_offset : 0x8F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT1 RXHUBPORT1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT1_PORT

USB_RXHUBPORT1_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0TXFUNCADDR2

USB Transmit Functional Address Endpoint 2
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR2 USB0TXFUNCADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR2_ADDR

USB_TXFUNCADDR2_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR2

USB Transmit Functional Address Endpoint 2
address_offset : 0x90 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR2 TXFUNCADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR2_ADDR

USB_TXFUNCADDR2_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR2

USB Transmit Hub Address Endpoint 2
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR2 USB0TXHUBADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR2_ADDR

USB_TXHUBADDR2_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR2

USB Transmit Hub Address Endpoint 2
address_offset : 0x92 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR2 TXHUBADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR2_ADDR

USB_TXHUBADDR2_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT2

USB Transmit Hub Port Endpoint 2
address_offset : 0x93 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT2 USB0TXHUBPORT2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT2_PORT

USB_TXHUBPORT2_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT2

USB Transmit Hub Port Endpoint 2
address_offset : 0x93 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT2 TXHUBPORT2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT2_PORT

USB_TXHUBPORT2_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR2

USB Receive Functional Address Endpoint 2
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR2 USB0RXFUNCADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR2_ADDR

USB_RXFUNCADDR2_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR2

USB Receive Functional Address Endpoint 2
address_offset : 0x94 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR2 RXFUNCADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR2_ADDR

USB_RXFUNCADDR2_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR2

USB Receive Hub Address Endpoint 2
address_offset : 0x96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR2 USB0RXHUBADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR2_ADDR

USB_RXHUBADDR2_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR2

USB Receive Hub Address Endpoint 2
address_offset : 0x96 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR2 RXHUBADDR2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR2_ADDR

USB_RXHUBADDR2_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT2

USB Receive Hub Port Endpoint 2
address_offset : 0x97 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT2 USB0RXHUBPORT2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT2_PORT

USB_RXHUBPORT2_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT2

USB Receive Hub Port Endpoint 2
address_offset : 0x97 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT2 RXHUBPORT2 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT2_PORT

USB_RXHUBPORT2_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0TXFUNCADDR3

USB Transmit Functional Address Endpoint 3
address_offset : 0x98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR3 USB0TXFUNCADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR3_ADDR

USB_TXFUNCADDR3_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR3

USB Transmit Functional Address Endpoint 3
address_offset : 0x98 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR3 TXFUNCADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR3_ADDR

USB_TXFUNCADDR3_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR3

USB Transmit Hub Address Endpoint 3
address_offset : 0x9A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR3 USB0TXHUBADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR3_ADDR

USB_TXHUBADDR3_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR3

USB Transmit Hub Address Endpoint 3
address_offset : 0x9A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR3 TXHUBADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR3_ADDR

USB_TXHUBADDR3_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT3

USB Transmit Hub Port Endpoint 3
address_offset : 0x9B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT3 USB0TXHUBPORT3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT3_PORT

USB_TXHUBPORT3_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT3

USB Transmit Hub Port Endpoint 3
address_offset : 0x9B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT3 TXHUBPORT3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT3_PORT

USB_TXHUBPORT3_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR3

USB Receive Functional Address Endpoint 3
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR3 USB0RXFUNCADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR3_ADDR

USB_RXFUNCADDR3_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR3

USB Receive Functional Address Endpoint 3
address_offset : 0x9C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR3 RXFUNCADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR3_ADDR

USB_RXFUNCADDR3_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR3

USB Receive Hub Address Endpoint 3
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR3 USB0RXHUBADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR3_ADDR

USB_RXHUBADDR3_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR3

USB Receive Hub Address Endpoint 3
address_offset : 0x9E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR3 RXHUBADDR3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR3_ADDR

USB_RXHUBADDR3_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT3

USB Receive Hub Port Endpoint 3
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT3 USB0RXHUBPORT3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT3_PORT

USB_RXHUBPORT3_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT3

USB Receive Hub Port Endpoint 3
address_offset : 0x9F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT3 RXHUBPORT3 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT3_PORT

USB_RXHUBPORT3_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0IS

USB General Interrupt Status
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0IS USB0IS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_IS_SUSPEND USB_IS_RESUME USB_IS_BABBLE USB_IS_SOF USB_IS_CONN USB_IS_DISCON USB_IS_SESREQ USB_IS_VBUSERR

USB_IS_SUSPEND : SUSPEND Signaling Detected
bits : 0 - 0 (1 bit)

USB_IS_RESUME : RESUME Signaling Detected
bits : 1 - 2 (2 bit)

USB_IS_BABBLE : Babble Detected
bits : 2 - 4 (3 bit)

USB_IS_SOF : Start of Frame
bits : 3 - 6 (4 bit)

USB_IS_CONN : Session Connect
bits : 4 - 8 (5 bit)

USB_IS_DISCON : Session Disconnect
bits : 5 - 10 (6 bit)

USB_IS_SESREQ : SESSION REQUEST
bits : 6 - 12 (7 bit)

USB_IS_VBUSERR : VBUS Error
bits : 7 - 14 (8 bit)


IS

USB General Interrupt Status
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IS IS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_IS_SUSPEND USB_IS_RESUME USB_IS_BABBLE USB_IS_RESET USB_IS_SOF USB_IS_CONN USB_IS_DISCON USB_IS_SESREQ USB_IS_VBUSERR

USB_IS_SUSPEND : SUSPEND Signaling Detected
bits : 0 - 0 (1 bit)

USB_IS_RESUME : RESUME Signaling Detected
bits : 1 - 2 (2 bit)

USB_IS_BABBLE : Babble Detected
bits : 2 - 4 (3 bit)

USB_IS_RESET : RESET Signaling Detected
bits : 2 - 4 (3 bit)

USB_IS_SOF : Start of Frame
bits : 3 - 6 (4 bit)

USB_IS_CONN : Session Connect
bits : 4 - 8 (5 bit)

USB_IS_DISCON : Session Disconnect (OTG only)
bits : 5 - 10 (6 bit)

USB_IS_SESREQ : SESSION REQUEST (OTG only)
bits : 6 - 12 (7 bit)

USB_IS_VBUSERR : VBUS Error (OTG only)
bits : 7 - 14 (8 bit)


USB0TXFUNCADDR4

USB Transmit Functional Address Endpoint 4
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR4 USB0TXFUNCADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR4_ADDR

USB_TXFUNCADDR4_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR4

USB Transmit Functional Address Endpoint 4
address_offset : 0xA0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR4 TXFUNCADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR4_ADDR

USB_TXFUNCADDR4_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR4

USB Transmit Hub Address Endpoint 4
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR4 USB0TXHUBADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR4_ADDR

USB_TXHUBADDR4_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR4

USB Transmit Hub Address Endpoint 4
address_offset : 0xA2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR4 TXHUBADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR4_ADDR

USB_TXHUBADDR4_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT4

USB Transmit Hub Port Endpoint 4
address_offset : 0xA3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT4 USB0TXHUBPORT4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT4_PORT

USB_TXHUBPORT4_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT4

USB Transmit Hub Port Endpoint 4
address_offset : 0xA3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT4 TXHUBPORT4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT4_PORT

USB_TXHUBPORT4_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR4

USB Receive Functional Address Endpoint 4
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR4 USB0RXFUNCADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR4_ADDR

USB_RXFUNCADDR4_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR4

USB Receive Functional Address Endpoint 4
address_offset : 0xA4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR4 RXFUNCADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR4_ADDR

USB_RXFUNCADDR4_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR4

USB Receive Hub Address Endpoint 4
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR4 USB0RXHUBADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR4_ADDR

USB_RXHUBADDR4_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR4

USB Receive Hub Address Endpoint 4
address_offset : 0xA6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR4 RXHUBADDR4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR4_ADDR

USB_RXHUBADDR4_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT4

USB Receive Hub Port Endpoint 4
address_offset : 0xA7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT4 USB0RXHUBPORT4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT4_PORT

USB_RXHUBPORT4_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT4

USB Receive Hub Port Endpoint 4
address_offset : 0xA7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT4 RXHUBPORT4 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT4_PORT

USB_RXHUBPORT4_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0TXFUNCADDR5

USB Transmit Functional Address Endpoint 5
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR5 USB0TXFUNCADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR5_ADDR

USB_TXFUNCADDR5_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR5

USB Transmit Functional Address Endpoint 5
address_offset : 0xA8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR5 TXFUNCADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR5_ADDR

USB_TXFUNCADDR5_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR5

USB Transmit Hub Address Endpoint 5
address_offset : 0xAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR5 USB0TXHUBADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR5_ADDR

USB_TXHUBADDR5_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR5

USB Transmit Hub Address Endpoint 5
address_offset : 0xAA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR5 TXHUBADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR5_ADDR

USB_TXHUBADDR5_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT5

USB Transmit Hub Port Endpoint 5
address_offset : 0xAB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT5 USB0TXHUBPORT5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT5_PORT

USB_TXHUBPORT5_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT5

USB Transmit Hub Port Endpoint 5
address_offset : 0xAB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT5 TXHUBPORT5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT5_PORT

USB_TXHUBPORT5_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR5

USB Receive Functional Address Endpoint 5
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR5 USB0RXFUNCADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR5_ADDR

USB_RXFUNCADDR5_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR5

USB Receive Functional Address Endpoint 5
address_offset : 0xAC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR5 RXFUNCADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR5_ADDR

USB_RXFUNCADDR5_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR5

USB Receive Hub Address Endpoint 5
address_offset : 0xAE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR5 USB0RXHUBADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR5_ADDR

USB_RXHUBADDR5_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR5

USB Receive Hub Address Endpoint 5
address_offset : 0xAE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR5 RXHUBADDR5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR5_ADDR

USB_RXHUBADDR5_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT5

USB Receive Hub Port Endpoint 5
address_offset : 0xAF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT5 USB0RXHUBPORT5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT5_PORT

USB_RXHUBPORT5_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT5

USB Receive Hub Port Endpoint 5
address_offset : 0xAF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT5 RXHUBPORT5 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT5_PORT

USB_RXHUBPORT5_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0IE

USB Interrupt Enable
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0IE USB0IE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_IE_SUSPND USB_IE_RESUME USB_IE_BABBLE USB_IE_SOF USB_IE_CONN USB_IE_DISCON USB_IE_SESREQ USB_IE_VBUSERR

USB_IE_SUSPND : Enable SUSPEND Interrupt
bits : 0 - 0 (1 bit)

USB_IE_RESUME : Enable RESUME Interrupt
bits : 1 - 2 (2 bit)

USB_IE_BABBLE : Enable Babble Interrupt
bits : 2 - 4 (3 bit)

USB_IE_SOF : Enable Start-of-Frame Interrupt
bits : 3 - 6 (4 bit)

USB_IE_CONN : Enable Connect Interrupt
bits : 4 - 8 (5 bit)

USB_IE_DISCON : Enable Disconnect Interrupt
bits : 5 - 10 (6 bit)

USB_IE_SESREQ : Enable Session Request
bits : 6 - 12 (7 bit)

USB_IE_VBUSERR : Enable VBUS Error Interrupt
bits : 7 - 14 (8 bit)


IE

USB Interrupt Enable
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_IE_SUSPND USB_IE_RESUME USB_IE_BABBLE USB_IE_RESET USB_IE_SOF USB_IE_CONN USB_IE_DISCON USB_IE_SESREQ USB_IE_VBUSERR

USB_IE_SUSPND : Enable SUSPEND Interrupt
bits : 0 - 0 (1 bit)

USB_IE_RESUME : Enable RESUME Interrupt
bits : 1 - 2 (2 bit)

USB_IE_BABBLE : Enable Babble Interrupt
bits : 2 - 4 (3 bit)

USB_IE_RESET : Enable RESET Interrupt
bits : 2 - 4 (3 bit)

USB_IE_SOF : Enable Start-of-Frame Interrupt
bits : 3 - 6 (4 bit)

USB_IE_CONN : Enable Connect Interrupt
bits : 4 - 8 (5 bit)

USB_IE_DISCON : Enable Disconnect Interrupt
bits : 5 - 10 (6 bit)

USB_IE_SESREQ : Enable Session Request (OTG only)
bits : 6 - 12 (7 bit)

USB_IE_VBUSERR : Enable VBUS Error Interrupt (OTG only)
bits : 7 - 14 (8 bit)


USB0TXFUNCADDR6

USB Transmit Functional Address Endpoint 6
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR6 USB0TXFUNCADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR6_ADDR

USB_TXFUNCADDR6_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR6

USB Transmit Functional Address Endpoint 6
address_offset : 0xB0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR6 TXFUNCADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR6_ADDR

USB_TXFUNCADDR6_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR6

USB Transmit Hub Address Endpoint 6
address_offset : 0xB2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR6 USB0TXHUBADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR6_ADDR

USB_TXHUBADDR6_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR6

USB Transmit Hub Address Endpoint 6
address_offset : 0xB2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR6 TXHUBADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR6_ADDR

USB_TXHUBADDR6_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT6

USB Transmit Hub Port Endpoint 6
address_offset : 0xB3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT6 USB0TXHUBPORT6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT6_PORT

USB_TXHUBPORT6_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT6

USB Transmit Hub Port Endpoint 6
address_offset : 0xB3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT6 TXHUBPORT6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT6_PORT

USB_TXHUBPORT6_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR6

USB Receive Functional Address Endpoint 6
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR6 USB0RXFUNCADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR6_ADDR

USB_RXFUNCADDR6_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR6

USB Receive Functional Address Endpoint 6
address_offset : 0xB4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR6 RXFUNCADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR6_ADDR

USB_RXFUNCADDR6_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR6

USB Receive Hub Address Endpoint 6
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR6 USB0RXHUBADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR6_ADDR

USB_RXHUBADDR6_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR6

USB Receive Hub Address Endpoint 6
address_offset : 0xB6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR6 RXHUBADDR6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR6_ADDR

USB_RXHUBADDR6_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT6

USB Receive Hub Port Endpoint 6
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT6 USB0RXHUBPORT6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT6_PORT

USB_RXHUBPORT6_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT6

USB Receive Hub Port Endpoint 6
address_offset : 0xB7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT6 RXHUBPORT6 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT6_PORT

USB_RXHUBPORT6_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0TXFUNCADDR7

USB Transmit Functional Address Endpoint 7
address_offset : 0xB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXFUNCADDR7 USB0TXFUNCADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR7_ADDR

USB_TXFUNCADDR7_ADDR : Device Address
bits : 0 - 6 (7 bit)


TXFUNCADDR7

USB Transmit Functional Address Endpoint 7
address_offset : 0xB8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXFUNCADDR7 TXFUNCADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXFUNCADDR7_ADDR

USB_TXFUNCADDR7_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0TXHUBADDR7

USB Transmit Hub Address Endpoint 7
address_offset : 0xBA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBADDR7 USB0TXHUBADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR7_ADDR

USB_TXHUBADDR7_ADDR : Hub Address
bits : 0 - 6 (7 bit)


TXHUBADDR7

USB Transmit Hub Address Endpoint 7
address_offset : 0xBA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBADDR7 TXHUBADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBADDR7_ADDR

USB_TXHUBADDR7_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0TXHUBPORT7

USB Transmit Hub Port Endpoint 7
address_offset : 0xBB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TXHUBPORT7 USB0TXHUBPORT7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT7_PORT

USB_TXHUBPORT7_PORT : Hub Port
bits : 0 - 6 (7 bit)


TXHUBPORT7

USB Transmit Hub Port Endpoint 7
address_offset : 0xBB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXHUBPORT7 TXHUBPORT7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TXHUBPORT7_PORT

USB_TXHUBPORT7_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0RXFUNCADDR7

USB Receive Functional Address Endpoint 7
address_offset : 0xBC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXFUNCADDR7 USB0RXFUNCADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR7_ADDR

USB_RXFUNCADDR7_ADDR : Device Address
bits : 0 - 6 (7 bit)


RXFUNCADDR7

USB Receive Functional Address Endpoint 7
address_offset : 0xBC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFUNCADDR7 RXFUNCADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXFUNCADDR7_ADDR

USB_RXFUNCADDR7_ADDR : Device Address
bits : 0 - 6 (7 bit)


USB0RXHUBADDR7

USB Receive Hub Address Endpoint 7
address_offset : 0xBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBADDR7 USB0RXHUBADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR7_ADDR

USB_RXHUBADDR7_ADDR : Hub Address
bits : 0 - 6 (7 bit)


RXHUBADDR7

USB Receive Hub Address Endpoint 7
address_offset : 0xBE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBADDR7 RXHUBADDR7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBADDR7_ADDR

USB_RXHUBADDR7_ADDR : Hub Address
bits : 0 - 6 (7 bit)


USB0RXHUBPORT7

USB Receive Hub Port Endpoint 7
address_offset : 0xBF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0RXHUBPORT7 USB0RXHUBPORT7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT7_PORT

USB_RXHUBPORT7_PORT : Hub Port
bits : 0 - 6 (7 bit)


RXHUBPORT7

USB Receive Hub Port Endpoint 7
address_offset : 0xBF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXHUBPORT7 RXHUBPORT7 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_RXHUBPORT7_PORT

USB_RXHUBPORT7_PORT : Hub Port
bits : 0 - 6 (7 bit)


USB0FRAME

USB Frame Value
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0FRAME USB0FRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FRAME

USB_FRAME : Frame Number
bits : 0 - 10 (11 bit)


FRAME

USB Frame Value
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAME FRAME read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FRAME

USB_FRAME : Frame Number
bits : 0 - 10 (11 bit)


USB0EPIDX

USB Endpoint Index
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0EPIDX USB0EPIDX read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_EPIDX_EPIDX

USB_EPIDX_EPIDX : Endpoint Index
bits : 0 - 3 (4 bit)


EPIDX

USB Endpoint Index
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EPIDX EPIDX read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_EPIDX_EPIDX

USB_EPIDX_EPIDX : Endpoint Index
bits : 0 - 3 (4 bit)


USB0TEST

USB Test Mode
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0TEST USB0TEST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TEST_FORCEFS USB_TEST_FIFOACC USB_TEST_FORCEH

USB_TEST_FORCEFS : Force Full-Speed Mode
bits : 5 - 10 (6 bit)

USB_TEST_FIFOACC : FIFO Access
bits : 6 - 12 (7 bit)

USB_TEST_FORCEH : Force Host Mode
bits : 7 - 14 (8 bit)


TEST

USB Test Mode
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST TEST read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_TEST_FORCEFS USB_TEST_FIFOACC USB_TEST_FORCEH

USB_TEST_FORCEFS : Force Full-Speed Mode
bits : 5 - 10 (6 bit)

USB_TEST_FIFOACC : FIFO Access
bits : 6 - 12 (7 bit)

USB_TEST_FORCEH : Force Host Mode
bits : 7 - 14 (8 bit)


USB0PP

USB Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB0PP USB0PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_PP_TYPE USB_PP_PHY USB_PP_USB USB_PP_ECNT

USB_PP_TYPE : Controller Type
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : USB_PP_TYPE_0

The first-generation USB controller

End of enumeration elements list.

USB_PP_PHY : PHY Present
bits : 4 - 8 (5 bit)

USB_PP_USB : USB Capability
bits : 6 - 13 (8 bit)

Enumeration:

0x1 : USB_PP_USB_DEVICE

DEVICE

0x2 : USB_PP_USB_HOSTDEVICE

HOST

0x3 : USB_PP_USB_OTG

OTG

End of enumeration elements list.

USB_PP_ECNT : Endpoint Count
bits : 8 - 23 (16 bit)


PP

USB Peripheral Properties
address_offset : 0xFC0 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PP PP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_PP_TYPE USB_PP_PHY USB_PP_USB USB_PP_ECNT

USB_PP_TYPE : Controller Type
bits : 0 - 3 (4 bit)

Enumeration:

0x0 : USB_PP_TYPE_0

The first-generation USB controller

End of enumeration elements list.

USB_PP_PHY : PHY Present
bits : 4 - 8 (5 bit)

USB_PP_USB : USB Capability
bits : 6 - 13 (8 bit)

Enumeration:

0x1 : USB_PP_USB_DEVICE

DEVICE

0x2 : USB_PP_USB_HOSTDEVICE

HOST

0x3 : USB_PP_USB_OTG

OTG

End of enumeration elements list.

USB_PP_ECNT : Endpoint Count
bits : 8 - 23 (16 bit)



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