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CRYPTO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DMACH0CTL

AESTAGOUT1

AESKEY22

AESKEY32

AESIV2

AESTAGOUT2

DMASTAT

AESKEY23

AESKEY33

AESIV3

AESTAGOUT3

DMASWRESET

DMACH1CTL

DMACH1EXTADDR

DMACH1LEN

DMACH0EXTADDR

KEYWRITEAREA

KEYWRITTENAREA

KEYSIZE

KEYREADAREA

AESCTL

AESDATALEN0

AESDATALEN1

AESAUTHLEN

AESDATAOUT0

AESDATAIN0

AESDATAOUT1

AESDATAIN1

AESDATAOUT2

AESDATAIN2

AESDATAOUT3

AESDATAIN3

ALGSEL

DMAPROTCTL

SWRESET

DMABUSCFG

IRQTYPE

IRQEN

IRQCLR

IRQSET

IRQSTAT

DMAPORTERR

HWVER

AESKEY20

AESKEY30

AESIV0

AESTAGOUT0

DMACH0LEN

AESKEY21

AESKEY31

DMAHWVER

AESIV1


DMACH0CTL

DMA Channel 0 Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACH0CTL DMACH0CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PRIO

EN : EN
bits : 0 - 0 (1 bit)

PRIO : PRIO
bits : 1 - 2 (2 bit)


AESTAGOUT1

AES Tag Output
address_offset : 0x1054 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AESTAGOUT1 AESTAGOUT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : TAG
bits : 0 - 31 (32 bit)


AESKEY22

Clear AES_KEY2/GHASH Key
address_offset : 0x140C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY22 AESKEY22 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : KEY2
bits : 0 - 31 (32 bit)


AESKEY32

Clear AES_KEY3
address_offset : 0x144C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY32 AESKEY32 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY3

KEY3 : KEY3
bits : 0 - 31 (32 bit)


AESIV2

AES Initialization Vector
address_offset : 0x150C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AESIV2 AESIV2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : IV
bits : 0 - 31 (32 bit)


AESTAGOUT2

AES Tag Output
address_offset : 0x15CC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AESTAGOUT2 AESTAGOUT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : TAG
bits : 0 - 31 (32 bit)


DMASTAT

DMA Controller Status
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMASTAT DMASTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_ACTIVE CH1_ACTIVE PORT_ERR

CH0_ACTIVE : CH0_ACTIVE
bits : 0 - 0 (1 bit)

CH1_ACTIVE : CH1_ACTIVE
bits : 1 - 2 (2 bit)

PORT_ERR : PORT_ERR
bits : 17 - 34 (18 bit)


AESKEY23

Clear AES_KEY2/GHASH Key
address_offset : 0x1918 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY23 AESKEY23 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : KEY2
bits : 0 - 31 (32 bit)


AESKEY33

Clear AES_KEY3
address_offset : 0x1968 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY33 AESKEY33 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY3

KEY3 : KEY3
bits : 0 - 31 (32 bit)


AESIV3

AES Initialization Vector
address_offset : 0x1A58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AESIV3 AESIV3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : IV
bits : 0 - 31 (32 bit)


AESTAGOUT3

AES Tag Output
address_offset : 0x1B48 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AESTAGOUT3 AESTAGOUT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : TAG
bits : 0 - 31 (32 bit)


DMASWRESET

DMA Controller Software Reset
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DMASWRESET DMASWRESET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET

RESET : RESET
bits : 0 - 0 (1 bit)


DMACH1CTL

DMA Channel 1 Control
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACH1CTL DMACH1CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PRIO

EN : EN
bits : 0 - 0 (1 bit)

PRIO : PRIO
bits : 1 - 2 (2 bit)


DMACH1EXTADDR

DMA Channel 1 External Address
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACH1EXTADDR DMACH1EXTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ADDR
bits : 0 - 31 (32 bit)


DMACH1LEN

DMA Channel 1 Length
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACH1LEN DMACH1LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : LEN
bits : 0 - 15 (16 bit)


DMACH0EXTADDR

DMA Channel 0 External Address
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACH0EXTADDR DMACH0EXTADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDR

ADDR : ADDR
bits : 0 - 31 (32 bit)


KEYWRITEAREA

Key Write Area
address_offset : 0x400 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYWRITEAREA KEYWRITEAREA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM_AREA0 RAM_AREA1 RAM_AREA2 RAM_AREA3 RAM_AREA4 RAM_AREA5 RAM_AREA6 RAM_AREA7

RAM_AREA0 : RAM_AREA0
bits : 0 - 0 (1 bit)

RAM_AREA1 : RAM_AREA1
bits : 1 - 2 (2 bit)

RAM_AREA2 : RAM_AREA2
bits : 2 - 4 (3 bit)

RAM_AREA3 : RAM_AREA3
bits : 3 - 6 (4 bit)

RAM_AREA4 : RAM_AREA4
bits : 4 - 8 (5 bit)

RAM_AREA5 : RAM_AREA5
bits : 5 - 10 (6 bit)

RAM_AREA6 : RAM_AREA6
bits : 6 - 12 (7 bit)

RAM_AREA7 : RAM_AREA7
bits : 7 - 14 (8 bit)


KEYWRITTENAREA

Key Written Area Status This register shows which areas of the key store RAM contain valid written keys. When a new key needs to be written to the key store, on a location that is already occupied by a valid key, this key area must be cleared first. This can be done by writing this register before the new key is written to the key store memory. Attempting to write to a key area that already contains a valid key is not allowed and will result in an error.
address_offset : 0x404 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYWRITTENAREA KEYWRITTENAREA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM_AREA_WRITTEN0 RAM_AREA_WRITTEN1 RAM_AREA_WRITTEN2 RAM_AREA_WRITTEN3 RAM_AREA_WRITTEN4 RAM_AREA_WRITTEN5 RAM_AREA_WRITTEN6 RAM_AREA_WRITTEN7

RAM_AREA_WRITTEN0 : RAM_AREA_WRITTEN0
bits : 0 - 0 (1 bit)

RAM_AREA_WRITTEN1 : RAM_AREA_WRITTEN1
bits : 1 - 2 (2 bit)

RAM_AREA_WRITTEN2 : RAM_AREA_WRITTEN2
bits : 2 - 4 (3 bit)

RAM_AREA_WRITTEN3 : RAM_AREA_WRITTEN3
bits : 3 - 6 (4 bit)

RAM_AREA_WRITTEN4 : RAM_AREA_WRITTEN4
bits : 4 - 8 (5 bit)

RAM_AREA_WRITTEN5 : RAM_AREA_WRITTEN5
bits : 5 - 10 (6 bit)

RAM_AREA_WRITTEN6 : RAM_AREA_WRITTEN6
bits : 6 - 12 (7 bit)

RAM_AREA_WRITTEN7 : RAM_AREA_WRITTEN7
bits : 7 - 14 (8 bit)


KEYSIZE

Key Size This register defines the size of the keys that are written with DMA.
address_offset : 0x408 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYSIZE KEYSIZE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SIZE

SIZE : SIZE
bits : 0 - 1 (2 bit)


KEYREADAREA

Key Read Area
address_offset : 0x40C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

KEYREADAREA KEYREADAREA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM_AREA BUSY

RAM_AREA : RAM_AREA
bits : 0 - 3 (4 bit)

BUSY : BUSY
bits : 31 - 62 (32 bit)


AESCTL

AES Input/Output Buffer Control
address_offset : 0x550 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AESCTL AESCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTPUT_RDY INPUT_RDY DIR KEY_SIZE CBC CTR CTR_WIDTH CBC_MAC CCM CCM_L CCM_M SAVE_CONTEXT SAVED_CONTEXT_RDY CONTEXT_RDY

OUTPUT_RDY : OUTPUT_RDY
bits : 0 - 0 (1 bit)

INPUT_RDY : INPUT_RDY
bits : 1 - 2 (2 bit)

DIR : DIR
bits : 2 - 4 (3 bit)

KEY_SIZE : KEY_SIZE
bits : 3 - 7 (5 bit)

CBC : CBC
bits : 5 - 10 (6 bit)

CTR : CTR
bits : 6 - 12 (7 bit)

CTR_WIDTH : CTR_WIDTH
bits : 7 - 15 (9 bit)

CBC_MAC : CBC_MAC
bits : 15 - 30 (16 bit)

CCM : CCM
bits : 18 - 36 (19 bit)

CCM_L : CCM_L
bits : 19 - 40 (22 bit)

CCM_M : CCM_M
bits : 22 - 46 (25 bit)

SAVE_CONTEXT : SAVE_CONTEXT
bits : 29 - 58 (30 bit)

SAVED_CONTEXT_RDY : SAVED_CONTEXT_RDY
bits : 30 - 60 (31 bit)

CONTEXT_RDY : CONTEXT_RDY
bits : 31 - 62 (32 bit)


AESDATALEN0

Crypto Data Length LSW
address_offset : 0x554 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESDATALEN0 AESDATALEN0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN_LSW

LEN_LSW : LEN_LSW
bits : 0 - 31 (32 bit)


AESDATALEN1

Crypto Data Length MSW
address_offset : 0x558 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESDATALEN1 AESDATALEN1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN_MSW

LEN_MSW : LEN_MSW
bits : 0 - 28 (29 bit)


AESAUTHLEN

AES Authentication Length
address_offset : 0x55C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESAUTHLEN AESAUTHLEN write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : LEN
bits : 0 - 31 (32 bit)


AESDATAOUT0

Data Input/Output
address_offset : 0x560 Bytes (0x0)
access : read-only
reset_value : 0x0
alternate_register : AESDATAIN0
reset_Mask : 0x0

AESDATAOUT0 AESDATAOUT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAIN0

AES Data Input/Output 0
address_offset : 0x560 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESDATAIN0 AESDATAIN0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAOUT1

AES Data Input/Output 3
address_offset : 0x564 Bytes (0x0)
access : read-only
reset_value : 0x0
alternate_register : AESDATAIN1
reset_Mask : 0x0

AESDATAOUT1 AESDATAOUT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAIN1

AES Data Input/Output 1
address_offset : 0x564 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESDATAIN1 AESDATAIN1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAOUT2

AES Data Input/Output 2
address_offset : 0x568 Bytes (0x0)
access : read-only
reset_value : 0x0
alternate_register : AESDATAIN2
reset_Mask : 0x0

AESDATAOUT2 AESDATAOUT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAIN2

AES Data Input/Output 2
address_offset : 0x568 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESDATAIN2 AESDATAIN2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAOUT3

AES Data Input/Output 3
address_offset : 0x56C Bytes (0x0)
access : read-only
reset_value : 0x0
alternate_register : AESDATAIN3
reset_Mask : 0x0

AESDATAOUT3 AESDATAOUT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


AESDATAIN3

Data Input/Output
address_offset : 0x56C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESDATAIN3 AESDATAIN3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 31 (32 bit)


ALGSEL

Master Algorithm Select This register configures the internal destination of the DMA controller.
address_offset : 0x700 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALGSEL ALGSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY_STORE AES TAG

KEY_STORE : KEY_STORE
bits : 0 - 0 (1 bit)

AES : AES
bits : 1 - 2 (2 bit)

TAG : TAG
bits : 31 - 62 (32 bit)


DMAPROTCTL

Master Protection Control
address_offset : 0x704 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMAPROTCTL DMAPROTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN

EN : EN
bits : 0 - 0 (1 bit)


SWRESET

Software Reset
address_offset : 0x740 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWRESET SWRESET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET

RESET : RESET
bits : 0 - 0 (1 bit)


DMABUSCFG

DMA Controller Master Configuration
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMABUSCFG DMABUSCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_MST1_BIGEND AHB_MST1_LOCK_EN AHB_MST1_INCR_EN AHB_MST1_IDLE_EN AHB_MST1_BURST_SIZE

AHB_MST1_BIGEND : AHB_MST1_BIGEND
bits : 8 - 16 (9 bit)

AHB_MST1_LOCK_EN : AHB_MST1_LOCK_EN
bits : 9 - 18 (10 bit)

AHB_MST1_INCR_EN : AHB_MST1_INCR_EN
bits : 10 - 20 (11 bit)

AHB_MST1_IDLE_EN : AHB_MST1_IDLE_EN
bits : 11 - 22 (12 bit)

AHB_MST1_BURST_SIZE : AHB_MST1_BURST_SIZE
bits : 12 - 27 (16 bit)


IRQTYPE

Interrupt Configuration
address_offset : 0x780 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQTYPE IRQTYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IEN

IEN : IEN
bits : 0 - 0 (1 bit)


IRQEN

Interrupt Enable
address_offset : 0x784 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQEN IRQEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT_AVAIL DMA_IN_DONE

RESULT_AVAIL : RESULT_AVAIL
bits : 0 - 0 (1 bit)

DMA_IN_DONE : DMA_IN_DONE
bits : 1 - 2 (2 bit)


IRQCLR

Interrupt Clear
address_offset : 0x788 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IRQCLR IRQCLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT_AVAIL DMA_IN_DONE KEY_ST_RD_ERR KEY_ST_WR_ERR DMA_BUS_ERR

RESULT_AVAIL : RESULT_AVAIL
bits : 0 - 0 (1 bit)

DMA_IN_DONE : DMA_IN_DONE
bits : 1 - 2 (2 bit)

KEY_ST_RD_ERR : KEY_ST_RD_ERR
bits : 29 - 58 (30 bit)

KEY_ST_WR_ERR : KEY_ST_WR_ERR
bits : 30 - 60 (31 bit)

DMA_BUS_ERR : DMA_BUS_ERR
bits : 31 - 62 (32 bit)


IRQSET

Interrupt Set
address_offset : 0x78C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IRQSET IRQSET write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT_AVAIL DMA_IN_DONE

RESULT_AVAIL : RESULT_AVAIL
bits : 0 - 0 (1 bit)

DMA_IN_DONE : DMA_IN_DONE
bits : 1 - 2 (2 bit)


IRQSTAT

Interrupt Status
address_offset : 0x790 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IRQSTAT IRQSTAT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT_AVAIL DMA_IN_DONE KEY_ST_RD_ERR KEY_ST_WR_ERR DMA_BUS_ERR

RESULT_AVAIL : RESULT_AVAIL
bits : 0 - 0 (1 bit)

DMA_IN_DONE : DMA_IN_DONE
bits : 1 - 2 (2 bit)

KEY_ST_RD_ERR : KEY_ST_RD_ERR
bits : 29 - 58 (30 bit)

KEY_ST_WR_ERR : KEY_ST_WR_ERR
bits : 30 - 60 (31 bit)

DMA_BUS_ERR : DMA_BUS_ERR
bits : 31 - 62 (32 bit)


DMAPORTERR

DMA Controller Port Error
address_offset : 0x7C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAPORTERR DMAPORTERR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LAST_CH AHB_ERR

LAST_CH : LAST_CH
bits : 9 - 18 (10 bit)

AHB_ERR : AHB_ERR
bits : 12 - 24 (13 bit)


HWVER

CTRL Module Version
address_offset : 0x7FC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HWVER HWVER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VER_NUM VER_NUM_COMPL HW_PATCH_LVL HW_MINOR_VER HW_MAJOR_VER

VER_NUM : VER_NUM
bits : 0 - 7 (8 bit)

VER_NUM_COMPL : VER_NUM_COMPL
bits : 8 - 23 (16 bit)

HW_PATCH_LVL : HW_PATCH_LVL
bits : 16 - 35 (20 bit)

HW_MINOR_VER : HW_MINOR_VER
bits : 20 - 43 (24 bit)

HW_MAJOR_VER : HW_MAJOR_VER
bits : 24 - 51 (28 bit)


AESKEY20

Clear AES_KEY2/GHASH Key
address_offset : 0xA00 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY20 AESKEY20 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : KEY2
bits : 0 - 31 (32 bit)


AESKEY30

Clear AES_KEY3
address_offset : 0xA20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY30 AESKEY30 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY3

KEY3 : KEY3
bits : 0 - 31 (32 bit)


AESIV0

AES Initialization Vector
address_offset : 0xA80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AESIV0 AESIV0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : IV
bits : 0 - 31 (32 bit)


AESTAGOUT0

AES Tag Output
address_offset : 0xAE0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

AESTAGOUT0 AESTAGOUT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAG

TAG : TAG
bits : 0 - 31 (32 bit)


DMACH0LEN

DMA Channel 0 Length
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACH0LEN DMACH0LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN

LEN : LEN
bits : 0 - 15 (16 bit)


AESKEY21

Clear AES_KEY2/GHASH Key
address_offset : 0xF04 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY21 AESKEY21 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : KEY2
bits : 0 - 31 (32 bit)


AESKEY31

Clear AES_KEY3
address_offset : 0xF34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

AESKEY31 AESKEY31 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY3

KEY3 : KEY3
bits : 0 - 31 (32 bit)


DMAHWVER

DMA Controller Version
address_offset : 0xFC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DMAHWVER DMAHWVER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VER_NUM VER_NUM_COMPL HW_PATCH_LVL HW_MINOR_VER HW_MAJOR_VER

VER_NUM : VER_NUM
bits : 0 - 7 (8 bit)

VER_NUM_COMPL : VER_NUM_COMPL
bits : 8 - 23 (16 bit)

HW_PATCH_LVL : HW_PATCH_LVL
bits : 16 - 35 (20 bit)

HW_MINOR_VER : HW_MINOR_VER
bits : 20 - 43 (24 bit)

HW_MAJOR_VER : HW_MAJOR_VER
bits : 24 - 51 (28 bit)


AESIV1

AES Initialization Vector
address_offset : 0xFC4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AESIV1 AESIV1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IV

IV : IV
bits : 0 - 31 (32 bit)



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