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IOC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IOCFG0

IOCFG4

IOCFG5

IOCFG6

IOCFG7

IOCFG8

IOCFG9

IOCFG10

IOCFG11

IOCFG12

IOCFG13

IOCFG14

IOCFG15

IOCFG1

IOCFG16

IOCFG17

IOCFG18

IOCFG19

IOCFG20

IOCFG21

IOCFG22

IOCFG23

IOCFG24

IOCFG25

IOCFG26

IOCFG27

IOCFG28

IOCFG29

IOCFG30

IOCFG31

IOCFG2

IOCFG3


IOCFG0

Configuration of DIO0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG0 IOCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG4

Configuration of DIO4
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG4 IOCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG5

Configuration of DIO5
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG5 IOCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG6

Configuration of DIO6
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG6 IOCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG7

Configuration of DIO7
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG7 IOCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG8

Configuration of DIO8
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG8 IOCFG8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG9

Configuration of DIO9
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG9 IOCFG9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG10

Configuration of DIO10
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG10 IOCFG10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG11

Configuration of DIO11
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG11 IOCFG11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG12

Configuration of DIO12
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG12 IOCFG12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG13

Configuration of DIO13
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG13 IOCFG13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG14

Configuration of DIO14
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG14 IOCFG14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG15

Configuration of DIO15
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG15 IOCFG15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG1

Configuration of DIO1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG1 IOCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG16

Configuration of DIO16
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG16 IOCFG16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG17

Configuration of DIO17
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG17 IOCFG17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG18

Configuration of DIO18
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG18 IOCFG18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG19

Configuration of DIO19
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG19 IOCFG19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG20

Configuration of DIO20
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG20 IOCFG20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG21

Configuration of DIO21
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG21 IOCFG21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG22

Configuration of DIO22
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG22 IOCFG22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG23

Configuration of DIO23
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG23 IOCFG23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG24

Configuration of DIO24
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG24 IOCFG24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG25

Configuration of DIO25
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG25 IOCFG25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG26

Configuration of DIO26
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG26 IOCFG26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG27

Configuration of DIO27
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG27 IOCFG27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG28

Configuration of DIO28
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG28 IOCFG28 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG29

Configuration of DIO29
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG29 IOCFG29 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG30

Configuration of DIO30
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG30 IOCFG30 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG31

Configuration of DIO31
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG31 IOCFG31 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG2

Configuration of DIO2
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG2 IOCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)


IOCFG3

Configuration of DIO3
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IOCFG3 IOCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PORT_ID IOSTR IOCURR SLEW_RED PULL_CTL EDGE_DET EDGE_IRQ_EN IOMODE WU_CFG IE HYST_EN

PORT_ID : PORT_ID
bits : 0 - 5 (6 bit)

IOSTR : IOSTR
bits : 8 - 17 (10 bit)

IOCURR : IOCURR
bits : 10 - 21 (12 bit)

SLEW_RED : SLEW_RED
bits : 12 - 24 (13 bit)

PULL_CTL : PULL_CTL
bits : 13 - 27 (15 bit)

EDGE_DET : EDGE_DET
bits : 16 - 33 (18 bit)

EDGE_IRQ_EN : EDGE_IRQ_EN
bits : 18 - 36 (19 bit)

IOMODE : IOMODE
bits : 24 - 50 (27 bit)

WU_CFG : WU_CFG
bits : 27 - 55 (29 bit)

IE : IE
bits : 29 - 58 (30 bit)

HYST_EN : HYST_EN
bits : 30 - 60 (31 bit)



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