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SSI0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR0

CPSR

IMSC

RIS

MIS

ICR

DMACR

CR1

DR

SR


CR0

Control 0
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR0 CR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSS FRF SPO SPH SCR

DSS : DSS
bits : 0 - 3 (4 bit)

FRF : FRF
bits : 4 - 9 (6 bit)

SPO : SPO
bits : 6 - 12 (7 bit)

SPH : SPH
bits : 7 - 14 (8 bit)

SCR : SCR
bits : 8 - 23 (16 bit)


CPSR

Clock Prescale
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPSR CPSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPSDVSR

CPSDVSR : CPSDVSR
bits : 0 - 7 (8 bit)


IMSC

Interrupt Mask Set and Clear
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IMSC IMSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIM RTIM RXIM TXIM

RORIM : RORIM
bits : 0 - 0 (1 bit)

RTIM : RTIM
bits : 1 - 2 (2 bit)

RXIM : RXIM
bits : 2 - 4 (3 bit)

TXIM : TXIM
bits : 3 - 6 (4 bit)


RIS

Raw Interrupt Status
address_offset : 0x18 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RIS RIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORRIS RTRIS RXRIS TXRIS

RORRIS : RORRIS
bits : 0 - 0 (1 bit)

RTRIS : RTRIS
bits : 1 - 2 (2 bit)

RXRIS : RXRIS
bits : 2 - 4 (3 bit)

TXRIS : TXRIS
bits : 3 - 6 (4 bit)


MIS

Masked Interrupt Status
address_offset : 0x1C Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

MIS MIS read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORMIS RTMIS RXMIS TXMIS

RORMIS : RORMIS
bits : 0 - 0 (1 bit)

RTMIS : RTMIS
bits : 1 - 2 (2 bit)

RXMIS : RXMIS
bits : 2 - 4 (3 bit)

TXMIS : TXMIS
bits : 3 - 6 (4 bit)


ICR

Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect.
address_offset : 0x20 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RORIC RTIC

RORIC : RORIC
bits : 0 - 0 (1 bit)

RTIC : RTIC
bits : 1 - 2 (2 bit)


DMACR

DMA Control
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACR DMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAE TXDMAE

RXDMAE : RXDMAE
bits : 0 - 0 (1 bit)

TXDMAE : TXDMAE
bits : 1 - 2 (2 bit)


CR1

Control 1
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LBM SSE MS SOD

LBM : LBM
bits : 0 - 0 (1 bit)

SSE : SSE
bits : 1 - 2 (2 bit)

MS : MS
bits : 2 - 4 (3 bit)

SOD : SOD
bits : 3 - 6 (4 bit)


DR

Data 16-bits wide data register: When read, the entry in the receive FIFO, pointed to by the current FIFO read pointer, is accessed. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer. When written, the entry in the transmit FIFO, pointed to by the write pointer, is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer.
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DR DR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : DATA
bits : 0 - 15 (16 bit)


SR

Status
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFE TNF RNE RFF BSY

TFE : TFE
bits : 0 - 0 (1 bit)

TNF : TNF
bits : 1 - 2 (2 bit)

RNE : RNE
bits : 2 - 4 (3 bit)

RFF : RFF
bits : 3 - 6 (4 bit)

BSY : BSY
bits : 4 - 8 (5 bit)



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