\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Status
address_offset : 0x0 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MASTERENABLE : MASTERENABLE
bits : 0 - 0 (1 bit)
STATE : STATE
bits : 4 - 11 (8 bit)
TOTALCHANNELS : TOTALCHANNELS
bits : 16 - 36 (21 bit)
TEST : TEST
bits : 28 - 59 (32 bit)
Channel Wait On Request Status
address_offset : 0x10 Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHNLSTATUS : CHNLSTATUS
bits : 0 - 31 (32 bit)
Channel Software Request
address_offset : 0x14 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Set UseBurst
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Clear UseBurst
address_offset : 0x1C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Set Request Mask
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Clear Channel Request Mask
address_offset : 0x24 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Set Channel Enable
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Clear Channel Enable
address_offset : 0x2C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Set Primary-Alternate
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Clear Primary-Alternate
address_offset : 0x34 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Set Channel Priority
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Clear Channel Priority
address_offset : 0x3C Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Configuration
address_offset : 0x4 Bytes (0x0)
access : write-only
reset_value : 0x0
reset_Mask : 0x0
MASTERENABLE : MASTERENABLE
bits : 0 - 0 (1 bit)
PRTOCTRL : PRTOCTRL
bits : 5 - 12 (8 bit)
Error Status and Clear
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATUS : STATUS
bits : 0 - 0 (1 bit)
Channel Request Done
address_offset : 0x504 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Request Done Mask
address_offset : 0x520 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNLS : CHNLS
bits : 0 - 31 (32 bit)
Channel Control Data Base Pointer
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASEPTR : BASEPTR
bits : 10 - 41 (32 bit)
Channel Alternate Control Data Base Pointer
address_offset : 0xC Bytes (0x0)
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BASEPTR : BASEPTR
bits : 0 - 31 (32 bit)
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