\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
PCE core interrupt control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCERST : PCERST
bits : 0 - 0 (1 bit)
access : read-write
PCENMI : PCENMI
bits : 1 - 1 (1 bit)
access : write-only
PCEINT : PCEINT
bits : 2 - 2 (1 bit)
access : write-only
PCE core NMI event clear)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTNMIC : WDTNMIC
bits : 0 - 0 (1 bit)
access : write-only
PCEIFNMIC : PCEIFNMIC
bits : 1 - 1 (1 bit)
access : write-only
Interrupt control to the main core
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAININT : MAININT
bits : 0 - 0 (1 bit)
access : write-only
PCE core clock control)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCECLK : PCECLK
bits : 0 - 0 (1 bit)
access : read-write
PCE core NMI event flag)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTNMIF : WDTNMIF
bits : 0 - 0 (1 bit)
access : read-only
PCEIFNMIF : PCEIFNMIF
bits : 1 - 1 (1 bit)
access : read-only
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