Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
UART receive/transmit FIFO
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTX : Receive and Transmit FIFO buffer (read: RX FIFO, write: TX FIFO)
bits : 0 - 6 (7 bit)
UART Line Status
address_offset : 0x14 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXDR : RX data ready
bits : 0 - -1 (0 bit)
Enumeration:
0 : empty
RX FIFO empty
1 : not empty
At least one entry in RX FIFO
End of enumeration elements list.
RXOE : RX overrun error
bits : 1 - 0 (0 bit)
Enumeration:
0 : cleared
error cleared
1 : full
RX FIFO full and last entry overwritten, cleared on read
End of enumeration elements list.
RXPE : RX parity error
bits : 2 - 1 (0 bit)
Enumeration:
0 : cleared
error cleared
1 : error
entry on top of RX FIFO has parity error, cleared on read
End of enumeration elements list.
RXFE : RX framing error
bits : 3 - 2 (0 bit)
Enumeration:
0 : cleared
error cleared
1 : error
entry on top of RX FIFO has framing error, cleared on read
End of enumeration elements list.
RXBE : RX break error
bits : 4 - 3 (0 bit)
Enumeration:
0 : cleared
error cleared
1 : error
entry on top of RX FIFO has break error, cleared on read
End of enumeration elements list.
TCFE : TX FIFO empty
bits : 5 - 4 (0 bit)
Enumeration:
0 : cleared
error cleared
1 : error
TX FIFO is empty
End of enumeration elements list.
TXE : TX empty
bits : 6 - 5 (0 bit)
Enumeration:
0 : cleared
error cleared
1 : error
TX shift register and TX FIFO are empty
End of enumeration elements list.
RXE : RX FIFO error
bits : 7 - 6 (0 bit)
Enumeration:
0 : no error
no error in RX FIFO
1 : error
At least one parity, framing or break error active in FIFO
End of enumeration elements list.
FIFO control
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FEN : FIFO enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : disabled
disable RX, TX FIFO
1 : enabled
enable RX, TX FIFO
End of enumeration elements list.
RXFRESET : RX FIFO reset
bits : 1 - 0 (0 bit)
Enumeration:
0 : no action
no action
1 : clear
clear RX FIFO, cleared on read
End of enumeration elements list.
TXFRESET : RX FIFO reset
bits : 2 - 1 (0 bit)
Enumeration:
0 : no action
no action
1 : clear
clear TX FIFO, cleared on read
End of enumeration elements list.
RXFT : RX FIFO Theshold
bits : 6 - 6 (1 bit)
Enumeration:
0 : 1
1 byte in FIFO
1 : 4
4 bytes in FIFO
2 : 8
8 bytes in FIFO
3 : 14
14 bytes in FIFO
End of enumeration elements list.
UART interrupt enable remapped
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXINTEN : RX register data available interrupt enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : disabled
disable interrupt
1 : enabled
enable interrupt
End of enumeration elements list.
TXINTEN : TX register data available interrupt enable
bits : 1 - 0 (0 bit)
Enumeration:
0 : disabled
disable interrupt
1 : enabled
enable interrupt
End of enumeration elements list.
RSINTEN : Receive interrupt enable
bits : 2 - 1 (0 bit)
Enumeration:
0 : disabled
disable interrupt
1 : enabled
enable interrupt
End of enumeration elements list.
MSINTEN : Modem status interrupt enable
bits : 3 - 2 (0 bit)
Enumeration:
0 : disabled
disable interrupt
1 : enabled
enable interrupt
End of enumeration elements list.
UART divisor latch low byte
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DL_L : RX register data available interrupt enable
bits : 0 - 6 (7 bit)
UART divisor latch high byte
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DL_H : Divisor value, high byte
bits : 0 - 6 (7 bit)
UART fractional divisor value
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAC : Fractional divisor value
bits : 0 - 6 (7 bit)
UART interrupt enable
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXINTEN : RX register data available interrupt enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : disable
disable interrupt
1 : enable
enable interrupt
End of enumeration elements list.
TXINTEN : TX register data available interrupt enable
bits : 1 - 0 (0 bit)
Enumeration:
0 : disable
disable interrupt
1 : enable
enable interrupt
End of enumeration elements list.
RSINTEN : Receive interrupt enable
bits : 2 - 1 (0 bit)
Enumeration:
0 : disable
disable interrupt
1 : enable
enable interrupt
End of enumeration elements list.
MSINTEN : Model Status interrupt enable
bits : 3 - 2 (0 bit)
Enumeration:
0 : disable
disable interrupt
1 : enable
enable interrupt
End of enumeration elements list.
UART FIFO status
address_offset : 0x40 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFE : TX FIFO empty
bits : 0 - -1 (0 bit)
Enumeration:
0 : not empty
TX FIFO not empty
1 : empty
TX FIFO empty
End of enumeration elements list.
TXFF : TX FIFO full
bits : 1 - 0 (0 bit)
Enumeration:
0 : not full
TX FIFO not full
1 : full
TX FIFO full
End of enumeration elements list.
RXFE : RX FIFO empty
bits : 2 - 1 (0 bit)
Enumeration:
0 : not empty
RX FIFO not empty
1 : empty
RX FIFO empty
End of enumeration elements list.
RXFF : RX FIFO full
bits : 3 - 2 (0 bit)
Enumeration:
0 : not full
RX FIFO not full
1 : full
RX FIFO full
End of enumeration elements list.
UART interrupt identification
address_offset : 0x8 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UARTINT : UART interrupt
bits : 0 - -1 (0 bit)
Enumeration:
0 : disable
disable interrupt
1 : enable
enable interrupt
End of enumeration elements list.
UARTINTID : UART interrupt type
bits : 1 - 2 (2 bit)
Enumeration:
0 : modem status
modem status
1 : TX hold register empty
TX hold register empty
2 : RX data available
RX data available
3 : RX line status
RX line status
6 : Timeout
Timeout
End of enumeration elements list.
UART Line Control
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BPC : Bit per character
bits : 0 - 0 (1 bit)
Enumeration:
0 : 5
5 bits
1 : 6
6 bits
2 : 7
7 bits
3 : 8
8 bits
End of enumeration elements list.
STB : Stop bits
bits : 2 - 1 (0 bit)
Enumeration:
0 : 1
1 stop bit
1 : 2
2 stop bits (1.5 if BPC=00b)
End of enumeration elements list.
PEN : Parity enable
bits : 3 - 2 (0 bit)
Enumeration:
0 : disabled
parity disabled
1 : enabled
parity enabled
End of enumeration elements list.
EPS : Parity type
bits : 4 - 3 (0 bit)
Enumeration:
0 : odd
generate ODD parity
1 : even
generate EVEN parity
End of enumeration elements list.
SP : Stick parity
bits : 5 - 4 (0 bit)
Enumeration:
0 : disable
disable
1 : enable
enable
End of enumeration elements list.
SB : Break control
bits : 6 - 5 (0 bit)
Enumeration:
0 : normal
normal operation
1 : 0
force TX to 0
End of enumeration elements list.
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