Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SPI Control
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSEN : SPI enable
bits : 0 - -1 (0 bit)
Enumeration:
0 : disable
disable this module
1 : enable
enable this module
End of enumeration elements list.
SIE : SPI interrupt enable
bits : 1 - 0 (0 bit)
Enumeration:
0 : disable
disable interrupts
1 : enable
enable interrupts
End of enumeration elements list.
LPBK : Internal loopback mode
bits : 2 - 1 (0 bit)
Enumeration:
0 : disabled
normal operation
1 : enabled
tie the serial out source to serial in internally (no IO buffers)
End of enumeration elements list.
SE : Slave enable
bits : 3 - 2 (0 bit)
Enumeration:
0 : disabled
SPI is configured as master
1 : enabled
SPI is configured as slave
End of enumeration elements list.
MTRARM : MTRANS re-arm
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
1 : re-arm
re-arms the SOCBCTL.MTRANS operation by de-asserting CSx chip select and returning the master mode state machine to IDLE.
End of enumeration elements list.
MTRANS : Multiple transfer mode
bits : 6 - 5 (0 bit)
Enumeration:
0 : single
Generate single transfers
1 : multiple
Generate multiple transfers
End of enumeration elements list.
MMST_N : Multi-master mode
bits : 7 - 6 (0 bit)
Enumeration:
0 : enabled
Multi-master mode
1 : disabled
Single master mode
End of enumeration elements list.
RTRANS : Auto-retrans on clock error
bits : 8 - 7 (0 bit)
Enumeration:
0 : enabled
Retransmit on clock error
1 : disabled
No retransmit on clock error
End of enumeration elements list.
SPI Status
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPI_INT : SPI interrupt
bits : 0 - -1 (0 bit)
Enumeration:
0 : none
no interrupt
1 : interrupt
interrupt
End of enumeration elements list.
RDOFL : Read buffer overflow
bits : 2 - 1 (0 bit)
Enumeration:
0 : none
no read overflow since bit cleared
1 : overflow
read overflow detected, write 1 to clear
End of enumeration elements list.
LE : Chip select leading edge detect
bits : 3 - 2 (0 bit)
Enumeration:
0 : none
No chip select assertion detected since this bit was cleared
1 : detected
Chip select assertion detected, write 1 to clear
End of enumeration elements list.
UCLK : Underclock condition
bits : 4 - 3 (0 bit)
Enumeration:
0 : none
No underclock detected since this bit was cleared
1 : detected
Underclock condition detected, write 1 to clear
End of enumeration elements list.
CYC_DONE : Cycle done (current transfer is complete)
bits : 5 - 4 (0 bit)
Enumeration:
0 : not done
No cycle done detected since this bit was cleared
1 : completed
Cycle done detected, write one to clear
End of enumeration elements list.
TE : Chip select trailing edge detect
bits : 6 - 5 (0 bit)
Enumeration:
0 : none
No chip select de-assertion detected since this bit was cleared
1 : detected
Chip select de-assertion was detected, write 1 to clear
End of enumeration elements list.
WRUFL : Write buffer underflow
bits : 8 - 7 (0 bit)
Enumeration:
0 : none
No write buffer underflow detected since this bit was cleared
1 : underflow
Write buffer underflow detected, write one to clear
End of enumeration elements list.
TXFULL : Transmit holding register in use
bits : 9 - 8 (0 bit)
Enumeration:
0 : ready
TX transmit holding register ready to accept data word
1 : not ready
TX transmit holding register in use and not ready
End of enumeration elements list.
RXFULL : Receive holding register in use
bits : 10 - 9 (0 bit)
Enumeration:
0 : empty
RX incoming holding register contains no valid data word
1 : full
RX incoming holding register contains a valid data word
End of enumeration elements list.
CURSTATE : Raw status of the SOC bus bridge master state machine's 'current_state' register
bits : 12 - 13 (2 bit)
Enumeration:
0 : IDLE
IDLE
1 : CSSETUP
CSSETUP
2 : TRANSFER
TRANSFER
3 : CSHOLD
CSHOLD
4 : CSWAIT
CSWAIT
5 : CKWAIT
CKWAIT
6 : MTRANS
MTRANS
7 : CSBEGIN
CSBEGIN
End of enumeration elements list.
SPI Chip Select Steering Register
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSNUM : Chip select number
bits : 0 - 0 (1 bit)
Enumeration:
0 : SPICS0
SPICS0
1 : SPICS1
SPICS1
2 : SPICS2
SPICS2
End of enumeration elements list.
CSL : Chip select active high level select
bits : 2 - 1 (0 bit)
Enumeration:
0 : active-low
Active-low outgoing (master) or incoming (slave) chip select
1 : active-high
Active-high outgoing (master) or incoming (slave) ship select
End of enumeration elements list.
CSSETUP : Chip select setup. Minimum number of SPICLK periods to wait from assertion of CS
bits : 8 - 10 (3 bit)
CSHOLD : Chip select hold. Minimum number of SPICLK periods to wait from the last SPICLK transition to de-assertion of CS
bits : 12 - 14 (3 bit)
CSWAIT : Chip select wait. The minimum number of SPICLK periods to wait between the de-assertion of CS
bits : 16 - 18 (3 bit)
CKWAIT : SPI clock wait. Only applies if SPICTL.MTRANS=1b(multiple transfers with one chip select assertion). This value determines the minimum number of SPICLK periods to wait between back-to-back transfers. During this wait time, SPICLK does not toggle but CSx remains active.
bits : 20 - 22 (3 bit)
SPI Data. On READ, retrieve received data word from the incoming holding buffer. On WRITE, write address or data word to the outgoing holding buffer
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : SOC bus bridge data
bits : 0 - 6 (7 bit)
SPI Interrupt Enable
address_offset : 0x20 Bytes (0x0)
size : -1 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDOFL_EN : Read buffer overflow RDOFL interrupt enable
bits : 2 - 1 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.RDOFL interrupt
1 : enable
enable SOCBSTAT.RDOFL interrupt
End of enumeration elements list.
LE_EN : Leading edge detect LE interrupt enable
bits : 3 - 2 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.LE interrupt
1 : enable
enable SOCBSTAT.LE interrupt
End of enumeration elements list.
UCLK_EN : Underclock UCLK interrupt enable
bits : 4 - 3 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.UCLK interrupt
1 : enable
enable SOCBSTAT.UCLK interrupt
End of enumeration elements list.
CYC_DONE_EN : Cycle done CYC_DONE interrupt enable
bits : 5 - 4 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.CYC_DONE interrupt
1 : enable
enable SOCBSTAT.CYC_DONE interrupt
End of enumeration elements list.
TE_EN : Trailing edge detect TE interrupt enable
bits : 6 - 5 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.TE interrupt
1 : enable
enable SOCBSTAT.TE interrupt
End of enumeration elements list.
BP_DONE : Byte packing BP_DONE interrupt enable
bits : 7 - 6 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT. BP_DONE interrupt
1 : enable
enable SOCBSTAT.BP_DONE interrupt
End of enumeration elements list.
WRUFL_EN : Write buffer underflow SOCBSTAT.WRUFL interrupt enable
bits : 8 - 7 (0 bit)
Enumeration:
0 : disable
disable SOCBSTAT.WRUFL interrupt
1 : enable
enable SOCBSTAT.WRUFL interrupt
End of enumeration elements list.
SPI Configuration
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WL : Word length
bits : 0 - 0 (1 bit)
Enumeration:
0 : 8
Word Length = 8-bits
1 : 16
Word Length = 16-bits
2 : 24
Word Length = 24-bits
3 : 32
Word Length = 32-bits
End of enumeration elements list.
MRST : Module reset
bits : 2 - 1 (0 bit)
Enumeration:
0 : disabled
Do not hold module in reset
1 : enabled
Force soft reset of module
End of enumeration elements list.
LB1ST : Least bit first
bits : 3 - 2 (0 bit)
Enumeration:
0 : MSB
MSB is the first serial bit of transfer
1 : LSB
LSB is the first serial bit of transfer
End of enumeration elements list.
CP : Master mode clock polarity
bits : 4 - 3 (0 bit)
Enumeration:
0 : low
SPICLK is low in it's inactive state
1 : high
SPICLK is high in it's inactive state
End of enumeration elements list.
CPH : Master mode clock phase
bits : 5 - 4 (0 bit)
Enumeration:
0 : 1st
First clock transition of a new transfer is used to sample data
1 : 2nd
Second clock transition of a new transfer is used to sample data
End of enumeration elements list.
RCVCP : Slave mode clock polarity
bits : 6 - 5 (0 bit)
Enumeration:
0 : low
SPICLK is low in it's inactive state
1 : high
SPICLK is high in it's inactive state
End of enumeration elements list.
RCVCPH : Slave mode clock phase
bits : 7 - 6 (0 bit)
Enumeration:
0 : 1st
First clock transition of a new transfer used to sample data
1 : 2nd
Second clock transition of a new transfer used to sample data
End of enumeration elements list.
TXDATPH : Early transmit data phase
bits : 9 - 8 (0 bit)
Enumeration:
0 : disabled
Normal transmit data phase, transitions on launch edge of SPICLK
1 : enabled
MISO (slave) or MOSI (Master) transitions occur 1/2 a SPICLK period sooner than normal protocol
End of enumeration elements list.
TDBUF : Transmit double-buffer mode
bits : 10 - 9 (0 bit)
Enumeration:
0 : disabled
Disable double-buffer, legacy operation with single shift register buffer
1 : enabled
Enable double-buffer 'ping-pong' on shift register transmit output path
End of enumeration elements list.
MTURBO : Master turbo operation mode
bits : 11 - 10 (0 bit)
Enumeration:
0 : disabled
Legacy operation down to max 8:1 HCLK:SPICLK ratio
1 : enabled
Enable master turbo mode, using HCLK-based bit count allowing operation down to 2:1 HCLK:SPICLK ratio
End of enumeration elements list.
SPI Clock Divider
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock divisor for SCLK (HCLK / (CLKDIV + 1)*2)
bits : 0 - 14 (15 bit)
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