\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Power Supply Monitor Interrupt Enable
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBAT : Enable Interrupt for VBAT
bits : 0 - 0 (1 bit)
access : read-write
VREGUNDR : Enable Interrupt When VREG Undervoltage: Below 1V
bits : 1 - 1 (1 bit)
access : read-write
VREGOVR : Enable Interrupt When VREG Overvoltage: Above 1.32V
bits : 2 - 2 (1 bit)
access : read-write
RANGEBAT : Battery Monitor Range
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : region1
Configure to generate interrupt if VBAT > 2.75 V
1 : region2
Configure to generate interrupt if VBAT between 2.75 V - 1.6 V
2 : region3
Configure to generate interrupt if VBAT between 2.3 V - 1.6 V
3 : NA
N/A
End of enumeration elements list.
IENBAT : Interrupt Enable for VBAT Range
bits : 10 - 10 (1 bit)
access : read-write
Shutdown Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTINT0 : Wakeup by Interrupt from External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-only
EXTINT1 : Wakeup by Interrupt from External Interrupt 1
bits : 1 - 1 (1 bit)
access : read-only
EXTINT2 : Wakeup by Interrupt from External Interrupt 2
bits : 2 - 2 (1 bit)
access : read-only
RTC : Wakeup by Interrupt from RTC
bits : 3 - 3 (1 bit)
access : read-only
Control for Retention SRAM in Hibernate Mode
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BNK1EN : Enable Retention Bank 1 (8kB)
bits : 0 - 0 (1 bit)
access : read-write
BNK2EN : Enable Retention Bank 2 (16kB)
bits : 1 - 1 (1 bit)
access : read-write
Power Supply Monitor Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATUNDR : Status Bit Indicating an Alarm That Battery is Below 1.8V
bits : 0 - 0 (1 bit)
access : read-write
VREGUNDR : Status Bit for Alarm Indicating VREG is Below 1V
bits : 1 - 1 (1 bit)
access : read-write
VREGOVR : Status Bit for Alarm Indicating Overvoltage for VREG
bits : 2 - 2 (1 bit)
access : read-write
WICENACK : WIC Enable Acknowledge from Cortex
bits : 7 - 7 (1 bit)
access : read-only
RANGE1 : VBAT Range1 (> 2.75v)
bits : 8 - 8 (1 bit)
access : read-write
RANGE2 : VBAT Range2 (2.75v - 2.3v)
bits : 9 - 9 (1 bit)
access : read-write
RANGE3 : VBAT Range3 (2.3v - 1.6v)
bits : 10 - 10 (1 bit)
access : read-write
RORANGE1 : VBAT Range1 (> 2.75v)
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : batstat1
VBAT not in the range specified
1 : batstat0
VBAT in the range specified
End of enumeration elements list.
RORANGE2 : VBAT Range2 (2.75v - 2.3v)
bits : 14 - 14 (1 bit)
access : read-only
RORANGE3 : VBAT Range3 (2.3v - 1.6v)
bits : 15 - 15 (1 bit)
access : read-only
Reset Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POR : Power-on-Reset
bits : 0 - 0 (1 bit)
access : read-write
EXTRST : External Reset
bits : 1 - 1 (1 bit)
access : read-write
WDRST : Watchdog Time-out Reset
bits : 2 - 2 (1 bit)
access : read-write
SWRST : Software Reset
bits : 3 - 3 (1 bit)
access : read-write
PORSRC : Power-on-Reset Source
bits : 4 - 5 (2 bit)
access : read-only
Enumeration:
0 : FAILSAFE_HV
POR triggered because VBAT drops below Fail Safe
1 : RST_VBAT
POR trigger because VBAT supply (VBAT < 1.7 V)
2 : RST_VREG
POR triggered because VDD supply (VDD < 1.08 V)
3 : FAILSAFE_LV
POR triggered because VREG drops below Fail Safe
End of enumeration elements list.
HP Buck Control
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPBUCKEN : Enable HP Buck
bits : 0 - 0 (1 bit)
access : read-write
Power Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Power Mode Bits
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : FLEXI
Flexi Mode
2 : HIBERNATE
Hibernate Mode
3 : SHUTDOWN
Shutdown Mode
End of enumeration elements list.
MONVBATN : Monitor VBAT During Hibernate Mode. Monitors VBAT by Default
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : VBAT_MONEN
VBAT monitor enabled in PMG block.
1 : VBAT_MONDIS
VBAT monitor disabled in PMG block.
End of enumeration elements list.
Key Protection for PMG_PWRMOD and PMG_SRAMRET
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Power Control Key Register
bits : 0 - 15 (16 bit)
access : write-only
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