\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Watchdog Timer Load Value
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOAD : WDT Load Value
bits : 0 - 15 (16 bit)
access : read-write
Timer Status
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQ : WDT Interrupt
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : Cleared
Watchdog Timer Interrupt Not Pending
1 : Pending
Watchdog Timer Interrupt Pending
End of enumeration elements list.
CLRI : WDTCLRI Write Status
bits : 1 - 1 (1 bit)
access : read-only
TLD : WDTVAL Write Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : Sync_Complete
Arm and AFE Watchdog Clock Domains WDTLD values match
1 : Sync_In_Progress
Synchronize In Progress
End of enumeration elements list.
CON : WDTCON Write Status
bits : 3 - 3 (1 bit)
access : read-only
LOCK : Lock Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : Open
Timer Operation Not Locked
1 : Locked
Timer Enabled and Locked
End of enumeration elements list.
OTPWRDONE : Reset Type Status
bits : 5 - 5 (1 bit)
access : read-only
TMINLD : WDTMINLD Write Status
bits : 6 - 6 (1 bit)
access : read-only
RESERVED_15_7 : RESERVED
bits : 7 - 15 (9 bit)
access : read-write
Minimum Load Value
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIN_LOAD : WDT Min Load Value
bits : 0 - 15 (16 bit)
access : read-write
Current Count Value
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCOUNT : Current WDT Count Value.
bits : 0 - 15 (16 bit)
access : read-only
Watchdog Timer Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDSTOP : Power Down Stop Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Continue
Continue Counting When In Hibernate
1 : Stop
Stop Counter When In Hibernate.
End of enumeration elements list.
IRQ : WDT Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : Reset
Watchdog Timer timeout creates a reset.
1 : Interrupt
Watchdog Timer timeout creates an interrupt instead of reset.
End of enumeration elements list.
PRE : Prescaler.
bits : 2 - 3 (2 bit)
access : read-write
EN : Timer Enable
bits : 5 - 5 (1 bit)
access : read-write
MDE : Timer Mode Select
bits : 6 - 6 (1 bit)
access : read-write
Reserved1_7 : Reserved
bits : 7 - 7 (1 bit)
access : read-only
CLKDIV2 : Clock Source
bits : 8 - 8 (1 bit)
access : read-write
MINLOAD_EN : Timer Window Control
bits : 9 - 9 (1 bit)
access : read-write
WDTIRQEN : WDT Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
RESERVED_15_11 : RESERVED
bits : 11 - 15 (5 bit)
access : read-write
Refresh Watchdog Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRWDG : Refresh Register
bits : 0 - 15 (16 bit)
access : write-only
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