\n
address_offset : 0x0 Bytes (0x0)
size : 0x800 byte (0x0)
mem_usage : registers
protection : not protected
AFE Configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HPREFDIS : Disable High Power Reference
bits : 5 - 5 (1 bit)
access : read-write
DACEN : High Power DAC Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : Off
High Power DAC Disabled
1 : On
High Power DAC Enabled
End of enumeration elements list.
ADCEN : ADC Power Enable
bits : 7 - 7 (1 bit)
access : read-write
ADCCONVEN : ADC Conversion Start Enable
bits : 8 - 8 (1 bit)
access : read-write
EXBUFEN : Enable Excitation Buffer
bits : 9 - 9 (1 bit)
access : read-write
INAMPEN : Enable Excitation Amplifier
bits : 10 - 10 (1 bit)
access : read-write
TIAEN : High Power TIA Enable
bits : 11 - 11 (1 bit)
access : read-write
TEMPSENSEN0 : ADC Temperature Sensor Channel Enable
bits : 12 - 12 (1 bit)
access : read-write
TEMPCONVEN : ADC Temp Sensor Convert Enable
bits : 13 - 13 (1 bit)
access : read-write
WAVEGENEN : Waveform Generator Enable
bits : 14 - 14 (1 bit)
access : read-write
DFTEN : DFT Hardware Accelerator Enable
bits : 15 - 15 (1 bit)
access : read-write
SINC2EN : ADC Output 50/60Hz Filter Enable
bits : 16 - 16 (1 bit)
access : read-write
ALDOILIMITEN : Analog LDO Current Limiting Enable
bits : 19 - 19 (1 bit)
access : read-write
DACREFEN : High Speed DAC Reference Enable
bits : 20 - 20 (1 bit)
access : read-write
DACBUFEN : Enable DC DAC Buffer
bits : 21 - 21 (1 bit)
access : read-write
High Speed DAC Configuration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTENEN : PGA Stage Gain Attenuation
bits : 0 - 0 (1 bit)
access : read-write
RATE : DAC Update Rate
bits : 1 - 8 (8 bit)
access : read-write
INAMPGNMDE : Excitation Amplifier Gain Control
bits : 12 - 12 (1 bit)
access : read-write
DAC DC Buffer Configuration
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Reserved_0 : Reserved
bits : 0 - 0 (1 bit)
access : read-write
CHANSEL : DAC DC Channel Selection
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : Chan0
ULPDAC0 Sets DC level
1 : Chan1
ULPDAC1 Sets DC level
End of enumeration elements list.
LPDAC Data-out
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACIN12 : 12BITVAL, 1LSB=537uV
bits : 0 - 11 (12 bit)
access : read-write
DACIN6 : 6BITVAL, 1LSB=34.375mV
bits : 12 - 17 (6 bit)
access : read-write
LPDAC0 Switch Control
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPDACSW : LPDAC0 Switches Matrix
bits : 0 - 4 (5 bit)
access : read-write
LPMODEDIS : Switch Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DACCONBIT5
ULPDAC Switch controlled by ULPDACCON0 bit 5
1 : OVRRIDE
ULPDAC Switches override
End of enumeration elements list.
LPDAC Control Bits
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTEN : Enable Writes to ULPDAC0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : WRITEDIS
Disable ULPDAC0 Writes
1 : WRITEEN
Enable ULPDAC0 Writes
End of enumeration elements list.
PWDEN : LPDAC0 Power Down
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PWREN
ULPDAC0 Powered On
1 : PWRDIS
ULPDAC0 Powered Off
End of enumeration elements list.
REFSEL : Reference Select Bit
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ULPREF
ULP2P5V Ref
1 : AVDD
AVDD Reference
End of enumeration elements list.
VBIASMUX : VBIAS MUX Select
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : 12BIT
Output 12Bit
1 : EN
output 6Bit
End of enumeration elements list.
VZEROMUX : VZERO MUX Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BITS6
VZERO 6BIT
1 : BITS12
VZERO 12BIT
End of enumeration elements list.
DACMDE : LPDAC0 Switch Settings
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NORM
ULPDAC0 switches set for normal mode
1 : DIAG
ULPDAC0 switches set for Diagnostic mode
End of enumeration elements list.
WAVETYPE : LPDAC Data Source
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : MMR
Direct from ULPDACDAT0
1 : WAVEGEN
Waveform generator
End of enumeration elements list.
Low Power DAC1 data register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACIN12 : 12BITVAL, 1LSB=537uV
bits : 0 - 11 (12 bit)
access : read-write
DACIN6 : 6BITVAL, 1LSB=34.375mV
bits : 12 - 17 (6 bit)
access : read-write
Control register for switches to LPDAC1
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPDACSW : ULPDAC0 Switches Matrix
bits : 0 - 4 (5 bit)
access : read-write
LPMODEDIS : Switch Control
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DACCONBIT5
ULPDAC Switch controlled by ULPDACCON1 bit 5
1 : OVRRIDE
ULPDAC Switches override
End of enumeration elements list.
ULP_DACCON1
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RSTEN : Enable Writes to ULPDAC1
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : WRITEDIS
Disable ULPDAC1 Writes
1 : WRITEEN
Enable ULPDAC1 Writes
End of enumeration elements list.
PWDEN : ULPDAC0 Power
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : PWREN
ULPDAC1 Powered On
1 : PWRDIS
ULPDAC1 Powered Off
End of enumeration elements list.
REFSEL : REFSEL
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : ULPREF
Unknown
1 : AVDD
Unknown
End of enumeration elements list.
VBIASMUX : BITSEL
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DIS
12BIT Output
1 : EN
6BIT Output
End of enumeration elements list.
VZEROMUX : VZEROOUT
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : BITS6
VZERO 6BIT
1 : BITS12
VZERO 12BIT
End of enumeration elements list.
DACMDE : LPDAC1 Switch Settings
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NORM
ULPDAC1 switches set for normal mode
1 : DIAG
ULPDAC1 switches set for Diagnostic mode
End of enumeration elements list.
WAVETYPE : DAC Input Source
bits : 6 - 6 (1 bit)
access : read-write
Waveform Generator Configuration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TYPESEL : Selects the Type of Waveform
bits : 1 - 2 (2 bit)
access : read-write
DACOFFSETCAL : Bypass DAC Offset
bits : 4 - 4 (1 bit)
access : read-write
DACGAINCAL : Bypass DAC Gain
bits : 5 - 5 (1 bit)
access : read-write
Switch Matrix Full Configuration (D)
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DR0 : Control of Dr0 Switch.
bits : 0 - 0 (1 bit)
access : read-write
D2 : Control of D2 Switch.
bits : 1 - 1 (1 bit)
access : read-write
D3 : Control of D3 Switch.
bits : 2 - 2 (1 bit)
access : read-write
D4 : Control of D4 Switch.
bits : 3 - 3 (1 bit)
access : read-write
D5 : Control of D5 Switch.
bits : 4 - 4 (1 bit)
access : read-write
D6 : Control of D6 Switch.
bits : 5 - 5 (1 bit)
access : read-write
D7 : Control of D7 Switch.
bits : 6 - 6 (1 bit)
access : read-write
D8 : Control of D8 Switch.
bits : 7 - 7 (1 bit)
access : read-write
Switch Matrix Full Configuration (N)
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
N1 : Control of N1 Switch. Set Will Close N1, Unset Open
bits : 0 - 0 (1 bit)
access : read-write
N2 : Control of N2 Switch. Set Will Close N2, Unset Open
bits : 1 - 1 (1 bit)
access : read-write
N3 : Control of N3 Switch. Set Will Close N3, Unset Open
bits : 2 - 2 (1 bit)
access : read-write
N4 : Control of N4 Switch. Set Will Close N4, Unset Open
bits : 3 - 3 (1 bit)
access : read-write
N5 : Control of N5 Switch. Set Will Close N5, Unset Open
bits : 4 - 4 (1 bit)
access : read-write
N6 : Control of N6 Switch. Set Will Close N6, Unset Open
bits : 5 - 5 (1 bit)
access : read-write
N7 : Control of N7 Switch. Set Will Close N7, Unset Open
bits : 6 - 6 (1 bit)
access : read-write
N8 : Control of N8 Switch. Set Will Close N8, Unset Open
bits : 7 - 7 (1 bit)
access : read-write
N9 : Control of N9 Switch. Set Will Close N9, Unset Open
bits : 8 - 8 (1 bit)
access : read-write
NR1 : Control of Nr1 Switch. Set Will Close Nr1, Unset Open
bits : 9 - 9 (1 bit)
access : read-write
Nl : Control of NL Switch.
bits : 10 - 10 (1 bit)
access : read-write
NL2 : Control of NL2 Switch.
bits : 11 - 11 (1 bit)
access : read-write
Switch Matrix Full Configuration (P)
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR0 : PR0 Switch Control
bits : 0 - 0 (1 bit)
access : read-write
P2 : Control of P2 Switch. Set Will Close P2, Unset Open
bits : 1 - 1 (1 bit)
access : read-write
P3 : Control of P3 Switch. Set Will Close P3, Unset Open
bits : 2 - 2 (1 bit)
access : read-write
P4 : Control of P4 Switch. Set Will Close P4, Unset Open
bits : 3 - 3 (1 bit)
access : read-write
P5 : Control of P5 Switch. Set Will Close P5, Unset Open
bits : 4 - 4 (1 bit)
access : read-write
P6 : Control of P6 Switch. Set Will Close P6, Unset Open
bits : 5 - 5 (1 bit)
access : read-write
P7 : Control of P7 Switch. Set Will Close P7, Unset Open
bits : 6 - 6 (1 bit)
access : read-write
P8 : Control of P8 Switch. Set Will Close P8, Unset Open
bits : 7 - 7 (1 bit)
access : read-write
P9 : Control of P9 Switch. Set Will Close P9, Unset Open
bits : 8 - 8 (1 bit)
access : read-write
P10 : P10 Switch Control
bits : 9 - 9 (1 bit)
access : read-write
P11 : Control of P11 Switch. Set Will Close P11, Unset Open
bits : 10 - 10 (1 bit)
access : read-write
P12 : Control of P12 Switch. Set Will Close P12, Unset Open
bits : 11 - 11 (1 bit)
access : read-write
PL : PL Switch Control
bits : 13 - 13 (1 bit)
access : read-write
PL2 : PL2 Switch Control
bits : 14 - 14 (1 bit)
access : read-write
Switch Matrix Full Configuration (T)
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T1 : Control of T1 Switch. Set Will Close T1, Unset Open
bits : 0 - 0 (1 bit)
access : read-write
T2 : Control of T2 Switch. Set Will Close T2, Unset Open
bits : 1 - 1 (1 bit)
access : read-write
T3 : Control of T3 Switch. Set Will Close T3, Unset Open
bits : 2 - 2 (1 bit)
access : read-write
T4 : Control of T4 Switch. Set Will Close T4, Unset Open
bits : 3 - 3 (1 bit)
access : read-write
T5 : Control of T5 Switch. Set Will Close T5, Unset Open
bits : 4 - 4 (1 bit)
access : read-write
T7 : Control of T7 Switch. Set Will Close T7, Unset Open
bits : 6 - 6 (1 bit)
access : read-write
T9 : Control of T9 Switch. Set Will Close T9, Unset Open
bits : 8 - 8 (1 bit)
access : read-write
T10 : Control of T10 Switch. Set Will Close T10, Unset Open
bits : 9 - 9 (1 bit)
access : read-write
T11 : Control of T11 Switch. Set Will Close T11, Unset Open
bits : 10 - 10 (1 bit)
access : read-write
TR1 : Control of Tr1 Switch. Set Will Close Tr1, Unset Open
bits : 11 - 11 (1 bit)
access : read-write
Temp Sensor Configuration
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Unused
bits : 0 - 0 (1 bit)
access : read-write
CHOPCON : Temp Sensor Chop Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable chop
1 : EN
Enable chop
End of enumeration elements list.
CHOPFRESEL : Chop Mode Frequency Setting
bits : 2 - 3 (2 bit)
access : read-write
HP and LP Buffer Control
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
V1P8HPADCEN : HP 1.8V Reference Buffer
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HPBUF_DIS
Disable 1.8V HP ADC Reference Buffer
1 : HPBUF_EN
Enable 1.8V HP ADC Reference Buffer
End of enumeration elements list.
V1P8HPADCILIMITEN : HP ADC Input Current Limit
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : Limit_Dis
Disable buffer Current Limit
1 : Limit_En
Enable buffer Current Limit
End of enumeration elements list.
V1P8LPADCEN : ADC 1.8V LP Reference Buffer
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : LPADCREF_DIS
Disable LP 1.8V Reference Buffer
1 : LPADCREF_EN
Enable LP 1.8V Reference Buffer
End of enumeration elements list.
V1P8HPADCCHGDIS : Controls Decoupling Cap Discharge Switch
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : Open
Open switch
1 : Closed
Close Switch
End of enumeration elements list.
V1P1HPADCEN : Enable 1.1V HP CM Buffer
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : Off
Disable 1.1V HP Common Mode Buffer
1 : On
Enable 1.1V HP Common Mode Buffer
End of enumeration elements list.
V1P1LPADCEN : ADC 1.1V LP Buffer
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : Disable
Disable ADC 1.8V LP Reference Buffer
1 : Enable
Enable ADC 1.8V LP Reference Buffer
End of enumeration elements list.
V1P1LPADCCHGDIS : Controls Decoupling Cap Discharge Switch
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : EnChrg
Open switch
1 : DisChrg
Close Switch
End of enumeration elements list.
V1P8THERMSTEN : Buffered Reference Output
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable 1.8V Buffered Reference output
1 : EN
Enable 1.8V Buffered Reference output
End of enumeration elements list.
ADC Configuration
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MUXSELP : Select Positive Input
bits : 0 - 5 (6 bit)
access : read-write
MUXSELN : Select Negative Input
bits : 8 - 12 (5 bit)
access : read-write
GNOFFSEL : Obsolete
bits : 13 - 14 (2 bit)
access : read-write
GNOFSELPGA : Internal Offset/Gain Cancellation
bits : 15 - 15 (1 bit)
access : read-write
GNPGA : PGA Gain Setup
bits : 16 - 18 (3 bit)
access : read-write
Switch Matrix Status (D)
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D1STA : Status of Dr0 Switch.
bits : 0 - 0 (1 bit)
access : read-only
D2STA : Status of D2 Switch.
bits : 1 - 1 (1 bit)
access : read-only
D3STA : Status of D3 Switch.
bits : 2 - 2 (1 bit)
access : read-only
D4STA : Status of D4 Switch.
bits : 3 - 3 (1 bit)
access : read-only
D5STA : Status of D5 Switch.
bits : 4 - 4 (1 bit)
access : read-only
D6STA : Status of D6 Switch.
bits : 5 - 5 (1 bit)
access : read-only
D7STA : Status of D7 Switch.
bits : 6 - 6 (1 bit)
access : read-only
D8STA : Status of D8 Switch.
bits : 7 - 7 (1 bit)
access : read-only
Switch Matrix Status (P)
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR0STA : PR0 Switch Control
bits : 0 - 0 (1 bit)
access : read-only
P2STA : Status of P2 Switch.
bits : 1 - 1 (1 bit)
access : read-only
P3STA : Status of P3 Switch.
bits : 2 - 2 (1 bit)
access : read-only
P4STA : Status of P4 Switch.
bits : 3 - 3 (1 bit)
access : read-only
P5STA : Status of P5 Switch.
bits : 4 - 4 (1 bit)
access : read-only
P6STA : Status of P6 Switch.
bits : 5 - 5 (1 bit)
access : read-only
P7STA : Status of P7 Switch.
bits : 6 - 6 (1 bit)
access : read-only
P8STA : Status of P8 Switch.
bits : 7 - 7 (1 bit)
access : read-only
P9STA : Status of P9 Switch.
bits : 8 - 8 (1 bit)
access : read-only
P10STA : Status of P10 Switch.
bits : 9 - 9 (1 bit)
access : read-only
P11STA : Status of P11 Switch.
bits : 10 - 10 (1 bit)
access : read-only
P12STA : Status of P12 Switch.
bits : 11 - 11 (1 bit)
access : read-only
P13STA : Status of P13 Switch.
bits : 12 - 12 (1 bit)
access : read-only
PLSTA : PL Switch Control
bits : 13 - 13 (1 bit)
access : read-only
PL2STA : PL Switch Control
bits : 14 - 14 (1 bit)
access : read-only
Switch Matrix Status (N)
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
N1STA : Status of N1 Switch.
bits : 0 - 0 (1 bit)
access : read-only
N2STA : Status of N2 Switch.
bits : 1 - 1 (1 bit)
access : read-only
N3STA : Status of N3 Switch.
bits : 2 - 2 (1 bit)
access : read-only
N4STA : Status of N4 Switch.
bits : 3 - 3 (1 bit)
access : read-only
N5STA : Status of N5 Switch.
bits : 4 - 4 (1 bit)
access : read-only
N6STA : Status of N6 Switch.
bits : 5 - 5 (1 bit)
access : read-only
N7STA : Status of N7 Switch.
bits : 6 - 6 (1 bit)
access : read-only
N8STA : Status of N8 Switch.
bits : 7 - 7 (1 bit)
access : read-only
N9STA : Status of N9 Switch.
bits : 8 - 8 (1 bit)
access : read-only
NR1STA : Status of NR1 Switch.
bits : 9 - 9 (1 bit)
access : read-only
NLSTA : Status of NL Switch.
bits : 10 - 10 (1 bit)
access : read-only
NL2STA : Status of NL2 Switch.
bits : 11 - 11 (1 bit)
access : read-only
Switch Matrix Status (T)
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T1STA : Status of T1 Switch.
bits : 0 - 0 (1 bit)
access : read-only
T2STA : Status of T2 Switch.
bits : 1 - 1 (1 bit)
access : read-only
T3STA : Status of T3 Switch.
bits : 2 - 2 (1 bit)
access : read-only
T4STA : Status of T4 Switch.
bits : 3 - 3 (1 bit)
access : read-only
T5STA : Status of T5 Switch.
bits : 4 - 4 (1 bit)
access : read-only
T6STA : Status of T6 Switch.
bits : 5 - 5 (1 bit)
access : read-only
T7STA : Status of T7 Switch.
bits : 6 - 6 (1 bit)
access : read-only
T8STA : Status of T8 Switch.
bits : 7 - 7 (1 bit)
access : read-only
T9STA : Status of T9 Switch.
bits : 8 - 8 (1 bit)
access : read-only
T10STA : Status of T10 Switch.
bits : 9 - 9 (1 bit)
access : read-only
T11STA : Status of T11 Switch.
bits : 10 - 10 (1 bit)
access : read-only
TR1STA : Status of TR1 Switch.
bits : 11 - 11 (1 bit)
access : read-only
Variance Output
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VARIANCE : Statistical Variance Value
bits : 0 - 30 (31 bit)
access : read-only
Statistics Control
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATSEN : Statistics Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable Statistics
1 : EN
Enable Statistics
End of enumeration elements list.
RESRVED : Reserved
bits : 1 - 3 (3 bit)
access : read-write
SAMPLENUM : Sample Size
bits : 4 - 6 (3 bit)
access : read-write
STDDEV : Standard Deviation Configuration
bits : 7 - 11 (5 bit)
access : read-write
Statistics Mean Output
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEAN : Mean Output
bits : 0 - 15 (16 bit)
access : read-only
REPEAT ADC Conversions
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable Repeat ADC Conversions
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : Dis
Disable Repeat ADC Conversions
1 : En
Enable Repeat ADC Conversions
End of enumeration elements list.
NUM : Repeat Value
bits : 4 - 11 (8 bit)
access : read-write
Calibration Data Lock
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY : Password for Calibration Data Registers
bits : 0 - 31 (32 bit)
access : read-write
ADC Offset Calibration High Speed TIA Channel
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : HPTIA Offset Calibration
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration Temp Sensor Channel
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration Temp Sensor Channel
bits : 0 - 14 (15 bit)
access : read-write
ADC Offset Calibration Temp Sensor Channel 0
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Temp Sensor
bits : 0 - 14 (15 bit)
access : read-write
ADCPGAGN1: ADC Gain Calibration Auxiliary Input Channel
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration PGA Gain 1x
bits : 0 - 14 (15 bit)
access : read-write
ADC Offset Calibration Auxiliary Channel (PGA Gain=1)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Gain1
bits : 0 - 14 (15 bit)
access : read-write
DACGAIN
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : HS DAC Gain Correction Factor
bits : 0 - 11 (12 bit)
access : read-write
DAC Offset with Attenuator Enabled (LP Mode)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : DAC Offset Correction Factor
bits : 0 - 11 (12 bit)
access : read-write
DAC Offset with Attenuator Disabled (LP Mode)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : DAC Offset Correction Factor
bits : 0 - 11 (12 bit)
access : read-write
ADC Gain Calibration Auxiliary Input Channel (PGA Gain=1.5)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration PGA Gain 1.5x
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration Auxiliary Input Channel (PGA Gain=2)
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration PGA Gain 2x
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration Auxiliary Input Channel (PGA Gain=4)
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration PGA Gain 4x
bits : 0 - 14 (15 bit)
access : read-write
ADC Offset Cancellation (Optional)
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OFFSETCANCEL : Offset Cancellation
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration for HS TIA Channel
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Error Calibration HS TIA Channel
bits : 0 - 14 (15 bit)
access : read-write
ADC Offset Calibration ULP-TIA0 Channel
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration for ULP-TIA0
bits : 0 - 14 (15 bit)
access : read-write
ADC GAIN Calibration for LP TIA0 Channel
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Error Calibration ULPTIA0
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration with DC Cancellation(PGA G=4)
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCGAINAUX : DC Calibration Gain=4
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration Auxiliary Input Channel (PGA Gain=9)
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration PGA Gain 9x
bits : 0 - 14 (15 bit)
access : read-write
ADC Offset Calibration Temp Sensor Channel 1
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Temp Sensor
bits : 0 - 14 (15 bit)
access : read-write
ADC Gain Calibration Temperature Sensor Channel
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gain Calibration for Diode Temp Sensor
bits : 0 - 14 (15 bit)
access : read-write
DAC Offset with Attenuator Enabled (HP Mode)
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : DAC Offset Correction Factor
bits : 0 - 11 (12 bit)
access : read-write
DAC Offset with Attenuator Disabled (HP Mode)
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : DAC Offset Correction Factor
bits : 0 - 11 (12 bit)
access : read-write
ADC Offset Calibration LP TIA1 Channel
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration for ULP-TIA1
bits : 0 - 14 (15 bit)
access : read-write
ADC GAIN Calibration for LP TIA1 Channel
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULPTIA1GN : Gain Calibration ULP-TIA1
bits : 0 - 14 (15 bit)
access : read-write
Offset Calibration Auxiliary Channel (PGA Gain =2)
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Auxiliary Channel (PGA Gain =2)
bits : 0 - 14 (15 bit)
access : read-write
Offset Calibration Auxiliary Channel (PGA Gain =1.5)
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Gain1.5
bits : 0 - 14 (15 bit)
access : read-write
Offset Calibration Auxiliary Channel (PGA Gain =9)
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Gain9
bits : 0 - 14 (15 bit)
access : read-write
Offset Calibration Auxiliary Channel (PGA Gain =4)
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Offset Calibration Gain4
bits : 0 - 14 (15 bit)
access : read-write
Power Mode Configuration
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSHP : Set High Speed DAC and ADC in High Power Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : LP
LP mode
1 : HP
HP mode
End of enumeration elements list.
SYSBW : Configure System Bandwidth
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : BWNA
no action for system configuration
1 : BW50
50kHz -3dB bandwidth
2 : BW100
100kHz -3dB bandwidth
3 : BW250
250kHz -3dB bandwidth
End of enumeration elements list.
Waveform Generator - Sinusoid Frequency Control Word
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINEFCW : Sinusoid Generator Frequency Control Word
bits : 0 - 23 (24 bit)
access : read-write
Waveform Generator - Sinusoid Phase Offset
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINEOFFSET : Sinusoid Phase Offset
bits : 0 - 19 (20 bit)
access : read-write
Switch Mux for ECG
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWMUX : ECG Swmux Control
bits : 0 - 2 (3 bit)
access : read-write
CMMUX : CM Resistor Select for Ain2, Ain3
bits : 3 - 3 (1 bit)
access : read-write
AFE_TEMPSEN_DIO
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISWCON : Bias Current Selection
bits : 0 - 15 (16 bit)
access : read-write
EN : Test Signal Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : On
Turn On
1 : Off
Turn Off
End of enumeration elements list.
PWD : Power Down Control
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : Active
Unknown
1 : PowerDown
Unknown
End of enumeration elements list.
Waveform Generator - Sinusoid Offset
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINEOFFSET : Sinusoid Offset
bits : 0 - 11 (12 bit)
access : read-write
DAC Test
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPFBYPEN : Bypass Low Pass Filter Between Dac and Buffer
bits : 2 - 2 (1 bit)
access : read-write
Configure ADC Input Buffer
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHOPDIS : Disable Chop
bits : 0 - 3 (4 bit)
access : read-write
AMPDIS : Disable OpAmp.
bits : 4 - 8 (5 bit)
access : read-write
Waveform Generator - Sinusoid Amplitude
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SINEAMPLITUDE : Sinusoid Amplitude
bits : 0 - 10 (11 bit)
access : read-write
ADC Output Filters Configuration
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCCLK : ADC Data Rate
bits : 0 - 0 (1 bit)
access : read-write
LPFBYPEN : 50/60Hz Low Pass Filter
bits : 4 - 4 (1 bit)
access : read-write
SINC3BYP : SINC3 Filter Bypass
bits : 6 - 6 (1 bit)
access : read-write
AVRGEN : Average Function Enable
bits : 7 - 7 (1 bit)
access : read-write
SINC2OSR : SINC2 OSR
bits : 8 - 11 (4 bit)
access : read-write
SINC3OSR : SINC3 OSR
bits : 12 - 13 (2 bit)
access : read-write
AVRGNUM : Number of Samples Averaged
bits : 14 - 15 (2 bit)
access : read-write
SINC2CLKENB : SINC2 Filter Clock Enable
bits : 16 - 16 (1 bit)
access : read-write
DACWAVECLKENB : DAC Wave Clock Enable
bits : 17 - 17 (1 bit)
access : read-write
DFTCLKENB : DFT Clock Enable
bits : 18 - 18 (1 bit)
access : read-write
HS DAC Code
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DACDAT : DAC Code
bits : 0 - 11 (12 bit)
access : read-write
LPREF_BUF_CON
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPREFDIS : Set This Bit Will Power Down Low Power Bandgap
bits : 0 - 0 (1 bit)
access : read-write
LPBUF2P5DIS : Low Power Bandgap's Output Buffer
bits : 1 - 1 (1 bit)
access : read-write
BOOSTCURRENT : Set: Drive 2 Dac Unset Drive 1 Dac, and Save Power
bits : 2 - 2 (1 bit)
access : read-write
ADC Raw Result
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : ADC Result
bits : 0 - 15 (16 bit)
access : read-write
DFT Result, Real Part
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DFT Real
bits : 0 - 17 (18 bit)
access : read-write
DFT Result, Imaginary Part
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : DFT Imaginary
bits : 0 - 17 (18 bit)
access : read-write
Supply Rejection Filter Result
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : LPF Result
bits : 0 - 15 (16 bit)
access : read-write
Temperature Sensor Result
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Temp Sensor
bits : 0 - 15 (16 bit)
access : read-write
ADC Interrupt Enable Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCRDYIEN : ADCDAT Ready Interrupt
bits : 0 - 0 (1 bit)
access : read-write
DFTRDYIEN : DFT Result Ready Interrupt
bits : 1 - 1 (1 bit)
access : read-write
SINC2RDYIEN : Low Pass Filter Result Interrupt
bits : 2 - 2 (1 bit)
access : read-write
TEMPRDYIEN : Temp Sensor Interrupt
bits : 3 - 3 (1 bit)
access : read-write
ADCMINFAILIEN : ADCMIN Interrupt
bits : 4 - 4 (1 bit)
access : read-write
ADCMAXFAILIEN : ADCMAX Interrupt
bits : 5 - 5 (1 bit)
access : read-write
ADCDELTAFAILIEN : Delta Interrupt
bits : 6 - 6 (1 bit)
access : read-write
MEANIEN : Mean Interrupt
bits : 7 - 7 (1 bit)
access : read-write
VARIEN : Variance Interrupt
bits : 8 - 8 (1 bit)
access : read-write
ADC Interrupt Status
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADCRDY : ADC Result Ready Status
bits : 0 - 0 (1 bit)
access : read-write
DFTRDY : DFT Result Ready Status
bits : 1 - 1 (1 bit)
access : read-write
SINC2RDY : Low Pass Filter Result Status
bits : 2 - 2 (1 bit)
access : read-write
TEMPRDY : Temp Sensor Result Ready
bits : 3 - 3 (1 bit)
access : read-write
ADCMINERR : ADC Minimum Value
bits : 4 - 4 (1 bit)
access : read-write
ADCMAXERR : ADC Maximum Value
bits : 5 - 5 (1 bit)
access : read-write
ADCDIFFERR : ADC Delta Ready
bits : 6 - 6 (1 bit)
access : read-write
MEANRDY : Mean Result Ready
bits : 7 - 7 (1 bit)
access : read-write
VARRDY : Variance Result Ready
bits : 8 - 8 (1 bit)
access : read-write
Analog Generation Interrupt
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CUSTOMIRQ0 : Custom IRQ 0
bits : 0 - 0 (1 bit)
access : read-write
CUSTOMIRQ1 : Custom IRQ 1.
bits : 1 - 1 (1 bit)
access : read-write
CUSTOMIRQ2 : Custom IRQ 2
bits : 2 - 2 (1 bit)
access : read-write
CUSTOMIRQ3 : Custom IRQ 3.
bits : 3 - 3 (1 bit)
access : read-write
ADC Minimum Value Check
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MINVAL : ADC Minimum Value Threshold
bits : 0 - 15 (16 bit)
access : read-write
ADCMIN Hysteresis Value
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MINCLRVAL : ADCMIN Hysteresis Value
bits : 0 - 15 (16 bit)
access : read-write
ADC Maximum Value Check
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXVAL : ADC Max Threshold
bits : 0 - 15 (16 bit)
access : read-write
ADCMAX Hysteresis Value
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXSWEN : ADCMAX Hysteresis Value
bits : 0 - 15 (16 bit)
access : read-write
ADC Delta Value
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELTAVAL : ADCDAT Code Differences Limit Option
bits : 0 - 15 (16 bit)
access : read-write
HPOSC Configuration
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLK32MHZEN : 16M/32M Output Selector Signal.
bits : 2 - 2 (1 bit)
access : read-write
Switch Matrix Configuration
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMUXCON : Control of D Switch MUX
bits : 0 - 3 (4 bit)
access : read-write
PMUXCON : Control of P Switch MUX
bits : 4 - 7 (4 bit)
access : read-write
NMUXCON : Control of N Switch MUX
bits : 8 - 11 (4 bit)
access : read-write
TMUXCON : Control of T Switch MUX.
bits : 12 - 15 (4 bit)
access : read-write
SWSOURCESEL : Switch Control Select
bits : 16 - 16 (1 bit)
access : read-write
T9CON : Control of T[9]
bits : 17 - 17 (1 bit)
access : read-write
T10CON : Control of T[10]
bits : 18 - 18 (1 bit)
access : read-write
T11CON : Control of T[11]
bits : 19 - 19 (1 bit)
access : read-write
AFE DSP Configuration
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HANNINGEN : Hanning Window Enable
bits : 0 - 0 (1 bit)
access : read-write
DFTNUM : ADC Samples Used
bits : 4 - 7 (4 bit)
access : read-write
DFTINSEL : DFT Input Select
bits : 20 - 21 (2 bit)
access : read-write
ULPTIA Switch Configuration for Channel 1
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIASWCON : TIA SW[11:0] Control
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
20 : CAPA_LP
CAPA test with LP TIA
44 : NORM
Normal work mode
45 : DIO
Normal work mode with back-back diode enabled.
46 : SHORTSW
Work mode with short switch protection
108 : LOWNOISE
Work mode, vzero-vbias=0.
End of enumeration elements list.
PABIASSEL : TIA SW12 Control. Active High
bits : 12 - 12 (1 bit)
access : read-write
TIABIASSEL : TIA SW13 Control. Active High
bits : 13 - 13 (1 bit)
access : read-write
ULPTIA Switch Configuration for Channel 0
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIASWCON : TIA SW[11:0] Control
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
20 : 11
CAPA test with LP TIA
44 : NORM
Normal work mode
45 : DIO
Normal work mode with back-back diode enabled.
46 : SHORTSW
Work mode with short switch protection
108 : LOWNOISE
Work mode, vzero-vbias=0.
End of enumeration elements list.
PABIASSEL : TIA SW12 Control. Active High
bits : 12 - 12 (1 bit)
access : read-write
TIABIASSEL : TIA SW13 Control. Active High
bits : 13 - 13 (1 bit)
access : read-write
VZEROSHARE : TIA SW14 Control. Active High
bits : 14 - 14 (1 bit)
access : read-write
RECAL : TIA SW15 Control. Active High
bits : 15 - 15 (1 bit)
access : read-write
ULPTIA Control Bits Channel 1
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIAPDEN : TIA Power Down
bits : 0 - 0 (1 bit)
access : read-write
PAPDEN : PA Power Down
bits : 1 - 1 (1 bit)
access : read-write
HALFPWR : Half Power Mode Select
bits : 2 - 2 (1 bit)
access : read-write
IBOOST : Current Boost Control
bits : 3 - 4 (2 bit)
access : read-write
TIAGAIN : Set RTIA Gain Resistor
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0 : DISCONTIA
Disconnect TIA Gain resistor
1 : TIAGAIN200
200 Ohm
2 : TIAGAIN1k
1k ohm
3 : TIAGAIN2k
2k
4 : TIAGAIN3k
3k
5 : TIAGAIN4k
4k
6 : TIAGAIN6k
6k
7 : TIAGAIN8k
8k
8 : TIAGAIN10k
10k
9 : TIAGAIN12k
12k
10 : TIAGAIN16k
16k
11 : TIAGAIN20k
20k
12 : TIAGAIN24k
24k
13 : TIAGAIN30k
30k
14 : TIAGAIN32k
32k
15 : TIAGAIN40k
40k
16 : TIAGAIN48k
48k
17 : TIAGAIN64k
64k
18 : TIAGAIN85k
85k
19 : TIAGAIN96k
96k
20 : TIAGAIN100k
100k
21 : TIAGAIN120k
120k
22 : TIAGAIN128k
128k
23 : TIAGAIN160k
160k
24 : TIAGAIN196k
196k
25 : TIAGAIN256k
256k
26 : TIAGAIN512k
512k
End of enumeration elements list.
TIARL : Set RLOAD
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
0 : RL0
0 ohm
1 : RL10
10 ohm
2 : RL30
30 ohm
3 : RL50
50 ohm
4 : RL100
100 ohm
5 : RL1p6k
1.6kohm
6 : RL3p1k
3.1kohm
7 : RL3p5k
3.6kohm
End of enumeration elements list.
TIARF : Set LPF Resistor
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : DISCONRF
Disconnect TIA output from LPF pin
1 : BYPRF
Bypass resistor
2 : RF20k
20k Ohm
3 : RF100k
100k Ohm
4 : RF200k
200k Ohm
5 : RF400k
400k Ohm
6 : RF600k
600k Ohm
7 : RF1MOHM
1Meg Ohm
End of enumeration elements list.
CHOPEN : Chopping Enable
bits : 16 - 17 (2 bit)
access : read-write
ULPTIA Control Bits Channel 0
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIAPDEN : TIA Power Down
bits : 0 - 0 (1 bit)
access : read-write
PAPDEN : PA Power Down
bits : 1 - 1 (1 bit)
access : read-write
HALFPWR : Half Power Mode Select
bits : 2 - 2 (1 bit)
access : read-write
IBOOST : Current Boost Control
bits : 3 - 4 (2 bit)
access : read-write
TIAGAIN : Set RTIA
bits : 5 - 9 (5 bit)
access : read-write
Enumeration:
0 : DISCONTIA
Disconnect TIA Gain resistor
1 : TIAGAIN200
200 Ohm
2 : TIAGAIN1k
1k ohm
3 : TIAGAIN2k
2k
4 : TIAGAIN3k
3k
5 : TIAGAIN4k
4k
6 : TIAGAIN6k
6k
7 : TIAGAIN8k
8k
8 : TIAGAIN10k
10k
9 : TIAGAIN12k
12k
10 : TIAGAIN16k
16k
11 : TIAGAIN20k
20k
12 : TIAGAIN24k
24k
13 : TIAGAIN30k
30k
14 : TIAGAIN32k
32k
15 : TIAGAIN40k
40k
16 : TIAGAIN48k
48k
17 : TIAGAIN64k
64k
18 : TIAGAIN85k
85k
19 : TIAGAIN96k
96k
20 : TIAGAIN100k
100k
21 : TIAGAIN120k
120k
22 : TIAGAIN128k
128k
23 : TIAGAIN160k
160k
24 : TIAGAIN196k
196k
25 : TIAGAIN256k
256k
26 : TIAGAIN512k
512k
End of enumeration elements list.
TIARL : Set RLOAD
bits : 10 - 12 (3 bit)
access : read-write
Enumeration:
0 : RL0
0 ohm
1 : RL10
10 ohm
2 : RL30
30 ohm
3 : RL50
50 ohm
4 : RL100
100 ohm
5 : RL1p6k
1.6kohm
6 : RL3p1k
3.1kohm
7 : RL3p5k
3.6kohm
End of enumeration elements list.
TIARF : Set LPF Resistor
bits : 13 - 15 (3 bit)
access : read-write
Enumeration:
0 : DISCONRF
Disconnect TIA output from LPF pin
1 : BYPRF
Bypass resistor
2 : RF20k
20k Ohm
3 : RF100k
100k Ohm
4 : RF200k
200k Ohm
5 : RF400k
400k Ohm
6 : RF600k
600k Ohm
7 : RF1MOHM
1Meg Ohm
End of enumeration elements list.
CHOPEN : Chopping Enable
bits : 16 - 17 (2 bit)
access : read-write
High Power RTIA Configuration
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTIACON : Configure General RTIA Value
bits : 0 - 3 (4 bit)
access : read-write
TIASW6CON : SW6 Control
bits : 4 - 4 (1 bit)
access : read-write
CTIACON : Configure Capacitor in Parallel with RTIA
bits : 5 - 12 (8 bit)
access : read-write
DE1 HSTIA Resistors Configuration
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DE1RCON : DE1 RLOAD RTIA Setting
bits : 0 - 7 (8 bit)
access : read-write
DE0 HSTIA Resistors Configuration
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DE0RCON : DE0 RLOAD RTIA Setting
bits : 0 - 7 (8 bit)
access : read-write
HSTIA Amplifier Configuration
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBIASSEL : Select HSTIA Positive Input
bits : 0 - 1 (2 bit)
access : read-write
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