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CLKCTL

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x448 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CLKCON0

CLKDIS

CLKCON1

XOSCCON

CLKSYSDIV


CLKCON0

System clocking architecture control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCON0 CLKCON0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD CLKMUX CLKOUT

CD : Clock divide bits
bits : 0 - 2 (3 bit)

Enumeration:

0 : DIV1

None

1 : DIV2

None

2 : DIV4

None

3 : DIV8

None

4 : DIV16

None

5 : DIV32

None

6 : DIV64

None

7 : DIV128

None

End of enumeration elements list.

CLKMUX : Digital subsystem clock source select bits.
bits : 3 - 4 (2 bit)

Enumeration:

0 : HFOSC

None

1 : LFXTAL

None

2 : LFOSC

None

3 : EXTCLK

None

End of enumeration elements list.

CLKOUT : GPIO output clock multiplexer select bits
bits : 5 - 7 (3 bit)

Enumeration:

0 : UCLKCG

None

1 : UCLK

None

2 : PCLK

None

5 : HFOSC

None

6 : LFOSC

None

7 : LFXTAL

None

End of enumeration elements list.


CLKDIS

System Clocks Control Register 1
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKDIS CLKDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISSPI0CLK DISSPI1CLK DISI2CCLK DISUARTCLK DISPWMCLK DIST0CLK DIST1CLK DISDACCLK DISDMACLK DISADCCLK

DISSPI0CLK : Disable SPI0 system clock bits
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISSPI1CLK : Disable SPI1 system clock
bits : 1 - 1 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISI2CCLK : Disable I2C system clock
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISUARTCLK : Disable UART system clock
bits : 3 - 3 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISPWMCLK : Disable PWM system clock
bits : 4 - 4 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DIST0CLK : Disable Timer 0 system clock
bits : 5 - 5 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DIST1CLK : Disable Timer 1 system clock
bits : 6 - 6 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISDACCLK : Disable DAC system clock
bits : 7 - 7 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISDMACLK : Disable DMA system clock
bits : 8 - 8 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DISADCCLK : Disable ADC system clock
bits : 9 - 9 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


CLKCON1

System Clocks Control Register 1
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKCON1 CLKCON1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI0CD SPI1CD I2CCD UARTCD PWMCD

SPI0CD : Clock divide bits for SPI0 system clock
bits : 0 - 2 (3 bit)

Enumeration:

0 : DIV1

None

1 : DIV2

None

2 : DIV4

None

3 : DIV8

None

4 : DIV16

None

5 : DIV32

None

6 : DIV64

None

7 : DIV128

None

End of enumeration elements list.

SPI1CD : Clock divide bits for SPI1 system clock
bits : 3 - 5 (3 bit)

Enumeration:

0 : DIV1

None

1 : DIV2

None

2 : DIV4

None

3 : DIV8

None

4 : DIV16

None

5 : DIV32

None

6 : DIV64

None

7 : DIV128

None

End of enumeration elements list.

I2CCD : Clock divide bits for I2C system clock
bits : 6 - 8 (3 bit)

Enumeration:

0 : DIV1

None

1 : DIV2

None

2 : DIV4

None

3 : DIV8

None

4 : DIV16

None

5 : DIV32

None

6 : DIV64

None

7 : DIV128

None

End of enumeration elements list.

UARTCD : Clock divide bits for UART system clock
bits : 9 - 11 (3 bit)

Enumeration:

0 : DIV1

None

1 : DIV2

None

2 : DIV4

None

3 : DIV8

None

4 : DIV16

None

5 : DIV32

None

6 : DIV64

None

7 : DIV128

None

End of enumeration elements list.

PWMCD : Clock divide bits for PWM system clock
bits : 12 - 14 (3 bit)

Enumeration:

0 : DIV1

None

1 : DIV2

None

2 : DIV4

None

3 : DIV8

None

4 : DIV16

None

5 : DIV32

None

6 : DIV64

None

7 : DIV128

None

End of enumeration elements list.


XOSCCON

Crystal Oscillator control
address_offset : 0x410 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSCCON XOSCCON read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 ENABLE DIV2

ENABLE : Crystal oscillator circuit enable (Enable the oscillator circuitry.)
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.

DIV2 : Divide by two enable
bits : 2 - 2 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.


CLKSYSDIV

Sys Clock div2 Register
address_offset : 0x444 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLKSYSDIV CLKSYSDIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIV2EN

DIV2EN : bits
bits : 0 - 0 (1 bit)

Enumeration:

0 : DIS

None

1 : EN

None

End of enumeration elements list.



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