\n

XINT0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFG0

CLR

NMICLR

EXT_STAT


CFG0

External Interrupt Configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ0MDE IRQ0EN IRQ1MDE IRQ1EN IRQ2MDE IRQ2EN IRQ3MDE IRQ3EN UART_RX_EN UART_RX_MDE

IRQ0MDE : External Interrupt 0 Mode Registers
bits : 0 - 2 (3 bit)
access : read-write

IRQ0EN : External Interrupt 0 Enable
bits : 3 - 3 (1 bit)
access : read-write

IRQ1MDE : External Interrupt 1 Mode Registers
bits : 4 - 6 (3 bit)
access : read-write

IRQ1EN : External Interrupt 1 Enable
bits : 7 - 7 (1 bit)
access : read-write

IRQ2MDE : External Interrupt 2 Mode Registers
bits : 8 - 10 (3 bit)
access : read-write

IRQ2EN : External Interrupt 2 Enable
bits : 11 - 11 (1 bit)
access : read-write

IRQ3MDE : External Interrupt 3 Mode Registers
bits : 12 - 14 (3 bit)
access : read-write

IRQ3EN : External Interrupt 3 Enable
bits : 15 - 15 (1 bit)
access : read-write

UART_RX_EN : External Interrupt Using UART_RX Enable Bit
bits : 20 - 20 (1 bit)
access : read-write

UART_RX_MDE : External Interrupt Using UART_RX Wakeup Mode Registers
bits : 21 - 23 (3 bit)
access : read-write


CLR

External Interrupt Clear
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLR CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IRQ0 IRQ1 IRQ2 IRQ3 UART_RX_CLR

IRQ0 : External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-write

IRQ1 : External Interrupt 1
bits : 1 - 1 (1 bit)
access : read-write

IRQ2 : External Interrupt 2
bits : 2 - 2 (1 bit)
access : read-write

IRQ3 : External Interrupt 3
bits : 3 - 3 (1 bit)
access : read-write

UART_RX_CLR : External Interrupt Clear for UART_RX WAKEUP Interrupt
bits : 5 - 5 (1 bit)
access : read-write


NMICLR

Non-maskable Interrupt Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMICLR NMICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR

CLR : NMI Clear
bits : 0 - 0 (1 bit)
access : read-write


EXT_STAT

External Wakeup Interrupt Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXT_STAT EXT_STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STAT_EXTINT0 STAT_EXTINT1 STAT_EXTINT2 STAT_EXTINT3 STAT_UART_RXWKUP

STAT_EXTINT0 : Interrupt Status Bit for External Interrupt 0
bits : 0 - 0 (1 bit)
access : read-only

STAT_EXTINT1 : Interrupt Status Bit for External Interrupt 1
bits : 1 - 1 (1 bit)
access : read-only

STAT_EXTINT2 : Interrupt Status Bit for External Interrupt 2
bits : 2 - 2 (1 bit)
access : read-only

STAT_EXTINT3 : Interrupt Status Bit for External Interrupt 3
bits : 3 - 3 (1 bit)
access : read-only

STAT_UART_RXWKUP : Interrupt Status Bit for UART RX WAKEUP Interrupt
bits : 5 - 5 (1 bit)
access : read-only



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