\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Counter Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : CNTDIS
Counter Disable
1 : CNTEN
Counter Enable
End of enumeration elements list.
DEBEN : Debounce Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DEBDIS
Disable
1 : DEBEN
Enable
End of enumeration elements list.
DIVEN : Divider Enable
bits : 2 - 2 (1 bit)
access : read-write
DIVNTV : Non-debounced Inputs to Divider Enable
bits : 3 - 3 (1 bit)
access : read-write
CDGINV : CDG Pin Polarity Invert
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : CDGINV_AHI
Active High, Rising Edge
1 : CDGINV_ALO
Active Low, Falling Edge
End of enumeration elements list.
CUDINV : CUD Pin Polarity Invert
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : CUDINV_AHI
Active High, Rising Edge
1 : CUDINV_ALO
Active Low, Falling Edge
End of enumeration elements list.
CZMINV : CZM Pin Polarity Invert
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CZMINV_AHI
Active High, Rising Edge
1 : CZMINV_ALO
Active Low, Falling Edge
End of enumeration elements list.
DIVMODE : Divider Mode
bits : 7 - 7 (1 bit)
access : read-write
CNTMODE : Counter Operating Mode
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : CNTMODE_QUADENC
QUAD_ENC.
1 : CNTMODE_BINENC
BIN_ENC.
2 : CNTMODE_UDCNT
UD_CNT.
4 : CNTMODE_DIRCNT
DIR_CNT.
5 : CNTMODE_DIRTMR
DIR_TMR.
End of enumeration elements list.
ZMZC : CZM Zeros Counter Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : ZMZC_DIS
Disable
1 : ZMZC_EN
Enable
End of enumeration elements list.
BNDMODE : Boundary Register Mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0 : BNDMODE_BNDCOMP
BND_COMP.
1 : BNDMODE_BINENC
BND_ZERO.
2 : BNDMODE_BNDCAPT
BND_CAPT.
3 : BNDMODE_BNDAEXT
BND_AEXT.
End of enumeration elements list.
INPDIS : CUD and CDG Pin Input Disable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NO_INPDIS
Enable
1 : INPDIS
Pin Input Disable
End of enumeration elements list.
Debounce Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPRESCALE : Debounce Prescale
bits : 0 - 4 (5 bit)
access : read-write
Counter Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : CNTR Value
bits : 0 - 31 (32 bit)
access : read-write
Maximum Count Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : MAX Value
bits : 0 - 31 (32 bit)
access : read-write
Minimum Count Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : MIN Value
bits : 0 - 31 (32 bit)
access : read-write
M Value for Divider
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MDIV : M Value for Divider
bits : 0 - 15 (16 bit)
access : read-write
N Value for Divider
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDIV : N Value for Divider
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC : Illegal Gray/Binary Code Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : IC_MSK
Mask Interrupt
1 : IC_UMSK
Unmask Interrupt
End of enumeration elements list.
UC : Upcount Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : UC_MSK
Mask Interrupt
1 : UC_UMSK
Unmask Interrupt
End of enumeration elements list.
DC : Downcount Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DC_MSK
Mask Interrupt
1 : DC_UMSK
Unmask Interrupt
End of enumeration elements list.
MINC : Min Count Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : MINC_MSK
Mask Interrupt
1 : MINC_UMSK
Unmask Interrupt
End of enumeration elements list.
MAXC : Max Count Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : MAXC_MSK
Mask Interrupt
1 : MAXC_UMSK
Unmask Interrupt
End of enumeration elements list.
COV31 : Bit 31 Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : COV31_MSK
Mask Interrupt
1 : COV31_UMSK
Unmask Interrupt
End of enumeration elements list.
COV15 : Bit 15 Overflow Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : COV15_MSK
Mask Interrupt
1 : COV15_UMSK
Unmask Interrupt
End of enumeration elements list.
CZERO : CNT_CNTR Counts To Zero Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : CZERO_MSK
Mask Interrupt
1 : CZERO_UMSK
Unmask Interrupt
End of enumeration elements list.
CZM : CZM Pin/Pushbutton Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : CZM_MSK
Mask Interrupt
1 : CZM_UMSK
Unmask Interrupt
End of enumeration elements list.
CZME : Zero Marker Error Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : CZME_MSK
Mask Interrupt
1 : CZME_UMSK
Unmask Interrupt
End of enumeration elements list.
CZMZ : Counter Zeroed by Zero Marker Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : CZMZ_MSK
Mask Interrupt
1 : CZMZ_UMSK
Unmask Interrupt
End of enumeration elements list.
STP : Stop Detect Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write
MERR : M Value Programming Error Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
DERR : Direction Error Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
DCHNG : Direction Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IC : Illegal Gray/Binary Code Interrupt
bits : 0 - 0 (1 bit)
access : read-write
UC : Up Count Interrupt
bits : 1 - 1 (1 bit)
access : read-write
DC : Down Count Interrupt
bits : 2 - 2 (1 bit)
access : read-write
MINC : Min Count Interrupt
bits : 3 - 3 (1 bit)
access : read-write
MAXC : Max Count Interrupt
bits : 4 - 4 (1 bit)
access : read-write
COV31 : Bit 31 Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-write
COV15 : Bit 15 Overflow Interrupt
bits : 6 - 6 (1 bit)
access : read-write
CZERO : CNT_CNTR Counts To Zero Interrupt
bits : 7 - 7 (1 bit)
access : read-write
CZM : CZM Pin/Pushbutton Interrupt
bits : 8 - 8 (1 bit)
access : read-write
CZME : Zero Marker Error Interrupt
bits : 9 - 9 (1 bit)
access : read-write
CZMZ : Counter Zeroed By Zero Marker Interrupt
bits : 10 - 10 (1 bit)
access : read-write
STP : Stop Detect Interrupt
bits : 11 - 11 (1 bit)
access : read-write
MERR : M Value Programming Error Interrupt
bits : 12 - 12 (1 bit)
access : read-write
DERR : Direction Error Interrupt
bits : 13 - 13 (1 bit)
access : read-write
DCHNG : Direction Change Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write
Command Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
W1LCNTZERO : Write 1 CNTR to Zero
bits : 0 - 0 (1 bit)
access : read-write
W1LCNTMIN : Write 1 CNTR Load from MIN
bits : 2 - 2 (1 bit)
access : read-write
W1LCNTMAX : Write 1 CNTR Load from MAX
bits : 3 - 3 (1 bit)
access : read-write
W1LMINZERO : Write 1 MIN to Zero
bits : 4 - 4 (1 bit)
access : read-write
W1LMINCNT : Write 1 MIN Capture from CNTR
bits : 5 - 5 (1 bit)
access : read-write
W1LMINMAX : Write 1 MIN Copy from MAX
bits : 7 - 7 (1 bit)
access : read-write
W1LMAXZERO : Write 1 MAX to Zero
bits : 8 - 8 (1 bit)
access : read-write
W1LMAXCNT : Write 1 MAX Capture from CNTR
bits : 9 - 9 (1 bit)
access : read-write
W1LMAXMIN : Write 1 MAX Copy from MIN
bits : 10 - 10 (1 bit)
access : read-write
W1ZMONCE : Write 1 Zero Marker Clear Once Enable
bits : 12 - 12 (1 bit)
access : read-write
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