\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GLOBEN : Module Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : PWM_DIS
Disable
1 : PWM_EN
Enable
End of enumeration elements list.
EMURUN : Output Behavior During Emulation Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : EMURUN_DIS
Disable Outputs
1 : EMURUN_EN
Enable Outputs
End of enumeration elements list.
SWTRIP : Software Trip
bits : 2 - 2 (1 bit)
access : read-write
DUEN : Double Update Mode Enable
bits : 3 - 3 (1 bit)
access : read-write
DLYAEN : Enable Delay Counter for Channel A
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DLYA_DIS
Disable
1 : DLYA_EN
Enable
End of enumeration elements list.
DLYBEN : Enable Delay Counter for Channel B
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DLYB_DIS
Disable
1 : DLYB_EN
Enable
End of enumeration elements list.
DLYCEN : Enable Delay Counter for Channel C
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DLYC_DIS
Disable
1 : DLYC_EN
Enable
End of enumeration elements list.
DLYDEN : Enable Delay Counter for Channel D
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DLYD_DIS
Disable
1 : DLYD_EN
Enable
End of enumeration elements list.
ADEN : Asymmetric Dead-time Enable
bits : 8 - 8 (1 bit)
access : read-write
EXTSYNC : External Sync
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : INTSYNC
Internal sync used
1 : EXTSYNC
External sync used
End of enumeration elements list.
EXTSYNCSEL : External Sync Select
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : EXTSYNC_ASYNC
Asynchronous External Sync
1 : EXTSYNC_SYNC
Synchronous External Sync
End of enumeration elements list.
INTSYNCREF : Timer reference for Internal Sync
bits : 18 - 20 (3 bit)
access : read-write
Enumeration:
0 : INTSYNC_0
PWMTMR0 provides sync reference
1 : INTSYNC_1
PWMTMR1 provides sync reference
2 : INTSYNC_2
PWMTMR2 provides sync reference
3 : INTSYNC_3
PWMTMR3 provides sync reference
4 : INTSYNC_4
PWMTMR4 provides sync reference
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIP0 : TRIP0 Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TRIP0_MSK
Mask TRIP0 Interrupt
1 : TRIP0_UMSK
Unmask TRIP0 Interrupt
End of enumeration elements list.
TRIP1 : TRIP1 Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TRIP1_MSK
Mask TRIP1 Interrupt
1 : TRIP1_UMSK
Unmask TRIP1 Interrupt
End of enumeration elements list.
TMR0PER : PWMTMR0 Period Boundary Interrupt Enable
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : PER0_MSK
Mask PWMTMR0 Period Interrupt
1 : PER0_UMSK
Unmask PWMTMR0 Period Interrupt
End of enumeration elements list.
TMR1PER : PWMTMR1 Period Boundary Interrupt Enable
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : PER1_MSK
Mask PWMTMR1 Period Interrupt
1 : PER1_UMSK
Unmask PWMTMR1 Period Interrupt
End of enumeration elements list.
TMR2PER : PWMTMR2 Period Boundary Interrupt Enable
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : PER2_MSK
Mask PWMTMR2 Period Interrupt
1 : PER2_UMSK
Unmask PWMTMR2 Period Interrupt
End of enumeration elements list.
TMR3PER : PWMTMR3 Period Boundary Interrupt Enable
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : PER3_MSK
Mask PWMTMR3 Period Interrupt
1 : PER3_UMSK
Unmask PWMTMR3 Period Interrupt
End of enumeration elements list.
TMR4PER : PWMTMR4 Period Boundary Interrupt Enable
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : PER4_MSK
Mask PWMTMR4 Period Interrupt
1 : PER4_UMSK
Unmask PWMTMR4 Period Interrupt
End of enumeration elements list.
Channel C-Low Full Duty0 Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel C-Low Full Duty1 Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel D-High Full Duty0 Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel D-High Full Duty1 Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel D-Low Full Duty0 Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel D-Low Full Duty1 Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel A Dead-time Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Dead-time value
bits : 0 - 9 (10 bit)
access : read-write
Channel B Dead-time Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Dead-time value
bits : 0 - 9 (10 bit)
access : read-write
Channel C Dead-time Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Dead-time value
bits : 0 - 9 (10 bit)
access : read-write
Channel D Dead-time Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Dead-time value
bits : 0 - 9 (10 bit)
access : read-write
Software Trip Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWTRIPAL : Software Trip Bit for Channel A Low Side
bits : 0 - 0 (1 bit)
access : read-write
SWTRIPBL : Software Trip Bit for Channel B Low Side
bits : 1 - 1 (1 bit)
access : read-write
SWTRIPCL : Software Trip Bit for Channel C Low Side
bits : 2 - 2 (1 bit)
access : read-write
SWTRIPDL : Software Trip Bit for Channel D Low Side
bits : 3 - 3 (1 bit)
access : read-write
SWTRIPAH : Software Trip Bit for Channel A High Side
bits : 16 - 16 (1 bit)
access : read-write
SWTRIPBH : Software Trip Bit for Channel B High Side
bits : 17 - 17 (1 bit)
access : read-write
SWTRIPCH : Software Trip Bit for Channel C High Side
bits : 18 - 18 (1 bit)
access : read-write
SWTRIPDH : Software Trip Bit for Channel D High Side
bits : 19 - 19 (1 bit)
access : read-write
Trip Polarity Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPOLAL : Channel A Low Side Trip Polarity
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : TPOLAL_DIS
Set Channel A Low Side to Inactive Polarity upon Trip
1 : TPOLAL_EN
Set Channel A Low Side to Active Polarity upon Trip
2 : TPOLAL_HIZ
Set Channel A Low Side to High Impedance upon Trip
End of enumeration elements list.
TPOLBL : Channel B Low Side Trip Polarity
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : TPOLBL_DIS
Set Channel B Low Side to Inactive Polarity upon Trip
1 : TPOLBL_EN
Set Channel B Low Side to Active Polarity upon Trip
2 : TPOLBL_HIZ
Set Channel B Low Side to High Impedance upon Trip
End of enumeration elements list.
TPOLCL : Channel C Low Side Trip Polarity
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : TPOLCL_DIS
Set Channel C Low Side to Inactive Polarity upon Trip
1 : TPOLCL_EN
Set Channel C Low Side to Active Polarity upon Trip
2 : TPOLCL_HIZ
Set Channel C Low Side to High Impedance upon Trip
End of enumeration elements list.
TPOLDL : Channel D Low Side Trip Polarity
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : TPOLDL_DIS
Set Channel D Low Side to Inactive Polarity upon Trip
1 : TPOLDL_EN
Set Channel D Low Side to Active Polarity upon Trip
2 : TPOLDL_HIZ
Set Channel D Low Side to High Impedance upon Trip
End of enumeration elements list.
TPOLAH : Channel A High Side Trip Polarity
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0 : TPOLAH_DIS
Set Channel A High Side to Inactive Polarity upon Trip
1 : TPOLAH_EN
Set Channel A High Side to Active Polarity upon Trip
2 : TPOLAH_HIZ
Set Channel A High Side to High Impedance upon Trip
End of enumeration elements list.
TPOLBH : Channel B High Side Trip Polarity
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0 : TPOLBH_DIS
Set Channel B High Side to Inactive Polarity upon Trip
1 : TPOLBH_EN
Set Channel B High Side to Active Polarity upon Trip
2 : TPOLBH_HIZ
Set Channel B High Side to High Impedance upon Trip
End of enumeration elements list.
TPOLCH : Channel C High Side Trip Polarity
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : TPOLCH_DIS
Set Channel C High Side to Inactive Polarity upon Trip
1 : TPOLCH_EN
Set Channel C High Side to Active Polarity upon Trip
2 : TPOLCH_HIZ
Set Channel C High Side to High Impedance upon Trip
End of enumeration elements list.
TPOLDH : Channel D High Side Trip Polarity
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : TPOLDH_DIS
Set Channel D High Side to Inactive Polarity upon Trip
1 : TPOLDH_EN
Set Channel D High Side to Active Polarity upon Trip
2 : TPOLDH_HIZ
Set Channel D High Side to High Impedance upon Trip
End of enumeration elements list.
Interrupt Latch Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIP0 : TRIP0 Interrupt Latched Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TRIP0_INTLO
No Interrupt Latched
1 : TRIP0_INTHI
Interrupt Latched
End of enumeration elements list.
TRIP1 : TRIP1 Interrupt Latched Status
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TRIP1_INTLO
No Interrupt Latched
1 : TRIP1_INTHI
Interrupt Latched
End of enumeration elements list.
TMR0PER : PWMTMR0 Period Boundary Interrupt Latched Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : PER0_INTLO
No Interrupt Latched
1 : PER0_INTHI
Interrupt Latched
End of enumeration elements list.
TMR1PER : PWMTMR1 Period Latched Interrupt Status
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : PER1_INTLO
No Interrupt Latched
1 : PER1_INTHI
Interrupt Latched
End of enumeration elements list.
TMR2PER : PWMTMR2 Period Latched Interrupt Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : PER2_INTLO
No Interrupt Latched
1 : PER2_INTHI
Interrupt Latched
End of enumeration elements list.
TMR3PER : PWMTMR3 Period Latched Interrupt Status
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : PER3_INTLO
No Interrupt Latched
1 : PER3_INTHI
Interrupt Latched
End of enumeration elements list.
TMR4PER : PWMTMR4 Period Latched Interrupt Status
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : PER4_INTLO
No Interrupt Latched
1 : PER4_INTHI
Interrupt Latched
End of enumeration elements list.
Chop Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Gate Chopping Divisor
bits : 0 - 7 (8 bit)
access : read-write
Sync Pulse Width Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Sync Pulse Width
bits : 0 - 9 (10 bit)
access : read-write
Timer 0 Period Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Timer PWMTMR0 Period Value
bits : 0 - 15 (16 bit)
access : read-write
Timer 1 Period Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Timer PWMTMR1 Period Value
bits : 0 - 15 (16 bit)
access : read-write
Timer 2 Period Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Timer PWMTMR2 Period Value
bits : 0 - 15 (16 bit)
access : read-write
Timer 3 Period Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Timer PWMTMR3 Period Value
bits : 0 - 15 (16 bit)
access : read-write
Timer 4 Period Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Timer PWMTMR4 Period Value
bits : 0 - 15 (16 bit)
access : read-write
Channel A Delay Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Channel A Delay Value
bits : 0 - 15 (16 bit)
access : read-write
Channel B Delay Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Channel B Delay Value
bits : 0 - 15 (16 bit)
access : read-write
Channel Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFTMRA : Channel A Timer Reference
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : REFTMRA_0
PWMTMR0 is Channel A reference
1 : REFTMRA_1
PWMTMR1 is Channel A reference
End of enumeration elements list.
MODELSA : Channel A Mode of low Side Output
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LOA_INVHI
Invert of high output
1 : LOA_IND
Independent control
End of enumeration elements list.
POLAH : Channel A High side Polarity
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : AH_ACTLO
Active Low
1 : AH_ACTHI
Active High
End of enumeration elements list.
ENCHOPAH : Channel A Gate Chopping Enable High Side
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : CHOPAH_DIS
Disable Chopping Channel A High Side
1 : CHOPAH_EN
Enable Chopping Channel A High Side
End of enumeration elements list.
ENHPAH : Channel A heightened-precision enable for high side Output
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : HPAH_DIS
Disable HP Output Channel A High
1 : HPAH_EN
Enable HP Output Channel A High
End of enumeration elements list.
POLAL : Channel A low side Polarity
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : AL_ACTLO
Active Low
1 : AL_ACTHI
Active High
End of enumeration elements list.
ENCHOPAL : Channel A Gate Chopping Enable Low Side
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : CHOPAL_DIS
Disable Chopping Channel A Low Side
1 : CHOPAL_EN
Enable Chopping Channel A Low Side
End of enumeration elements list.
REFTMRB : Channel B Timer Reference
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : REFTMRB_0
PWMTMR0 is Channel B reference
1 : REFTMRB_1
PWMTMR2 is Channel B reference
End of enumeration elements list.
MODELSB : Channel B Mode of low Side Output
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : LOB_INV
Invert of high output
1 : LOB_IND
Independent control
End of enumeration elements list.
POLBH : Channel B High side Polarity
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : BH_ACTLO
Active Low
1 : BH_ACTHI
Active High
End of enumeration elements list.
ENCHOPBH : Channel B Gate Chopping Enable High Side
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : CHOPBH_DIS
Disable Chopping Channel B High Side
1 : CHOPBH_EN
Enable Chopping Channel B High Side
End of enumeration elements list.
ENHPBH : Channel B heightened-precision enable for high side Output
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : HPBH_DIS
Disable HP Output Channel B High
1 : HPBH_EN
Enable HP Output Channel B High
End of enumeration elements list.
POLBL : Channel B low side Polarity
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : BL_ACTLO
Active Low
1 : BL_ACTHI
Active High
End of enumeration elements list.
ENCHOPBL : Channel B Gate Chopping Enable Low Side
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : CHOPBL_DIS
Disable Chopping Channel B Low Side
1 : CHOPBL_EN
Enable Chopping Channel B Low Side
End of enumeration elements list.
REFTMRC : Channel C Timer Reference
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : REFTMRC_0
PWMTMR0 is Channel C reference
1 : REFTMRC_1
PWMTMR3 is Channel C reference
End of enumeration elements list.
MODELSC : Channel C Mode of low Side Output
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : LOC_INVHI
Invert of high output
1 : LOC_IND
Independent control
End of enumeration elements list.
POLCH : Channel C High side Polarity
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : CH_ACTLO
Active Low
1 : CH_ACTHI
Active High
End of enumeration elements list.
ENCHOPCH : Channel C Gate Chopping Enable High Side
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : CHOPCH_DIS
Disable Chopping Channel C High Side
1 : CHOPCH_EN
Enable Chopping Channel C High Side
End of enumeration elements list.
ENHPCH : Channel C heightened-precision enable for high side Output
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : HPCH_DIS
Disable HP Output Channel C High
1 : HPCH_EN
Enable HP Output Channel C High
End of enumeration elements list.
POLCL : Channel C low side Polarity
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : CL_ACTLO
Active Low
1 : CL_ACTHI
Active High
End of enumeration elements list.
ENCHOPCL : Channel C Gate Chopping Enable Low Side
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : CHOPCL_DIS
Disable Chopping Channel C Low Side
1 : CHOPCL_EN
Enable Chopping Channel C Low Side
End of enumeration elements list.
REFTMRD : Channel D Timer Reference
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : REFTMRD_0
PWMTMR0 is Channel D reference
1 : REFTMRD_1
PWMTMR4 is Channel D reference
End of enumeration elements list.
MODELSD : Channel D Mode of low Side Output
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : LOD_INVHI
Invert of high output
1 : LOD_IND
Independent control
End of enumeration elements list.
POLDH : Channel D High side Polarity
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : DH_ACTLO
Active Low
1 : DH_ACTHI
Active High
End of enumeration elements list.
ENCHOPDH : Channel D Gate Chopping Enable High Side
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : CHOPDH_DIS
Disable Chopping Channel D High Side
1 : CHOPDH_EN
Enable Chopping Channel D High Side
End of enumeration elements list.
ENHPDH : Channel D heightened-precision enable for high side Output
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : HPDH_DIS
Disable HP Output Channel D High
1 : HPDH_EN
Enable HP Output Channel D High
End of enumeration elements list.
POLDL : Channel D low side Polarity
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : DL_ACTLO
Active Low
1 : DL_ACTHI
Active High
End of enumeration elements list.
ENCHOPDL : Channel D Gate Chopping Enable Low Side
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : CHOPDL_DIS
Disable Chopping Channel D Low Side
1 : CHOPDL_EN
Enable Chopping Channel D Low Side
End of enumeration elements list.
Channel C Delay Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Channel C Delay Value
bits : 0 - 15 (16 bit)
access : read-write
Channel D Delay Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Channel D Delay Value
bits : 0 - 15 (16 bit)
access : read-write
Channel A Control Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISHI : Channel High Side Output Disable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : HI_DIS
Enable High Side Output
1 : HI_EN
Disable High Side Output
End of enumeration elements list.
DISLO : Channel Low Side Output Disable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : LO_DIS
Enable Low Side Output
1 : LO_EN
Disable Low Side Output
End of enumeration elements list.
XOVR : high-low Crossover Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : XOVR_DIS
Disable Crossover
1 : XOVR_EN
Enable Crossover
End of enumeration elements list.
PULSEMODEHI : High Side Output Pulse Position
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : SYM_HI
Symmetrical
1 : ASYM_HI
Asymmetrical
2 : LEFT_HI
Left Half
3 : RIGHT_HI
Right Half
End of enumeration elements list.
PULSEMODELO : Low Side Output Pulse Position
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0 : SYM_LO
Symmetrical
1 : ASYM_LO
Asymmetrical
2 : LEFT_LO
Left Half
3 : RIGHT_LO
Right Half
End of enumeration elements list.
Channel A-High Duty-0 Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel A-High Duty-1 Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel A-High Heightened-Precision Duty-0 Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel A-High Heightened-Precision Duty-1 Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel A-Low Duty-0 Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel A-Low Duty-1 Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel A-Low Heightened-Precision Duty-0 Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel A-Low Heightened-Precision Duty-1 Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel B Control Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISHI : Channel High Side Output Disable
bits : 0 - 0 (1 bit)
access : read-write
DISLO : Channel Low Side Output Disable
bits : 1 - 1 (1 bit)
access : read-write
XOVR : high-low Crossover Enable
bits : 2 - 2 (1 bit)
access : read-write
PULSEMODEHI : High Side Output Pulse Position
bits : 8 - 9 (2 bit)
access : read-write
PULSEMODELO : Low Side Output Pulse Position
bits : 10 - 11 (2 bit)
access : read-write
Channel B-High Duty-0 Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel B-High Duty-1 Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel B-High Heightened-Precision Duty-0 Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel B-High Heightened-Precision Duty-1 Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Trip Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN0A : Enable TRIP0 as a trip source for Channel A
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : TRIP0A_DIS
Disable TRIP0 for Channel A
1 : TRIP0A_EN
Enable TRIP0 for Channel A
End of enumeration elements list.
MODE0A : Mode of TRIP0 for Channel A
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : TRIP0A_FLT
Fault Trip on TRIP0 Input
1 : TRIP0A_RSTRT
Self Restart on TRIP0 Input
End of enumeration elements list.
EN1A : Enable TRIP1 as a trip source for Channel A
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : TRIP1A_DIS
Disable TRIP1 for Channel A
1 : TRIP1A_EN
Enable TRIP1 for Channel A
End of enumeration elements list.
MODE1A : Mode of TRIP1 for Channel A
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : TRIP1A_FLT
Fault Trip on TRIP1 Input
1 : TRIP1A_RSTRT
Self Restart on TRIP1 Input
End of enumeration elements list.
EN0AL : Enable TRIP0 for Channel A Low Side
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : TRIP0AL_DIS
Disable Trip0 for Channel A Low Side
1 : TRIP0AL_EN
Enable Trip0 for Channel A Low Side
End of enumeration elements list.
EN0SELA : TRIP0 Enable Select for Channel A Low Side
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : TRIP0SEL_EN0A
Select EN0A for Channel A Low Side Trip0 Enable
1 : TRIP0SEL_EN0AL
Select EN0AL for Channel A Low Side Trip0 Enable
End of enumeration elements list.
EN1AL : Enable TRIP1 for Channel A Low Side
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : TRIP1AL_DIS
Disable Trip1 for Channel A Low Side
1 : TRIP1AL_EN
Enable Trip1 for Channel A Low Side
End of enumeration elements list.
EN1SELA : TRIP1 Enable Select for Channel A Low Side
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : TRIP1SEL_EN0A
Select EN0A for Channel A Low Side Trip1 Enable
1 : TRIP1SEL_EN0AL
Select EN0AL for Channel A Low Side Trip1 Enable
End of enumeration elements list.
EN0B : Enable TRIP0 as a trip source for Channel B
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : TRIP0B_DIS
Disable TRIP0 for Channel B
1 : TRIP0B_EN
Enable TRIP0 for Channel B
End of enumeration elements list.
MODE0B : Mode of TRIP0 for Channel B
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : TRIP0B_FLT
Fault Trip on TRIP0 Input
1 : TRIP0B_RSTRT
Self Restart on TRIP0 Input
End of enumeration elements list.
EN1B : Enable TRIP1 for Channel B
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : TRIP1B_DIS
Disable TRIP1 for Channel B
1 : TRIP1B_EN
Enable TRIP1 for Channel B
End of enumeration elements list.
MODE1B : Mode of TRIP1 for Channel B
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : TRIP1B_FLT
Fault Trip on TRIP1 Input
1 : TRIP1B_RSTRT
Self Restart on TRIP1 Input
End of enumeration elements list.
EN0BL : Enable TRIP0 for Channel B Low Side
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : TRIP0BL_DIS
Disable Trip0 for Channel B Low Side
1 : TRIP0BL_EN
Enable Trip0 for Channel B Low Side
End of enumeration elements list.
EN0SELB : TRIP0 Enable Select for Channel B Low Side
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : TRIP0SEL_EN0B
Select EN0B for Channel B Low Side Trip0 Enable
1 : TRIP0SEL_EN0BL
Select EN0BL for Channel B Low Side Trip0 Enable
End of enumeration elements list.
EN1BL : Enable TRIP1 as a trip source for Channel B Low Side
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : TRIP1BL_DIS
Disable Trip1 for Channel B Low Side
1 : TRIP1BL_EN
Enable Trip1 for Channel B Low Side
End of enumeration elements list.
EN1SELB : TRIP1 Enable Select for Channel B Low Side
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : TRIP1SEL_EN0B
Select EN0B for Channel B Low Side Trip1 Enable
1 : TRIP1SEL_EN0BL
Select EN0BL for Channel B Low Side Trip1 Enable
End of enumeration elements list.
EN0C : Enable TRIP0 for Channel C
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : TRIP0C_DIS
Disable TRIP0 for Channel C
1 : TRIP0C_EN
Enable TRIP0 for Channel C
End of enumeration elements list.
MODE0C : Mode of TRIP0 for Channel C
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : TRIP0C_FLT
Fault Trip on TRIP0 Input
1 : TRIP0C_RSTRT
Self Restart on TRIP0 Input
End of enumeration elements list.
EN1C : Enable TRIP1 as a trip source for Channel C
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : TRIP1C_DIS
Disable TRIP1 for Channel C
1 : TRIP1C_EN
Enable TRIP1 for Channel C
End of enumeration elements list.
MODE1C : Mode of TRIP1 for Channel C
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : TRIP1C_FLT
Fault Trip on TRIP1 Input
1 : TRIP1C_RSTRT
Self Restart on TRIP1 Input
End of enumeration elements list.
EN0CL : Enable TRIP0 for Channel C Low Side
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : TRIP0CL_DIS
Disable Trip0 for Channel C Low Side
1 : TRIP0CL_EN
Enable Trip0 for Channel C Low Side
End of enumeration elements list.
EN0SELC : TRIP0 Enable Select for Channel C Low Side
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : TRIP0SEL_EN0C
Select EN0C for Channel C Low Side Trip0 Enable
1 : TRIP0SEL_EN0CL
Select EN0CL for Channel C Low Side Trip0 Enable
End of enumeration elements list.
EN1CL : Enable TRIP1 for Channel C Low Side
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : TRIP1CL_DIS
Disable Trip1 for Channel C Low Side
1 : TRIP1CL_EN
Enable Trip1 for Channel C Low Side
End of enumeration elements list.
EN1SELC : TRIP1 Enable Select for Channel C Low Side
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : TRIP1SEL_EN0C
Select EN0C for Channel C Low Side Trip1 Enable
1 : TRIP1SEL_EN0CL
Select EN0CL for Channel C Low Side Trip1 Enable
End of enumeration elements list.
EN0D : Enable TRIP0 for Channel D
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : TRIP0D_DIS
Disable TRIP0 for Channel D
1 : TRIP0D_EN
Enable TRIP0 for Channel D
End of enumeration elements list.
MODE0D : Mode of TRIP0 for Channel D
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : TRIP0D_FLT
Fault Trip on TRIP0 Input
1 : TRIP0D_RSTRT
Self Restart on TRIP0 Input
End of enumeration elements list.
EN1D : Enable TRIP1 for Channel D
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TRIP1D_DIS
Disable TRIP1 for Channel D
1 : TRIP1D_EN
Enable TRIP1 for Channel D
End of enumeration elements list.
MODE1D : Mode of TRIP1 for Channel D
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : TRIP1D_FLT
Fault Trip on TRIP1 Input
1 : TRIP1D_RSTRT
Self Restart on TRIP1 Input
End of enumeration elements list.
EN0DL : Enable TRIP0 for Channel D Low Side
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : TRIP0DL_DIS
Disable Trip0 for Channel D Low Side
1 : TRIP0DL_EN
Enable Trip0 for Channel D Low Side
End of enumeration elements list.
EN0SELD : TRIP0 Enable Select for Channel D Low Side
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0 : TRIP0SEL_EN0D
Select EN0D for Channel D Low Side Trip0 Enable
1 : TRIP0SEL_EN0DL
Select EN0DL for Channel D Low Side Trip0 Enable
End of enumeration elements list.
EN1DL : Enable TRIP1 for Channel D Low Side
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
0 : TRIP1DL_DIS
Disable Trip1 for Channel D Low Side
1 : TRIP1DL_EN
Enable Trip1 for Channel D Low Side
End of enumeration elements list.
EN1SELD : TRIP1 Enable Select for Channel D Low Side
bits : 31 - 31 (1 bit)
access : read-write
Enumeration:
0 : TRIP1SEL_EN0D
Select EN0D for Channel D Low Side Trip1 Enable
1 : TRIP1SEL_EN0DL
Select EN0DL for Channel D Low Side Trip1 Enable
End of enumeration elements list.
Channel B-Low Duty-0 Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel B-Low Duty-1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel B-Low Heightened-Precision Duty-0 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel B-Low Heightened-Precision Duty-1 Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel C Control Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISHI : Channel High Side Output Disable
bits : 0 - 0 (1 bit)
access : read-write
DISLO : Channel Low Side Output Disable
bits : 1 - 1 (1 bit)
access : read-write
XOVR : high-low Crossover Enable
bits : 2 - 2 (1 bit)
access : read-write
PULSEMODEHI : High Side Output Pulse Position
bits : 8 - 9 (2 bit)
access : read-write
PULSEMODELO : Low Side Output Pulse Position
bits : 10 - 11 (2 bit)
access : read-write
Channel C-High Pulse Duty Register 0
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel C-High Pulse Duty Register 1
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel C-High Pulse Heightened-Precision Duty Register 0
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel C-High Pulse Heightened-Precision Duty Register 1
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel C-Low Pulse Duty Register 0
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel C-Low Duty-1 Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel C-Low Pulse Duty Register 1
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel C-Low Heightened-Precision Duty-1 Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel D Control Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISHI : Channel High Side Output Disable
bits : 0 - 0 (1 bit)
access : read-write
DISLO : Channel Low Side Output Disable
bits : 1 - 1 (1 bit)
access : read-write
XOVR : high-low Crossover Enable
bits : 2 - 2 (1 bit)
access : read-write
PULSEMODEHI : High Side Output Pulse Position
bits : 8 - 9 (2 bit)
access : read-write
PULSEMODELO : Low Side Output Pulse Position
bits : 10 - 11 (2 bit)
access : read-write
Channel D-High Duty-0 Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel D-High Pulse Duty Register 1
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIP0 : Status bit set when TRIP0 is active low
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_TRIP0
TRIP0 status is not tripped
1 : TRIP0
TRIP0 status is tripped (active low)
End of enumeration elements list.
TRIP1 : Status bit set when TRIP1 is active low
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NO_TRIP1
TRIP1 status is not tripped
1 : TRIP1
TRIP1 status is tripped (active low)
End of enumeration elements list.
RAWTRIP0 : Raw Trip 0 Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : TRIP0LVL_LO
TRIP0 Level is Low
1 : TRIP0LVL_HI
TRIP0 Level is High
End of enumeration elements list.
RAWTRIP1 : Raw Trip 1 Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : TRIP1LVL_LO
TRIP1 Level is Low
1 : TRIP1LVL_HI
TRIP1 Level is High
End of enumeration elements list.
FLTTRIPA : Fault Trip Status for Channel A
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : FLTA_NOTRIP
Channel A Fault Trip Status is not tripped
1 : FLTA_TRIP
Channel A Fault Trip Status is tripped
End of enumeration elements list.
SRTRIPA : Self-Restart Trip Status for Channel A
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : SRA_NOTRIP
Channel A Self-Restart Trip Status is not tripped
1 : SRA_TRIP
Channel A Self-Restart Trip Status is tripped
End of enumeration elements list.
FLTTRIPB : Fault Trip Status for Channel B
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : FLTB_NOTRIP
Channel B Fault Trip Status is not tripped
1 : FLTB_TRIP
Channel A Fault Trip Status is tripped
End of enumeration elements list.
SRTRIPB : Self-Restart Trip Status for Channel B
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : SRB_NOTRIP
Channel B Self-Restart Trip Status is not tripped
1 : SRB_TRIP
Channel B Self-Restart Trip Status is tripped
End of enumeration elements list.
FLTTRIPC : Fault Trip Status for Channel C
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : FLTC_NOTRIP
Channel C Fault Trip Status is not tripped
1 : FLTC_TRIP
Channel C Fault Trip Status is tripped
End of enumeration elements list.
SRTRIPC : Self-Restart Trip Status for Channel C
bits : 9 - 9 (1 bit)
access : read-only
Enumeration:
0 : SRC_NOTRIP
Channel C Self-Restart Trip Status is not tripped
1 : SRC_TRIP
Channel C Self-Restart Trip Status is tripped
End of enumeration elements list.
FLTTRIPD : Fault Trip Status for Channel D
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : FLTD_NOTRIP
Channel D Fault Trip Status is not tripped
1 : FLTD_TRIP
Channel D Fault Trip Status is tripped
End of enumeration elements list.
SRTRIPD : Self-Restart Trip Status for Channel D
bits : 11 - 11 (1 bit)
access : read-only
Enumeration:
0 : SRD_NOTRIP
Channel D Self-Restart Trip Status is not tripped
1 : SRD_TRIP
Channel D Self-Restart Trip Status is tripped
End of enumeration elements list.
TMR0PER : PWMTMR0 Period Boundary Status
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : NOT_PER0
PWMTMR0 period boundary not reached
1 : PER0
PWMTMR0 period boundary reached
End of enumeration elements list.
TMR1PER : PWMTMR1 Period Boundary Status
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : NOT_PER1
PWMTMR1 period boundary not reached
1 : PER1
PWMTMR1 period boundary reached
End of enumeration elements list.
TMR2PER : PWMTMR2 Period Boundary Status
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : NOT_PER2
PWMTMR2 period boundary not reached
1 : PER2
PWMTMR2 period boundary reached
End of enumeration elements list.
TMR3PER : PWMTMR3 Period Boundary Status
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : NOT_PER3
PWMTMR3 period boundary not reached
1 : PER3
PWMTMR3 period boundary reached
End of enumeration elements list.
TMR4PER : PWMTMR4 Period Boundary Status
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NOT_PER4
PWMTMR4 period boundary not reached
1 : PER4
PWMTMR4 period boundary reached
End of enumeration elements list.
TMR0PHASE : PWMTMR0 Phase Status
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : TMR0PH1
1st Half Phase
1 : TMR0PH2
2nd Half Phase
End of enumeration elements list.
TMR1PHASE : PWMTMR1 Phase Status
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : TMR1PH1
1st Half Phase
1 : TMR1PH2
2nd Half Phase
End of enumeration elements list.
TMR2PHASE : PWMTMR2 Phase Status
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : TMR2PH1
1st Half Phase
1 : TMR2PH2
2nd Half Phase
End of enumeration elements list.
TMR3PHASE : PWMTMR3 Phase Status
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : TMR3PH1
1st Half Phase
1 : TMR3PH2
2nd Half Phase
End of enumeration elements list.
TMR4PHASE : PWMTMR4 Phase Status
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : TMR4PH1
1st Half Phase
1 : TMR4PH2
2nd Half Phase
End of enumeration elements list.
EMU : Emulator Status
bits : 30 - 30 (1 bit)
access : read-write
HPRDY : Heightened-Precision Ready Status
bits : 31 - 31 (1 bit)
access : read-only
Enumeration:
0 : NOT_HPRDY
HPPWM Not Ready For Operation
1 : HPRDY
HPPWM Ready For Operation
End of enumeration elements list.
Channel D-High Pulse Heightened-Precision Duty Register 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel D High Pulse Heightened-Precision Duty Register 1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel D-Low Pulse Duty Register 0
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel D-Low Pulse Duty Register 1
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DUTY : Duty Cycle De-Asserted Count
bits : 0 - 15 (16 bit)
access : read-write
Channel D-Low Heightened-Precision Duty-0 Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel D-Low Heightened-Precision Duty-1 Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXDIV : Maximum Precision Supplementary Divider Bits
bits : 0 - 5 (6 bit)
access : read-write
ENHDIV : Enhanced Precision Divider Bits
bits : 6 - 7 (2 bit)
access : read-write
Channel A-High Full Duty0 Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel A-High Full Duty1 Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel A-Low Full Duty0 Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel A-Low Full Duty1 Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel B-High Full Duty0 Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel B-High Full Duty1 Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel B-Low Full Duty0 Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel B-Low Full Duty1 Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel C-High Full Duty0 Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
Channel C-High Full Duty1 Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENHDIV : Enhanced Precision Divider Bits
bits : 14 - 15 (2 bit)
access : read-write
DUTY : Coarse Duty Value
bits : 16 - 31 (16 bit)
access : read-write
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