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SPU0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTL

AP[0]

WP[2]

IDTLS

IADDR

WP[3]

AP[1]

WP[4]

WP[5]

DEVID

DEVTYPE

PID4

PID5

PID6

PID7

PID0

PID1

PID2

PID3

CID0

CID1

CID2

CID3

AP[2]

WP[6]

WP[7]

AP[3]

WP[8]

WP[9]

AP[4]

WP[10]

WP[11]

AP[5]

WP[12]

WP[13]

STAT

TIMEOUT

WP0

WP1

AP[6]

WP2

WP3

WP4

WP5

WP6

WP[14]

WP7

WP8

WP9

WP10

WP11

WP12

WP13

WP14

WP15

WP16

WP17

WP18

WP19

WP[15]

AP[7]

WP[16]

WP[17]

AP[8]

WP[18]

WP[19]

AP[9]

AP[10]

AP[11]

AP[12]

AP[13]

WP[0]

AP0

AP1

AP2

AP3

AP4

AP5

AP6

AP[14]

AP7

AP8

AP9

AP10

AP11

AP12

AP13

AP14

AP15

AP16

AP17

AP18

AP19

AP[15]

AP[16]

AP[17]

AP[18]

AP[19]

WP[1]


CTL

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTL CTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLCK PINTEN WPLCK APLCK TOMON

GLCK : Global Lock
bits : 0 - 7 (8 bit)
access : read-write

PINTEN : Protection Violation Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

WPLCK : Write Protect Register Lock
bits : 16 - 16 (1 bit)
access : read-write

APLCK : Access Protect Register Lock
bits : 18 - 18 (1 bit)
access : read-write

TOMON : Timeout Monitor
bits : 20 - 20 (1 bit)
access : read-write


AP[0]

Access Protect Register n
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[0] AP[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[2]

Write Protect Register n
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[2] WP[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


IDTLS

Interrupt Details Register
address_offset : 0x1080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDTLS IDTLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SECURE RNW ID

SECURE : Secure Status
bits : 0 - 0 (1 bit)
access : read-only

RNW : Read/Write Status
bits : 1 - 1 (1 bit)
access : read-only

ID : ID of Transaction
bits : 8 - 23 (16 bit)
access : read-only


IADDR

Interrupt Address Register
address_offset : 0x1084 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IADDR IADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Violation Address
bits : 0 - 31 (32 bit)
access : read-only


WP[3]

Write Protect Register n
address_offset : 0x1418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[3] WP[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[1]

Access Protect Register n
address_offset : 0x1804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[1] AP[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[4]

Write Protect Register n
address_offset : 0x1828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[4] WP[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[5]

Write Protect Register n
address_offset : 0x1C3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[5] WP[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


DEVID

Device Configuration Register
address_offset : 0x1FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVID DEVID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ITYPE NS CMCNT SMCNT ENDPTCNT

ITYPE : Interface Type
bits : 0 - 2 (3 bit)
access : read-only

NS : No Security
bits : 4 - 4 (1 bit)
access : read-only

CMCNT : Core Master Count
bits : 6 - 10 (5 bit)
access : read-only

SMCNT : System Master Count
bits : 11 - 15 (5 bit)
access : read-only

ENDPTCNT : End Point Count
bits : 16 - 24 (9 bit)
access : read-only


DEVTYPE

Device Type Identifier Register
address_offset : 0x1FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVTYPE DEVTYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Device Type
bits : 0 - 31 (32 bit)
access : read-only


PID4

Peripheral ID4 Register
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID4 PID4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEOP106CC SIZE

JEOP106CC : JEOP106 continuation code (number of leading 0x7Fs)
bits : 0 - 3 (4 bit)
access : read-only

SIZE : Number of 4k blocks
bits : 4 - 7 (4 bit)
access : read-only


PID5

Peripheral ID5 Register
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID5 PID5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUTUREUSE

FUTUREUSE : For future use
bits : 0 - 7 (8 bit)
access : read-only


PID6

Peripheral ID6 Register
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID6 PID6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUTUREUSE

FUTUREUSE : For future use
bits : 0 - 7 (8 bit)
access : read-only


PID7

Peripheral ID7 Register
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID7 PID7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUTUREUSE

FUTUREUSE : For future use
bits : 0 - 7 (8 bit)
access : read-only


PID0

Peripheral ID0 Register
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID0 PID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM

PARTNUM : PARTNUM[7:0] Part number for component identification. SPU in this case
bits : 0 - 7 (8 bit)
access : read-only


PID1

Peripheral ID1 Register
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID1 PID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PARTNUM JEP106

PARTNUM : PARTNUM[11:8] Part number for component identification. SPU in this case
bits : 0 - 3 (4 bit)
access : read-only

JEP106 : JEDEC JEP106 Manufacturer ID code
bits : 4 - 31 (28 bit)
access : read-only


PID2

Peripheral ID2 Register
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID2 PID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 JEP106 JEDECASGN REV

JEP106 : JEDEC JEP106 Manufacturer ID code
bits : 0 - 2 (3 bit)
access : read-only

JEDECASGN : A JEDEC Assigned Value is Used. Indicates that a JEDEC assigned value is used.
bits : 3 - 3 (1 bit)
access : read-only

REV : Peripheral Revision
bits : 4 - 7 (4 bit)
access : read-only


PID3

Peripheral ID3 Register
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PID3 PID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUSTMOD REVAND

CUSTMOD : Customer Modified
bits : 0 - 3 (4 bit)
access : read-only

REVAND : Metal fix revision
bits : 4 - 7 (4 bit)
access : read-only


CID0

Component ID0 Register
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CID0 CID0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : Component ID Preamble. Identifies this as a Component ID Register
bits : 0 - 7 (8 bit)
access : read-only


CID1

Component ID1 Register
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CID1 CID1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE COMPCLASS

PREAMBLE : Component ID Preamble. Identifies this as a Component ID Register
bits : 0 - 3 (4 bit)
access : read-only

COMPCLASS : Component Class
bits : 4 - 7 (4 bit)
access : read-only


CID2

Component ID2 Register
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CID2 CID2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : Component ID Preamble. Identifies this as a Component ID Register
bits : 0 - 7 (8 bit)
access : read-only


CID3

Component ID3 Register
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CID3 CID3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PREAMBLE

PREAMBLE : Component ID Preamble. Identifies this as a Component ID Register
bits : 0 - 7 (8 bit)
access : read-only


AP[2]

Access Protect Register n
address_offset : 0x200C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[2] AP[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[6]

Write Protect Register n
address_offset : 0x2054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[6] WP[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[7]

Write Protect Register n
address_offset : 0x2470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[7] WP[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[3]

Access Protect Register n
address_offset : 0x2818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[3] AP[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[8]

Write Protect Register n
address_offset : 0x2890 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[8] WP[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[9]

Write Protect Register n
address_offset : 0x2CB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[9] WP[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[4]

Access Protect Register n
address_offset : 0x3028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[4] AP[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[10]

Write Protect Register n
address_offset : 0x30DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[10] WP[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[11]

Write Protect Register n
address_offset : 0x3508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[11] WP[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[5]

Access Protect Register n
address_offset : 0x383C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[5] AP[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[12]

Write Protect Register n
address_offset : 0x3938 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[12] WP[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[13]

Write Protect Register n
address_offset : 0x3D6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[13] WP[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


STAT

Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GLCK VIRQ TIRQ TOERR ADDRERR LWERR

GLCK : Global Lock Status
bits : 0 - 0 (1 bit)
access : read-only

VIRQ : Violation Interrupt Request
bits : 12 - 12 (1 bit)
access : read-write

TIRQ : Timeout Interrupt
bits : 13 - 13 (1 bit)
access : read-write

TOERR : Timeout Error
bits : 29 - 29 (1 bit)
access : read-only

ADDRERR : Address Error
bits : 30 - 30 (1 bit)
access : read-write

LWERR : Lock Write Error
bits : 31 - 31 (1 bit)
access : read-write


TIMEOUT

Timeout Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMEOUT TIMEOUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Timeout Counter Value
bits : 0 - 15 (16 bit)
access : read-write


WP0

Write Protect Register n
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP0 WP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP1

Write Protect Register n
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP1 WP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[6]

Access Protect Register n
address_offset : 0x4054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[6] AP[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP2

Write Protect Register n
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP2 WP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP3

Write Protect Register n
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP3 WP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP4

Write Protect Register n
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP4 WP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP5

Write Protect Register n
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP5 WP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP6

Write Protect Register n
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP6 WP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[14]

Write Protect Register n
address_offset : 0x41A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[14] WP[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP7

Write Protect Register n
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP7 WP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP8

Write Protect Register n
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP8 WP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP9

Write Protect Register n
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP9 WP9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP10

Write Protect Register n
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP10 WP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP11

Write Protect Register n
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP11 WP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP12

Write Protect Register n
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP12 WP12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP13

Write Protect Register n
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP13 WP13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP14

Write Protect Register n
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP14 WP14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP15

Write Protect Register n
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP15 WP15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP16

Write Protect Register n
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP16 WP16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP17

Write Protect Register n
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP17 WP17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP18

Write Protect Register n
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP18 WP18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP19

Write Protect Register n
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP19 WP19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[15]

Write Protect Register n
address_offset : 0x45E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[15] WP[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[7]

Access Protect Register n
address_offset : 0x4870 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[7] AP[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[16]

Write Protect Register n
address_offset : 0x4A20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[16] WP[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[17]

Write Protect Register n
address_offset : 0x4E64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[17] WP[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[8]

Access Protect Register n
address_offset : 0x5090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[8] AP[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[18]

Write Protect Register n
address_offset : 0x52AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[18] WP[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[19]

Write Protect Register n
address_offset : 0x56F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[19] WP[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[9]

Access Protect Register n
address_offset : 0x58B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[9] AP[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[10]

Access Protect Register n
address_offset : 0x60DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[10] AP[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[11]

Access Protect Register n
address_offset : 0x6908 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[11] AP[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[12]

Access Protect Register n
address_offset : 0x7138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[12] AP[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[13]

Access Protect Register n
address_offset : 0x796C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[13] AP[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[0]

Write Protect Register n
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[0] WP[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP0

Access Protect Register n
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP0 AP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP1

Access Protect Register n
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP1 AP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP2

Access Protect Register n
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP2 AP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP3

Access Protect Register n
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP3 AP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP4

Access Protect Register n
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP4 AP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP5

Access Protect Register n
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP5 AP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP6

Access Protect Register n
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP6 AP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[14]

Access Protect Register n
address_offset : 0x81A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[14] AP[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP7

Access Protect Register n
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP7 AP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP8

Access Protect Register n
address_offset : 0x820 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP8 AP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP9

Access Protect Register n
address_offset : 0x824 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP9 AP9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP10

Access Protect Register n
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP10 AP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP11

Access Protect Register n
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP11 AP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP12

Access Protect Register n
address_offset : 0x830 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP12 AP12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP13

Access Protect Register n
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP13 AP13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP14

Access Protect Register n
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP14 AP14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP15

Access Protect Register n
address_offset : 0x83C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP15 AP15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP16

Access Protect Register n
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP16 AP16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP17

Access Protect Register n
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP17 AP17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP18

Access Protect Register n
address_offset : 0x848 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP18 AP18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP19

Access Protect Register n
address_offset : 0x84C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP19 AP19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[15]

Access Protect Register n
address_offset : 0x89E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[15] AP[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[16]

Access Protect Register n
address_offset : 0x9220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[16] AP[16] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[17]

Access Protect Register n
address_offset : 0x9A64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[17] AP[17] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[18]

Access Protect Register n
address_offset : 0xA2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[18] AP[18] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


AP[19]

Access Protect Register n
address_offset : 0xAAF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AP[19] AP[19] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMAn SMAn

CMAn : Core Master x Access Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMAn : System Master x Access Protect Enable
bits : 16 - 16 (1 bit)
access : read-write


WP[1]

Write Protect Register n
address_offset : 0xC04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WP[1] WP[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMn SMn

CMn : Core Master x Write Protect Enable
bits : 0 - 1 (2 bit)
access : read-write

SMn : System Master x Write Protect Enable
bits : 16 - 16 (1 bit)
access : read-write



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