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HAE0

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x8000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CFG4

DIDT_GAIN

DIDT_COEF

VLEVEL

H00_INDX

H01_INDX

H02_INDX

H03_INDX

H04_INDX

H05_INDX

H06_INDX

H07_INDX

H08_INDX

H09_INDX

H10_INDX

H11_INDX

RUN

CFG0

CFG1

CFG2

CFG3

STAT

ISAMPLE

VSAMPLE

IWAVEFORM

VWAVEFORM


CFG4

Configuration 4 Register
address_offset : 0x1E00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG4 CFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HPFEN DIDTEN

HPFEN : High-Pass Filter Enable
bits : 0 - 0 (1 bit)
access : read-write

DIDTEN : di/dt (Sensor) Enable
bits : 1 - 1 (1 bit)
access : read-write


DIDT_GAIN

DIDT Gain Register
address_offset : 0x1E04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIDT_GAIN DIDT_GAIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : di/dt Sensor Gain
bits : 0 - 27 (28 bit)
access : read-write


DIDT_COEF

DIDT Coefficient Register
address_offset : 0x1E08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIDT_COEF DIDT_COEF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : di/dt Coefficient
bits : 0 - 27 (28 bit)
access : read-write


VLEVEL

Voltage Level Register
address_offset : 0x1E10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLEVEL VLEVEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Voltage Input Level
bits : 0 - 27 (28 bit)
access : read-write


H00_INDX

Harmonic n Index Register
address_offset : 0x1E2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H00_INDX H00_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H01_INDX

Harmonic n Index Register
address_offset : 0x1E30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H01_INDX H01_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H02_INDX

Harmonic n Index Register
address_offset : 0x1E34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H02_INDX H02_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H03_INDX

Harmonic n Index Register
address_offset : 0x1E38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H03_INDX H03_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H04_INDX

Harmonic n Index Register
address_offset : 0x1E3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H04_INDX H04_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H05_INDX

Harmonic n Index Register
address_offset : 0x1E40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H05_INDX H05_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H06_INDX

Harmonic n Index Register
address_offset : 0x1E44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H06_INDX H06_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H07_INDX

Harmonic n Index Register
address_offset : 0x1E48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H07_INDX H07_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H08_INDX

Harmonic n Index Register
address_offset : 0x1E4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H08_INDX H08_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H09_INDX

Harmonic n Index Register
address_offset : 0x1E50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H09_INDX H09_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H10_INDX

Harmonic n Index Register
address_offset : 0x1E54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H10_INDX H10_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


H11_INDX

Harmonic n Index Register
address_offset : 0x1E58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

H11_INDX H11_INDX read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Harmonic n Index
bits : 0 - 5 (6 bit)
access : read-write


RUN

Run Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RUN RUN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RUN

RUN : Run/Stop
bits : 0 - 0 (1 bit)
access : read-write


CFG0

Configuration 0 Register
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG0 CFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LFREQ CLR_PERR PERR_EN TXIRQEN RXIRQEN

LFREQ : Line Frequency Select
bits : 1 - 1 (1 bit)
access : read-write

CLR_PERR : Clear Parity Status
bits : 4 - 4 (1 bit)
access : read-only

PERR_EN : Parity Enable
bits : 5 - 5 (1 bit)
access : read-write

TXIRQEN : Transmit IRQ Enable
bits : 6 - 6 (1 bit)
access : read-write

RXIRQEN : Receive IRQ Enable
bits : 7 - 7 (1 bit)
access : read-write


CFG1

Configuration 1 Register
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG1 CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STARTDIV

STARTDIV : Start (Clock) Divider
bits : 0 - 14 (15 bit)
access : read-write


CFG2

Configuration 2 Register
address_offset : 0xB08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG2 CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE SETTLE UPDATE EN

MODE : (Results) Mode Select
bits : 0 - 0 (1 bit)
access : read-write

SETTLE : Settle Period Select
bits : 1 - 2 (2 bit)
access : read-write

UPDATE : Update Rate Select
bits : 3 - 5 (3 bit)
access : read-write

EN : Enable Clock
bits : 6 - 6 (1 bit)
access : read-write


CFG3

Configuration 3 Register
address_offset : 0xB0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG3 CFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANEN

CHANEN : Channel n Enable
bits : 0 - 12 (13 bit)
access : read-write


STAT

Status Register
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STAT STAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXIRQ RXIRQ RDY PERR_STAT

TXIRQ : Transmit IRQ Status
bits : 0 - 0 (1 bit)
access : read-write

RXIRQ : Receive IRQ Status
bits : 1 - 1 (1 bit)
access : read-write

RDY : Ready Status
bits : 2 - 2 (1 bit)
access : read-only

PERR_STAT : Parity Error Status
bits : 3 - 3 (1 bit)
access : read-only


ISAMPLE

I (Current) Sample Register
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISAMPLE ISAMPLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Input Sample
bits : 0 - 23 (24 bit)
access : read-write


VSAMPLE

V (Voltage) Sample Register
address_offset : 0xB44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VSAMPLE VSAMPLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Voltage Input Sample
bits : 0 - 23 (24 bit)
access : read-write


IWAVEFORM

I (Current) Waveform Register
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWAVEFORM IWAVEFORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Current Waveform
bits : 0 - 23 (24 bit)
access : read-only


VWAVEFORM

V (Voltage) Waveform Register
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VWAVEFORM VWAVEFORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Voltage Waveform
bits : 0 - 23 (24 bit)
access : read-only



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