Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Pointer to Next Initial Descriptor Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Pointer to Next Descriptor Set
bits : 0 - 31 (32 bit)
access : read-write
Inner Loop Address Increment Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Inner Loop Address Increment in Bytes
bits : 0 - 31 (32 bit)
access : read-write
Outer Loop Count Start Value (2D only) Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Work Unit Inner Loop Counter Current Value
bits : 0 - 31 (32 bit)
access : read-write
Outer Loop Address Increment (2D only) Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Outer Loop Address Increment in Bytes
bits : 0 - 31 (32 bit)
access : read-write
Current Descriptor Pointer Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Pointer for Current Descriptor Element
bits : 0 - 31 (32 bit)
access : read-write
Previous Initial Descriptor Pointer Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDPO : Previous Descriptor Pointer Overrun
bits : 0 - 0 (1 bit)
access : read-only
DESCPPREV : Descriptor Pointer for Previous Element
bits : 2 - 31 (30 bit)
access : read-only
Current Address Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Work Unit Current Address Value
bits : 0 - 31 (32 bit)
access : read-write
Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IRQDONE : Work Unit/Row Done Interrupt
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NO_IRQ
Inactive
1 : IRQDONE
Active
End of enumeration elements list.
IRQERR : Error Interrupt Request
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NO_IRQERR
No Error
1 : IRQERR
Error Occurred
End of enumeration elements list.
PIRQ : Peripheral Interrupt Request
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NO_PIRQ
No Interrupt request
1 : PIRQ
Interrupt Request signaled by peripheral
End of enumeration elements list.
ERRC : Error Cause
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
0 : CFGERR
Configuration Error
1 : ILLWRERR
Illegal Write Occurred While Channel Running
2 : ALGNERR
Address Alignment Error
3 : MEMERR
Memory Access or Fabric Error
5 : TRGOVERR
Trigger Overrun
6 : BWMONERR
Bandwidth Monitor Error
End of enumeration elements list.
RUN : Run Status
bits : 8 - 10 (3 bit)
access : read-only
Enumeration:
0 : STOPPED
Idle/Stop State
1 : DSCFETCH
Descriptor Fetch
2 : DATAXFER
Data Transfer
3 : TRGWAIT
Waiting for Trigger
4 : ACKWAIT
Waiting for Write ACK/FIFO Drain to Peripheral
End of enumeration elements list.
PBWID : Peripheral Bus Width
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0 : PBUS01
1 Byte
1 : PBUS02
2 Bytes
2 : PBUS04
4 Bytes
3 : PBUS08
8 Bytes
End of enumeration elements list.
MBWID : Memory Bus Width
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0 : MBUS02
2 Bytes
1 : MBUS04
4 Bytes
2 : MBUS08
8 Bytes
3 : MBUS16
16 Bytes
End of enumeration elements list.
FIFOFILL : FIFO Fill Status
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0 : FIFOEMPTY
Empty
1 : FIFO25
Empty < FIFO = 1/4 Full
2 : FIFO50
1/4 Full < FIFO = 1/2 Full
3 : FIFO75
1/2 Full < FIFO = 3/4 Full
4 : FIFONEARFULL
3/4 Full < FIFO = Full
7 : FIFOFULL
Full
End of enumeration elements list.
TWAIT : Trigger Wait Status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : NOTRIGRX
No Trigger Received
1 : TRIGRX
Trigger Received
End of enumeration elements list.
Current Count (1D) or Intra-row XCNT (2D) Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Work Unit Outer Loop Counter Start Value
bits : 0 - 31 (32 bit)
access : read-only
Current Row Count (2D only) Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Work Unit Outer Loop Counter Current Value
bits : 0 - 31 (32 bit)
access : read-only
Start Address of Current Buffer Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Work Unit Address Start Value
bits : 0 - 31 (32 bit)
access : read-write
Bandwidth Limit Count Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Bandwidth Limit Count
bits : 0 - 15 (16 bit)
access : read-write
Bandwidth Limit Count Current Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Bandwidth Limit Count Current
bits : 0 - 15 (16 bit)
access : read-only
Bandwidth Monitor Count Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Bandwidth Monitor Count
bits : 0 - 31 (32 bit)
access : read-write
Bandwidth Monitor Count Current Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Bandwidth Monitor Count Current
bits : 0 - 31 (32 bit)
access : read-only
Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DIS
Disable
1 : EN
Enable
End of enumeration elements list.
WNR : Write/Read Channel Direction
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : READ
Transmit (Read from memory)
1 : WRITE
Receive (Write to memory)
End of enumeration elements list.
SYNC : Synchronize Work Unit Transitions
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NO_SYNC
No Synchronization
1 : SYNC
Synchronize Channel
End of enumeration elements list.
CADDR : Use Current Address
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : LD_STARTADDR
Load Starting Address
1 : LD_CURADDR
Use Current Address
End of enumeration elements list.
PSIZE : Peripheral Transfer Word Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0 : PSIZE01
1 Byte
1 : PSIZE02
2 Bytes
2 : PSIZE04
4 Bytes
3 : PSIZE08
8 Bytes
End of enumeration elements list.
MSIZE : Memory Transfer Word Size
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0 : MSIZE01
1 Byte
1 : MSIZE02
2 Bytes
2 : MSIZE04
4 Bytes
3 : MSIZE08
8 Bytes
4 : MSIZE16
16 Bytes
5 : MSIZE32
32 Bytes
End of enumeration elements list.
FLOW : Next Operation
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0 : STOP
STOP.
1 : AUTO
AUTO.
4 : DSCLIST
DSCL.
5 : DSCARRAY
DSCA.
6 : DODLIST
Descriptor On-Demand List.
7 : DODARRAY
Descriptor On Demand Array.
End of enumeration elements list.
TWAIT : Wait for Trigger
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : NO_TRGWAIT
Begin Work Unit Automatically (No Wait)
1 : TRGWAIT
Wait for Trigger (Halt before Work Unit)
End of enumeration elements list.
NDSIZE : Next Descriptor Set Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : FETCH01
Fetch One Descriptor Element
1 : FETCH02
Fetch Two Descriptor Elements
2 : FETCH03
Fetch Three Descriptor Elements
3 : FETCH04
Fetch Four Descriptor Elements
4 : FETCH05
Fetch Five Descriptor Elements
5 : FETCH06
Fetch Six Descriptor Elements
6 : FETCH07
Fetch Seven Descriptor Elements
End of enumeration elements list.
INT : Generate Interrupt Request
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0 : NO_INT
Never Assert Interrupt
1 : XCNT_INT
Interrupt When X Count Expires
2 : YCNT_INT
Interrupt When Y Count Expires
3 : PERIPH_INT
Peripheral Interrupt request
End of enumeration elements list.
TRIG : Generate Outgoing Trigger
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0 : NO_TRIG
Never Assert Trigger
1 : XCNT_TRIG
Trigger When XCNTCUR Reaches 0
2 : YCNT_TRIG
Trigger When YCNTCUR Reaches 0
End of enumeration elements list.
TOVEN : Trigger Overrun Error Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : TOV_DIS
Ignore Trigger Overrun
1 : TOV_EN
Error on Trigger Overrun
End of enumeration elements list.
DESCIDCPY : Descriptor ID Copy Control
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : NO_COPY
Never Copy
1 : COPY
Copy on Work Unit Complete
End of enumeration elements list.
TWOD : Two Dimension Addressing Enable
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : ADDR1D
One-Dimensional Addressing
1 : ADDR2D
Two-Dimensional Addressing
End of enumeration elements list.
PDRF : Peripheral Data Request Forward
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : PDAT_NOTFWD
Peripheral Data Request Not Forwarded
1 : PDAT_FWD
Peripheral Data Request Forwarded
End of enumeration elements list.
Inner Loop Count Start Value Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Work Unit Inner Loop Counter Start Value
bits : 0 - 31 (32 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.