\n

PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MR

IER

IDR

IMR

ISR

CMR0

CDTY0

CPRD0

CCNT0

CUPD0

CMR1

CDTY1

CPRD1

CCNT1

CUPD1

CMR2

CDTY2

CPRD2

CCNT2

CUPD2

CMR3

CDTY3

CPRD3

CCNT3

CUPD3

ENA

DIS

SR


MR

PWM Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVA PREA DIVB PREB

DIVA : CLKA, CLKB Divide Factor
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : CLK_OFF

CLKA, CLKB clock is turned off

1 : CLK_DIV1

CLKA, CLKB clock is clock selected by PREA, PREB

End of enumeration elements list.

PREA :
bits : 8 - 11 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master Clock

0x1 : MCKDIV2

Master Clock divided by 2

0x2 : MCKDIV4

Master Clock divided by 4

0x3 : MCKDIV8

Master Clock divided by 8

0x4 : MCKDIV16

Master Clock divided by 16

0x5 : MCKDIV32

Master Clock divided by 32

0x6 : MCKDIV64

Master Clock divided by 64

0x7 : MCKDIV128

Master Clock divided by 128

0x8 : MCKDIV256

Master Clock divided by 256

0x9 : MCKDIV512

Master Clock divided by 512

0xA : MCKDIV1024

Master Clock divided by 1024

End of enumeration elements list.

DIVB : CLKA, CLKB Divide Factor
bits : 16 - 23 (8 bit)
access : read-write

Enumeration:

0 : CLK_OFF

CLKA, CLKB clock is turned off

1 : CLK_DIV1

CLKA, CLKB clock is clock selected by PREA, PREB

End of enumeration elements list.

PREB :
bits : 24 - 27 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master Clock

0x1 : MCKDIV2

Master Clock divided by 2

0x2 : MCKDIV4

Master Clock divided by 4

0x3 : MCKDIV8

Master Clock divided by 8

0x4 : MCKDIV16

Master Clock divided by 16

0x5 : MCKDIV32

Master Clock divided by 32

0x6 : MCKDIV64

Master Clock divided by 64

0x7 : MCKDIV128

Master Clock divided by 128

0x8 : MCKDIV256

Master Clock divided by 256

0x9 : MCKDIV512

Master Clock divided by 512

0xA : MCKDIV1024

Master Clock divided by 1024

End of enumeration elements list.


IER

PWM Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID.
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Channel ID.
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Channel ID.
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Channel ID.
bits : 3 - 3 (1 bit)
access : write-only


IDR

PWM Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID.
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Channel ID.
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Channel ID.
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Channel ID.
bits : 3 - 3 (1 bit)
access : write-only


IMR

PWM Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID.
bits : 0 - 0 (1 bit)
access : read-only

CHID1 : Channel ID.
bits : 1 - 1 (1 bit)
access : read-only

CHID2 : Channel ID.
bits : 2 - 2 (1 bit)
access : read-only

CHID3 : Channel ID.
bits : 3 - 3 (1 bit)
access : read-only


ISR

PWM Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only


CMR0

PWM Channel Mode Register (ch_num = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR0 CMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CPD

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master Clock

0x1 : MCKDIV2

Master Clock divided by 2

0x2 : MCKDIV4

Master Clock divided by 4

0x3 : MCKDIV8

Master Clock divided by 8

0x4 : MCKDIV16

Master Clock divided by 16

0x5 : MCKDIV32

Master Clock divided by 32

0x6 : MCKDIV64

Master Clock divided by 64

0x7 : MCKDIV128

Master Clock divided by 128

0x8 : MCKDIV256

Master Clock divided by 256

0x9 : MCKDIV512

Master Clock divided by 512

0xA : MCKDIV1024

Master Clock divided by 1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write


CDTY0

PWM Channel Duty Cycle Register (ch_num = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY0 CDTY0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write


CPRD0

PWM Channel Period Register (ch_num = 0)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD0 CPRD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write


CCNT0

PWM Channel Counter Register (ch_num = 0)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT0 CCNT0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only


CUPD0

PWM Channel Update Register (ch_num = 0)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CUPD0 CUPD0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUPD

CUPD :
bits : 0 - 31 (32 bit)
access : write-only


CMR1

PWM Channel Mode Register (ch_num = 1)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR1 CMR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CPD

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master Clock

0x1 : MCKDIV2

Master Clock divided by 2

0x2 : MCKDIV4

Master Clock divided by 4

0x3 : MCKDIV8

Master Clock divided by 8

0x4 : MCKDIV16

Master Clock divided by 16

0x5 : MCKDIV32

Master Clock divided by 32

0x6 : MCKDIV64

Master Clock divided by 64

0x7 : MCKDIV128

Master Clock divided by 128

0x8 : MCKDIV256

Master Clock divided by 256

0x9 : MCKDIV512

Master Clock divided by 512

0xA : MCKDIV1024

Master Clock divided by 1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write


CDTY1

PWM Channel Duty Cycle Register (ch_num = 1)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY1 CDTY1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write


CPRD1

PWM Channel Period Register (ch_num = 1)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD1 CPRD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write


CCNT1

PWM Channel Counter Register (ch_num = 1)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT1 CCNT1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only


CUPD1

PWM Channel Update Register (ch_num = 1)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CUPD1 CUPD1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUPD

CUPD :
bits : 0 - 31 (32 bit)
access : write-only


CMR2

PWM Channel Mode Register (ch_num = 2)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR2 CMR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CPD

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master Clock

0x1 : MCKDIV2

Master Clock divided by 2

0x2 : MCKDIV4

Master Clock divided by 4

0x3 : MCKDIV8

Master Clock divided by 8

0x4 : MCKDIV16

Master Clock divided by 16

0x5 : MCKDIV32

Master Clock divided by 32

0x6 : MCKDIV64

Master Clock divided by 64

0x7 : MCKDIV128

Master Clock divided by 128

0x8 : MCKDIV256

Master Clock divided by 256

0x9 : MCKDIV512

Master Clock divided by 512

0xA : MCKDIV1024

Master Clock divided by 1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write


CDTY2

PWM Channel Duty Cycle Register (ch_num = 2)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY2 CDTY2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write


CPRD2

PWM Channel Period Register (ch_num = 2)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD2 CPRD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write


CCNT2

PWM Channel Counter Register (ch_num = 2)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT2 CCNT2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only


CUPD2

PWM Channel Update Register (ch_num = 2)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CUPD2 CUPD2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUPD

CUPD :
bits : 0 - 31 (32 bit)
access : write-only


CMR3

PWM Channel Mode Register (ch_num = 3)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMR3 CMR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRE CALG CPOL CPD

CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write

Enumeration:

0x0 : MCK

Master Clock

0x1 : MCKDIV2

Master Clock divided by 2

0x2 : MCKDIV4

Master Clock divided by 4

0x3 : MCKDIV8

Master Clock divided by 8

0x4 : MCKDIV16

Master Clock divided by 16

0x5 : MCKDIV32

Master Clock divided by 32

0x6 : MCKDIV64

Master Clock divided by 64

0x7 : MCKDIV128

Master Clock divided by 128

0x8 : MCKDIV256

Master Clock divided by 256

0x9 : MCKDIV512

Master Clock divided by 512

0xA : MCKDIV1024

Master Clock divided by 1024

0xB : CLKA

Clock A

0xC : CLKB

Clock B

End of enumeration elements list.

CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write

CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write

CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write


CDTY3

PWM Channel Duty Cycle Register (ch_num = 3)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CDTY3 CDTY3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CDTY

CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write


CPRD3

PWM Channel Period Register (ch_num = 3)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPRD3 CPRD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPRD

CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write


CCNT3

PWM Channel Counter Register (ch_num = 3)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CCNT3 CCNT3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNT

CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only


CUPD3

PWM Channel Update Register (ch_num = 3)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CUPD3 CUPD3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CUPD

CUPD :
bits : 0 - 31 (32 bit)
access : write-only


ENA

PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ENA ENA write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only


DIS

PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DIS DIS write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only


SR

PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHID0 CHID1 CHID2 CHID3

CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only

CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only

CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only

CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only



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