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UOTGHS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

DEVCTRL

DEVIMR

DEVEPTCFG0

HSTPIPICR[1]

DEVEPTCFG1

DEVEPTCFG2

HSTPIPIFR[1]

DEVEPTCFG3

DEVEPTCFG4

HSTPIPIMR[1]

HSTPIPIER[1]

HSTPIPIDR[1]

HSTPIPINRQ[1]

DEVEPTISR0_ISOENPT

DEVEPTISR0

DEVEPTISR1

DEVEPTISR2

HSTPIPERR[1]

DEVEPTISR3

DEVIDR

DEVEPTISR4

HSTPIPCFG[2]

HSTPIPISR[2]

HSTPIPICR[2]

DEVEPTICR0_ISOENPT

DEVEPTICR0

DEVEPTICR1

HSTPIPIFR[2]

DEVEPTICR2

DEVEPTICR3

DEVEPTICR4

HSTPIPIMR[2]

HSTPIPIER[2]

DEVIER

HSTPIPIDR[2]

DEVEPTIFR0_ISOENPT

DEVEPTIFR0

HSTPIPCFG[3]

DEVEPTIFR1

HSTPIPINRQ[2]

DEVEPTIFR2

DEVEPTIFR3

DEVEPTIFR4

HSTPIPISR[3]

HSTPIPERR[2]

HSTPIPICR[3]

HSTPIPIFR[3]

DEVEPT

DEVEPTIMR0_ISOENPT

DEVEPTIMR0

DEVEPTIMR1

DEVEPTIMR2

DEVEPTIMR3

HSTPIPIMR[3]

DEVEPTIMR4

HSTPIPIER[3]

HSTPIPCFG[4]

HSTPIPIDR[3]

DEVEPTIER0_ISOENPT

DEVEPTIER0

DEVEPTIER1

HSTPIPISR[4]

DEVEPTIER2

HSTPIPINRQ[3]

DEVEPTIER3

DEVFNUM

DEVEPTCFG[0]

DEVEPTIER4

HSTPIPICR[4]

HSTPIPERR[3]

HSTPIPIFR[4]

DEVEPTIDR0_ISOENPT

DEVEPTIDR0

DEVEPTIDR1

DEVEPTIDR2

HSTPIPIMR[4]

DEVEPTIDR3

DEVEPTIDR4

HSTPIPIER[4]

HSTPIPIDR[4]

DEVEPTISR[0]

HSTPIPINRQ[4]

HSTPIPERR[4]

DEVEPTICR[0]

DEVEPTCFG[1]

DEVDMANXTDSC1

DEVDMAADDRESS1

DEVDMACONTROL1

DEVDMASTATUS1

DEVEPTIFR[0]

DEVDMANXTDSC2

DEVDMAADDRESS2

DEVDMACONTROL2

DEVDMASTATUS2

DEVDMANXTDSC3

DEVDMAADDRESS3

DEVDMACONTROL3

DEVDMASTATUS3

DEVDMANXTDSC4

DEVDMAADDRESS4

DEVDMACONTROL4

DEVDMASTATUS4

DEVEPTIMR[0]

DEVEPTISR[1]

DEVEPTIER[0]

DEVISR

HSTCTRL

HSTISR

HSTICR

DEVEPTCFG[2]

HSTIFR

HSTIMR

HSTIDR

HSTIER

HSTPIP

HSTFNUM

DEVEPTICR[1]

HSTADDR1

HSTADDR2

HSTADDR3

DEVEPTIDR[0]

DEVEPTIFR[1]

DEVEPTISR[2]

HSTPIPCFG0

HSTPIPCFG1

HSTPIPCFG2

HSTPIPCFG3

HSTPIPCFG4

DEVEPTCFG[3]

HSTPIPISR0_INTPIPES

HSTPIPISR0_ISOPIPES

HSTPIPISR0

HSTPIPISR1

HSTPIPISR2

HSTPIPISR3

HSTPIPISR4

DEVEPTIMR[1]

HSTPIPICR0_INTPIPES

HSTPIPICR0_ISOPIPES

HSTPIPICR0

HSTPIPICR1

HSTPIPICR2

HSTPIPICR3

HSTPIPICR4

DEVEPTICR[2]

HSTPIPIFR0_INTPIPES

HSTPIPIFR0_ISOPIPES

HSTPIPIFR0

HSTPIPIFR1

HSTPIPIFR2

HSTPIPIFR3

HSTPIPIFR4

HSTPIPIMR0_INTPIPES

HSTPIPIMR0_ISOPIPES

HSTPIPIMR0

HSTPIPIMR1

HSTPIPIMR2

HSTPIPIMR3

HSTPIPIMR4

DEVEPTIER[1]

HSTPIPIER0_INTPIPES

HSTPIPIER0_ISOPIPES

HSTPIPIER0

HSTPIPIER1

HSTPIPIER2

HSTPIPIER3

HSTPIPIER4

DEVEPTISR[3]

HSTPIPIDR0_INTPIPES

HSTPIPIDR0_ISOPIPES

HSTPIPIDR0

HSTPIPIDR1

DEVEPTCFG[4]

HSTPIPIDR2

HSTPIPIDR3

HSTPIPIDR4

DEVEPTIFR[2]

HSTPIPINRQ0

HSTPIPINRQ1

HSTPIPINRQ2

HSTPIPINRQ3

HSTPIPINRQ4

DEVEPTIDR[1]

HSTPIPERR0

HSTPIPERR1

HSTPIPERR2

HSTPIPERR3

HSTPIPERR4

DEVEPTICR[3]

DEVEPTIMR[2]

HSTDMANXTDSC1

HSTDMAADDRESS1

HSTDMACONTROL1

HSTDMASTATUS1

HSTDMANXTDSC2

HSTDMAADDRESS2

HSTDMACONTROL2

HSTDMASTATUS2

HSTDMANXTDSC3

HSTDMAADDRESS3

HSTDMACONTROL3

HSTDMASTATUS3

HSTDMANXTDSC4

HSTDMAADDRESS4

DEVEPTISR[4]

HSTDMACONTROL4

HSTDMASTATUS4

DEVEPTIER[2]

DEVEPTIFR[3]

DEVICR

CTRL

SR

SCR

SFR

FSM

DEVEPTICR[4]

DEVEPTIDR[2]

DEVEPTIMR[3]

DEVEPTIFR[4]

DEVEPTIER[3]

HSTPIPCFG[0]

HSTPIPISR[0]

DEVEPTIMR[4]

DEVEPTIDR[3]

HSTPIPICR[0]

HSTPIPIFR[0]

HSTPIPIMR[0]

DEVEPTIER[4]

HSTPIPIER[0]

DEVIFR

HSTPIPIDR[0]

HSTPIPINRQ[0]

DEVEPTIDR[4]

HSTPIPERR[0]

HSTPIPCFG[1]

HSTPIPISR[1]


DEVCTRL

Device General Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVCTRL DEVCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UADD ADDEN DETACH RMWKUP LS

UADD : USB Address
bits : 0 - 6 (7 bit)
access : read-write

ADDEN : Address Enable
bits : 7 - 7 (1 bit)
access : read-write

DETACH : Detach
bits : 8 - 8 (1 bit)
access : read-write

RMWKUP : Remote Wake-Up
bits : 9 - 9 (1 bit)
access : read-write

LS : Low-Speed Mode Force
bits : 12 - 12 (1 bit)
access : read-write


DEVIMR

Device Global Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVIMR DEVIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPE SOFE EORSTE WAKEUPE EORSME UPRSME PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

SUSPE : Suspend Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

SOFE : Start of Frame Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

EORSTE : End of Reset Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

WAKEUPE : Wake-Up Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

EORSME : End of Resume Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

UPRSME : Upstream Resume Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

PEP_0 : Endpoint 0 Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only

PEP_1 : Endpoint 1 Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only

PEP_2 : Endpoint 2 Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only

PEP_3 : Endpoint 3 Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only

PEP_4 : Endpoint 4 Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only

DMA_1 : DMA Channel 1 Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only

DMA_2 : DMA Channel 2 Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only

DMA_3 : DMA Channel 3 Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only

DMA_4 : DMA Channel 4 Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only


DEVEPTCFG0

Device Endpoint Configuration Register (n = 0)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DEVEPTCFG0 DEVEPTCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


HSTPIPICR[1]

Host Pipe Clear Register (n = 0)
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPICR[1] HSTPIPICR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTCFG1

Device Endpoint Configuration Register (n = 0)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DEVEPTCFG1 DEVEPTCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


DEVEPTCFG2

Device Endpoint Configuration Register (n = 0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DEVEPTCFG2 DEVEPTCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


HSTPIPIFR[1]

Host Pipe Set Register (n = 0)
address_offset : 0x10B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIFR[1] HSTPIPIFR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTCFG3

Device Endpoint Configuration Register (n = 0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DEVEPTCFG3 DEVEPTCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


DEVEPTCFG4

Device Endpoint Configuration Register (n = 0)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

DEVEPTCFG4 DEVEPTCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


HSTPIPIMR[1]

Host Pipe Mask Register (n = 0)
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIMR[1] HSTPIPIMR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIER[1]

Host Pipe Enable Register (n = 0)
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIER[1] HSTPIPIER[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIDR[1]

Host Pipe Disable Register (n = 0)
address_offset : 0x1264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIDR[1] HSTPIPIDR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPINRQ[1]

Host Pipe IN Request Register (n = 0)
address_offset : 0x12F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPINRQ[1] HSTPIPINRQ[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


DEVEPTISR0_ISOENPT

Device Endpoint Status Register (n = 0)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0

DEVEPTISR0_ISOENPT DEVEPTISR0_ISOENPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI UNDERFI OVERFI CRCERRI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

CRCERRI : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTISR0

Device Endpoint Status Register (n = 0)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTISR0 DEVEPTISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTISR1

Device Endpoint Status Register (n = 0)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTISR1 DEVEPTISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTISR2

Device Endpoint Status Register (n = 0)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTISR2 DEVEPTISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPERR[1]

Host Pipe Error Register (n = 0)
address_offset : 0x1384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPERR[1] HSTPIPERR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


DEVEPTISR3

Device Endpoint Status Register (n = 0)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTISR3 DEVEPTISR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVIDR

Device Global Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVIDR DEVIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPEC SOFEC EORSTEC WAKEUPEC EORSMEC UPRSMEC PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

SUSPEC : Suspend Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

SOFEC : Start of Frame Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

EORSTEC : End of Reset Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPEC : Wake-Up Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

EORSMEC : End of Resume Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

UPRSMEC : Upstream Resume Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

PEP_0 : Endpoint 0 Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

PEP_1 : Endpoint 1 Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only

PEP_2 : Endpoint 2 Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only

PEP_3 : Endpoint 3 Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only

PEP_4 : Endpoint 4 Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only

DMA_1 : DMA Channel 1 Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

DMA_2 : DMA Channel 2 Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

DMA_3 : DMA Channel 3 Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

DMA_4 : DMA Channel 4 Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only


DEVEPTISR4

Device Endpoint Status Register (n = 0)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTISR4 DEVEPTISR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPCFG[2]

Host Pipe Configuration Register (n = 0)
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPCFG[2] HSTPIPCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPISR[2]

Host Pipe Status Register (n = 0)
address_offset : 0x14CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPISR[2] HSTPIPISR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPICR[2]

Host Pipe Clear Register (n = 0)
address_offset : 0x158C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPICR[2] HSTPIPICR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTICR0_ISOENPT

Device Endpoint Clear Register (n = 0)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0

DEVEPTICR0_ISOENPT DEVEPTICR0_ISOENPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC UNDERFIC OVERFIC CRCERRIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

CRCERRIC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTICR0

Device Endpoint Clear Register (n = 0)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTICR0 DEVEPTICR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTICR1

Device Endpoint Clear Register (n = 0)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTICR1 DEVEPTICR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPIFR[2]

Host Pipe Set Register (n = 0)
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIFR[2] HSTPIPIFR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTICR2

Device Endpoint Clear Register (n = 0)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTICR2 DEVEPTICR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTICR3

Device Endpoint Clear Register (n = 0)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTICR3 DEVEPTICR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTICR4

Device Endpoint Clear Register (n = 0)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTICR4 DEVEPTICR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPIMR[2]

Host Pipe Mask Register (n = 0)
address_offset : 0x170C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIMR[2] HSTPIPIMR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIER[2]

Host Pipe Enable Register (n = 0)
address_offset : 0x17CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIER[2] HSTPIPIER[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


DEVIER

Device Global Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVIER DEVIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPES SOFES EORSTES WAKEUPES EORSMES UPRSMES PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

SUSPES : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

SOFES : Start of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

EORSTES : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPES : Wake-Up Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

EORSMES : End of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

UPRSMES : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PEP_0 : Endpoint 0 Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

PEP_1 : Endpoint 1 Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only

PEP_2 : Endpoint 2 Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only

PEP_3 : Endpoint 3 Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only

PEP_4 : Endpoint 4 Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only

DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only

DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only


HSTPIPIDR[2]

Host Pipe Disable Register (n = 0)
address_offset : 0x188C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIDR[2] HSTPIPIDR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


DEVEPTIFR0_ISOENPT

Device Endpoint Set Register (n = 0)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0

DEVEPTIFR0_ISOENPT DEVEPTIFR0_ISOENPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS UNDERFIS OVERFIS CRCERRIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

CRCERRIS : CRC Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTIFR0

Device Endpoint Set Register (n = 0)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIFR0 DEVEPTIFR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPCFG[3]

Host Pipe Configuration Register (n = 0)
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPCFG[3] HSTPIPCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


DEVEPTIFR1

Device Endpoint Set Register (n = 0)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIFR1 DEVEPTIFR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPINRQ[2]

Host Pipe IN Request Register (n = 0)
address_offset : 0x194C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPINRQ[2] HSTPIPINRQ[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


DEVEPTIFR2

Device Endpoint Set Register (n = 0)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIFR2 DEVEPTIFR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTIFR3

Device Endpoint Set Register (n = 0)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIFR3 DEVEPTIFR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTIFR4

Device Endpoint Set Register (n = 0)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIFR4 DEVEPTIFR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPISR[3]

Host Pipe Status Register (n = 0)
address_offset : 0x1A08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPISR[3] HSTPIPISR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPERR[2]

Host Pipe Error Register (n = 0)
address_offset : 0x1A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPERR[2] HSTPIPERR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPICR[3]

Host Pipe Clear Register (n = 0)
address_offset : 0x1AF8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPICR[3] HSTPIPICR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPIFR[3]

Host Pipe Set Register (n = 0)
address_offset : 0x1BE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIFR[3] HSTPIPIFR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPT

Device Endpoint Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVEPT DEVEPT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPEN0 EPEN1 EPEN2 EPEN3 EPEN4 EPEN5 EPEN6 EPEN7 EPEN8 EPRST0 EPRST1 EPRST2 EPRST3 EPRST4 EPRST5 EPRST6 EPRST7 EPRST8

EPEN0 : Endpoint 0 Enable
bits : 0 - 0 (1 bit)
access : read-write

EPEN1 : Endpoint 1 Enable
bits : 1 - 1 (1 bit)
access : read-write

EPEN2 : Endpoint 2 Enable
bits : 2 - 2 (1 bit)
access : read-write

EPEN3 : Endpoint 3 Enable
bits : 3 - 3 (1 bit)
access : read-write

EPEN4 : Endpoint 4 Enable
bits : 4 - 4 (1 bit)
access : read-write

EPEN5 : Endpoint 5 Enable
bits : 5 - 5 (1 bit)
access : read-write

EPEN6 : Endpoint 6 Enable
bits : 6 - 6 (1 bit)
access : read-write

EPEN7 : Endpoint 7 Enable
bits : 7 - 7 (1 bit)
access : read-write

EPEN8 : Endpoint 8 Enable
bits : 8 - 8 (1 bit)
access : read-write

EPRST0 : Endpoint 0 Reset
bits : 16 - 16 (1 bit)
access : read-write

EPRST1 : Endpoint 1 Reset
bits : 17 - 17 (1 bit)
access : read-write

EPRST2 : Endpoint 2 Reset
bits : 18 - 18 (1 bit)
access : read-write

EPRST3 : Endpoint 3 Reset
bits : 19 - 19 (1 bit)
access : read-write

EPRST4 : Endpoint 4 Reset
bits : 20 - 20 (1 bit)
access : read-write

EPRST5 : Endpoint 5 Reset
bits : 21 - 21 (1 bit)
access : read-write

EPRST6 : Endpoint 6 Reset
bits : 22 - 22 (1 bit)
access : read-write

EPRST7 : Endpoint 7 Reset
bits : 23 - 23 (1 bit)
access : read-write

EPRST8 : Endpoint 8 Reset
bits : 24 - 24 (1 bit)
access : read-write


DEVEPTIMR0_ISOENPT

Device Endpoint Mask Register (n = 0)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0

DEVEPTIMR0_ISOENPT DEVEPTIMR0_ISOENPT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE UNDERFE OVERFE CRCERRE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

UNDERFE : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

CRCERRE : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


DEVEPTIMR0

Device Endpoint Mask Register (n = 0)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTIMR0 DEVEPTIMR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


DEVEPTIMR1

Device Endpoint Mask Register (n = 0)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTIMR1 DEVEPTIMR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


DEVEPTIMR2

Device Endpoint Mask Register (n = 0)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTIMR2 DEVEPTIMR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


DEVEPTIMR3

Device Endpoint Mask Register (n = 0)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTIMR3 DEVEPTIMR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


HSTPIPIMR[3]

Host Pipe Mask Register (n = 0)
address_offset : 0x1CD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIMR[3] HSTPIPIMR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


DEVEPTIMR4

Device Endpoint Mask Register (n = 0)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

DEVEPTIMR4 DEVEPTIMR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


HSTPIPIER[3]

Host Pipe Enable Register (n = 0)
address_offset : 0x1DC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIER[3] HSTPIPIER[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPCFG[4]

Host Pipe Configuration Register (n = 0)
address_offset : 0x1E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPCFG[4] HSTPIPCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPIDR[3]

Host Pipe Disable Register (n = 0)
address_offset : 0x1EB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIDR[3] HSTPIPIDR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


DEVEPTIER0_ISOENPT

Device Endpoint Enable Register (n = 0)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0

DEVEPTIER0_ISOENPT DEVEPTIER0_ISOENPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES UNDERFES OVERFES CRCERRES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

UNDERFES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

CRCERRES : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIER0

Device Endpoint Enable Register (n = 0)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIER0 DEVEPTIER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIER1

Device Endpoint Enable Register (n = 0)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIER1 DEVEPTIER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPISR[4]

Host Pipe Status Register (n = 0)
address_offset : 0x1F48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPISR[4] HSTPIPISR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTIER2

Device Endpoint Enable Register (n = 0)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIER2 DEVEPTIER2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPINRQ[3]

Host Pipe IN Request Register (n = 0)
address_offset : 0x1FA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPINRQ[3] HSTPIPINRQ[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


DEVEPTIER3

Device Endpoint Enable Register (n = 0)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIER3 DEVEPTIER3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


DEVFNUM

Device Frame Number Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVFNUM DEVFNUM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FNUM FNCERR

FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-only

FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
access : read-only


DEVEPTCFG[0]

Device Endpoint Configuration Register (n = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVEPTCFG[0] DEVEPTCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


DEVEPTIER4

Device Endpoint Enable Register (n = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIER4 DEVEPTIER4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPICR[4]

Host Pipe Clear Register (n = 0)
address_offset : 0x2068 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPICR[4] HSTPIPICR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPERR[3]

Host Pipe Error Register (n = 0)
address_offset : 0x2098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPERR[3] HSTPIPERR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPIFR[4]

Host Pipe Set Register (n = 0)
address_offset : 0x2188 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIFR[4] HSTPIPIFR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTIDR0_ISOENPT

Device Endpoint Disable Register (n = 0)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0

DEVEPTIDR0_ISOENPT DEVEPTIDR0_ISOENPT write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC UNDERFEC OVERFEC CRCERREC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

UNDERFEC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

CRCERREC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only


DEVEPTIDR0

Device Endpoint Disable Register (n = 0)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIDR0 DEVEPTIDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIDR1

Device Endpoint Disable Register (n = 0)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIDR1 DEVEPTIDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIDR2

Device Endpoint Disable Register (n = 0)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIDR2 DEVEPTIDR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPIMR[4]

Host Pipe Mask Register (n = 0)
address_offset : 0x22A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIMR[4] HSTPIPIMR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


DEVEPTIDR3

Device Endpoint Disable Register (n = 0)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIDR3 DEVEPTIDR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIDR4

Device Endpoint Disable Register (n = 0)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

DEVEPTIDR4 DEVEPTIDR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPIER[4]

Host Pipe Enable Register (n = 0)
address_offset : 0x23C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIER[4] HSTPIPIER[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIDR[4]

Host Pipe Disable Register (n = 0)
address_offset : 0x24E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIDR[4] HSTPIPIDR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


DEVEPTISR[0]

Device Endpoint Status Register (n = 0)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTISR[0] DEVEPTISR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPINRQ[4]

Host Pipe IN Request Register (n = 0)
address_offset : 0x2608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPINRQ[4] HSTPIPINRQ[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


HSTPIPERR[4]

Host Pipe Error Register (n = 0)
address_offset : 0x2728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPERR[4] HSTPIPERR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


DEVEPTICR[0]

Device Endpoint Clear Register (n = 0)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTICR[0] DEVEPTICR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTCFG[1]

Device Endpoint Configuration Register (n = 0)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVEPTCFG[1] DEVEPTCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


DEVDMANXTDSC1

Device DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMANXTDSC1 DEVDMANXTDSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMAADDRESS1

Device DMA Channel Address Register (n = 1)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMAADDRESS1 DEVDMAADDRESS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMACONTROL1

Device DMA Channel Control Register (n = 1)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMACONTROL1 DEVDMACONTROL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DEVDMASTATUS1

Device DMA Channel Status Register (n = 1)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMASTATUS1 DEVDMASTATUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DEVEPTIFR[0]

Device Endpoint Set Register (n = 0)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIFR[0] DEVEPTIFR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVDMANXTDSC2

Device DMA Channel Next Descriptor Address Register (n = 2)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMANXTDSC2 DEVDMANXTDSC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMAADDRESS2

Device DMA Channel Address Register (n = 2)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMAADDRESS2 DEVDMAADDRESS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMACONTROL2

Device DMA Channel Control Register (n = 2)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMACONTROL2 DEVDMACONTROL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DEVDMASTATUS2

Device DMA Channel Status Register (n = 2)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMASTATUS2 DEVDMASTATUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DEVDMANXTDSC3

Device DMA Channel Next Descriptor Address Register (n = 3)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMANXTDSC3 DEVDMANXTDSC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMAADDRESS3

Device DMA Channel Address Register (n = 3)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMAADDRESS3 DEVDMAADDRESS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMACONTROL3

Device DMA Channel Control Register (n = 3)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMACONTROL3 DEVDMACONTROL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DEVDMASTATUS3

Device DMA Channel Status Register (n = 3)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMASTATUS3 DEVDMASTATUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DEVDMANXTDSC4

Device DMA Channel Next Descriptor Address Register (n = 4)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMANXTDSC4 DEVDMANXTDSC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMAADDRESS4

Device DMA Channel Address Register (n = 4)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMAADDRESS4 DEVDMAADDRESS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DEVDMACONTROL4

Device DMA Channel Control Register (n = 4)
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMACONTROL4 DEVDMACONTROL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


DEVDMASTATUS4

Device DMA Channel Status Register (n = 4)
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVDMASTATUS4 DEVDMASTATUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DEVEPTIMR[0]

Device Endpoint Mask Register (n = 0)
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIMR[0] DEVEPTIMR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


DEVEPTISR[1]

Device Endpoint Status Register (n = 0)
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTISR[1] DEVEPTISR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTIER[0]

Device Endpoint Enable Register (n = 0)
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIER[0] DEVEPTIER[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


DEVISR

Device Global Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVISR DEVISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSP SOF EORST WAKEUP EORSM UPRSM PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

SUSP : Suspend Interrupt
bits : 0 - 0 (1 bit)
access : read-only

SOF : Start of Frame Interrupt
bits : 2 - 2 (1 bit)
access : read-only

EORST : End of Reset Interrupt
bits : 3 - 3 (1 bit)
access : read-only

WAKEUP : Wake-Up Interrupt
bits : 4 - 4 (1 bit)
access : read-only

EORSM : End of Resume Interrupt
bits : 5 - 5 (1 bit)
access : read-only

UPRSM : Upstream Resume Interrupt
bits : 6 - 6 (1 bit)
access : read-only

PEP_0 : Endpoint 0 Interrupt
bits : 12 - 12 (1 bit)
access : read-only

PEP_1 : Endpoint 1 Interrupt
bits : 13 - 13 (1 bit)
access : read-only

PEP_2 : Endpoint 2 Interrupt
bits : 14 - 14 (1 bit)
access : read-only

PEP_3 : Endpoint 3 Interrupt
bits : 15 - 15 (1 bit)
access : read-only

PEP_4 : Endpoint 4 Interrupt
bits : 16 - 16 (1 bit)
access : read-only

DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-only

DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
access : read-only

DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
access : read-only

DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
access : read-only


HSTCTRL

Host General Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTCTRL HSTCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOFE RESET RESUME

SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)
access : read-write

RESET : Send USB Reset
bits : 9 - 9 (1 bit)
access : read-write

RESUME : Send USB Resume
bits : 10 - 10 (1 bit)
access : read-write


HSTISR

Host Global Interrupt Status Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTISR HSTISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNI DDISCI RSTI RSMEDI RXRSMI HSOFI HWUPI PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

DCONNI : Device Connection Interrupt
bits : 0 - 0 (1 bit)
access : read-only

DDISCI : Device Disconnection Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RSTI : USB Reset Sent Interrupt
bits : 2 - 2 (1 bit)
access : read-only

RSMEDI : Downstream Resume Sent Interrupt
bits : 3 - 3 (1 bit)
access : read-only

RXRSMI : Upstream Resume Received Interrupt
bits : 4 - 4 (1 bit)
access : read-only

HSOFI : Host Start of Frame Interrupt
bits : 5 - 5 (1 bit)
access : read-only

HWUPI : Host Wake-Up Interrupt
bits : 6 - 6 (1 bit)
access : read-only

PEP_0 : Pipe 0 Interrupt
bits : 8 - 8 (1 bit)
access : read-only

PEP_1 : Pipe 1 Interrupt
bits : 9 - 9 (1 bit)
access : read-only

PEP_2 : Pipe 2 Interrupt
bits : 10 - 10 (1 bit)
access : read-only

PEP_3 : Pipe 3 Interrupt
bits : 11 - 11 (1 bit)
access : read-only

PEP_4 : Pipe 4 Interrupt
bits : 12 - 12 (1 bit)
access : read-only

DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-only

DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
access : read-only

DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
access : read-only

DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
access : read-only


HSTICR

Host Global Interrupt Clear Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTICR HSTICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIC DDISCIC RSTIC RSMEDIC RXRSMIC HSOFIC HWUPIC

DCONNIC : Device Connection Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

DDISCIC : Device Disconnection Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RSTIC : USB Reset Sent Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIC : Downstream Resume Sent Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIC : Upstream Resume Received Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

HSOFIC : Host Start of Frame Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

HWUPIC : Host Wake-Up Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only


DEVEPTCFG[2]

Device Endpoint Configuration Register (n = 0)
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVEPTCFG[2] DEVEPTCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


HSTIFR

Host Global Interrupt Set Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTIFR HSTIFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIS DDISCIS RSTIS RSMEDIS RXRSMIS HSOFIS HWUPIS DMA_1 DMA_2 DMA_3 DMA_4

DCONNIS : Device Connection Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

DDISCIS : Device Disconnection Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RSTIS : USB Reset Sent Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIS : Downstream Resume Sent Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIS : Upstream Resume Received Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

HSOFIS : Host Start of Frame Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

HWUPIS : Host Wake-Up Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

DMA_1 : DMA Channel 1 Interrupt Set
bits : 25 - 25 (1 bit)
access : write-only

DMA_2 : DMA Channel 2 Interrupt Set
bits : 26 - 26 (1 bit)
access : write-only

DMA_3 : DMA Channel 3 Interrupt Set
bits : 27 - 27 (1 bit)
access : write-only

DMA_4 : DMA Channel 4 Interrupt Set
bits : 28 - 28 (1 bit)
access : write-only


HSTIMR

Host Global Interrupt Mask Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTIMR HSTIMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIE DDISCIE RSTIE RSMEDIE RXRSMIE HSOFIE HWUPIE PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

DCONNIE : Device Connection Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

DDISCIE : Device Disconnection Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

RSTIE : USB Reset Sent Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

RSMEDIE : Downstream Resume Sent Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

RXRSMIE : Upstream Resume Received Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

HSOFIE : Host Start of Frame Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

HWUPIE : Host Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

PEP_0 : Pipe 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-only

PEP_1 : Pipe 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-only

PEP_2 : Pipe 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only

PEP_3 : Pipe 3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only

PEP_4 : Pipe 4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-only

DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-only

DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-only

DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-only


HSTIDR

Host Global Interrupt Disable Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTIDR HSTIDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIEC DDISCIEC RSTIEC RSMEDIEC RXRSMIEC HSOFIEC HWUPIEC PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

DCONNIEC : Device Connection Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

DDISCIEC : Device Disconnection Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

RSTIEC : USB Reset Sent Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIEC : Downstream Resume Sent Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIEC : Upstream Resume Received Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

HSOFIEC : Host Start of Frame Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

HWUPIEC : Host Wake-Up Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

PEP_0 : Pipe 0 Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

PEP_1 : Pipe 1 Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only

PEP_2 : Pipe 2 Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only

PEP_3 : Pipe 3 Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only

PEP_4 : Pipe 4 Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only

DMA_1 : DMA Channel 1 Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only

DMA_2 : DMA Channel 2 Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only

DMA_3 : DMA Channel 3 Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only

DMA_4 : DMA Channel 4 Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only


HSTIER

Host Global Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTIER HSTIER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCONNIES DDISCIES RSTIES RSMEDIES RXRSMIES HSOFIES HWUPIES PEP_0 PEP_1 PEP_2 PEP_3 PEP_4 DMA_1 DMA_2 DMA_3 DMA_4

DCONNIES : Device Connection Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

DDISCIES : Device Disconnection Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RSTIES : USB Reset Sent Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

RSMEDIES : Downstream Resume Sent Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

RXRSMIES : Upstream Resume Received Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

HSOFIES : Host Start of Frame Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

HWUPIES : Host Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

PEP_0 : Pipe 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

PEP_1 : Pipe 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only

PEP_2 : Pipe 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only

PEP_3 : Pipe 3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only

PEP_4 : Pipe 4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only

DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only

DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only

DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only


HSTPIP

Host Pipe Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIP HSTPIP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PEN0 PEN1 PEN2 PEN3 PEN4 PEN5 PEN6 PEN7 PEN8 PRST0 PRST1 PRST2 PRST3 PRST4 PRST5 PRST6 PRST7 PRST8

PEN0 : Pipe 0 Enable
bits : 0 - 0 (1 bit)
access : read-write

PEN1 : Pipe 1 Enable
bits : 1 - 1 (1 bit)
access : read-write

PEN2 : Pipe 2 Enable
bits : 2 - 2 (1 bit)
access : read-write

PEN3 : Pipe 3 Enable
bits : 3 - 3 (1 bit)
access : read-write

PEN4 : Pipe 4 Enable
bits : 4 - 4 (1 bit)
access : read-write

PEN5 : Pipe 5 Enable
bits : 5 - 5 (1 bit)
access : read-write

PEN6 : Pipe 6 Enable
bits : 6 - 6 (1 bit)
access : read-write

PEN7 : Pipe 7 Enable
bits : 7 - 7 (1 bit)
access : read-write

PEN8 : Pipe 8 Enable
bits : 8 - 8 (1 bit)
access : read-write

PRST0 : Pipe 0 Reset
bits : 16 - 16 (1 bit)
access : read-write

PRST1 : Pipe 1 Reset
bits : 17 - 17 (1 bit)
access : read-write

PRST2 : Pipe 2 Reset
bits : 18 - 18 (1 bit)
access : read-write

PRST3 : Pipe 3 Reset
bits : 19 - 19 (1 bit)
access : read-write

PRST4 : Pipe 4 Reset
bits : 20 - 20 (1 bit)
access : read-write

PRST5 : Pipe 5 Reset
bits : 21 - 21 (1 bit)
access : read-write

PRST6 : Pipe 6 Reset
bits : 22 - 22 (1 bit)
access : read-write

PRST7 : Pipe 7 Reset
bits : 23 - 23 (1 bit)
access : read-write

PRST8 : Pipe 8 Reset
bits : 24 - 24 (1 bit)
access : read-write


HSTFNUM

Host Frame Number Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTFNUM HSTFNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FNUM FLENHIGH

FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-write

FLENHIGH : Frame Length
bits : 16 - 23 (8 bit)
access : read-write


DEVEPTICR[1]

Device Endpoint Clear Register (n = 0)
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTICR[1] DEVEPTICR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTADDR1

Host Address 1 Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTADDR1 HSTADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTADDRP0 HSTADDRP1 HSTADDRP2 HSTADDRP3

HSTADDRP0 : USB Host Address
bits : 0 - 6 (7 bit)
access : read-write

HSTADDRP1 : USB Host Address
bits : 8 - 14 (7 bit)
access : read-write

HSTADDRP2 : USB Host Address
bits : 16 - 22 (7 bit)
access : read-write

HSTADDRP3 : USB Host Address
bits : 24 - 30 (7 bit)
access : read-write


HSTADDR2

Host Address 2 Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTADDR2 HSTADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTADDRP4 HSTADDRP5 HSTADDRP6 HSTADDRP7

HSTADDRP4 : USB Host Address
bits : 0 - 6 (7 bit)
access : read-write

HSTADDRP5 : USB Host Address
bits : 8 - 14 (7 bit)
access : read-write

HSTADDRP6 : USB Host Address
bits : 16 - 22 (7 bit)
access : read-write

HSTADDRP7 : USB Host Address
bits : 24 - 30 (7 bit)
access : read-write


HSTADDR3

Host Address 3 Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTADDR3 HSTADDR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSTADDRP8 HSTADDRP9

HSTADDRP8 : USB Host Address
bits : 0 - 6 (7 bit)
access : read-write

HSTADDRP9 : USB Host Address
bits : 8 - 14 (7 bit)
access : read-write


DEVEPTIDR[0]

Device Endpoint Disable Register (n = 0)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIDR[0] DEVEPTIDR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIFR[1]

Device Endpoint Set Register (n = 0)
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIFR[1] DEVEPTIFR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTISR[2]

Device Endpoint Status Register (n = 0)
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTISR[2] DEVEPTISR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPCFG0

Host Pipe Configuration Register (n = 0)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPCFG0 HSTPIPCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPCFG1

Host Pipe Configuration Register (n = 0)
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPCFG1 HSTPIPCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPCFG2

Host Pipe Configuration Register (n = 0)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPCFG2 HSTPIPCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPCFG3

Host Pipe Configuration Register (n = 0)
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPCFG3 HSTPIPCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPCFG4

Host Pipe Configuration Register (n = 0)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPCFG4 HSTPIPCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


DEVEPTCFG[3]

Device Endpoint Configuration Register (n = 0)
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVEPTCFG[3] DEVEPTCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


HSTPIPISR0_INTPIPES

Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0

HSTPIPISR0_INTPIPES HSTPIPISR0_INTPIPES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI UNDERFI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPISR0_ISOPIPES

Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0

HSTPIPISR0_ISOPIPES HSTPIPISR0_ISOPIPES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI UNDERFI PERRI NAKEDI OVERFI CRCERRI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

CRCERRI : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPISR0

Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPISR0 HSTPIPISR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPISR1

Host Pipe Status Register (n = 0)
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPISR1 HSTPIPISR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPISR2

Host Pipe Status Register (n = 0)
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPISR2 HSTPIPISR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPISR3

Host Pipe Status Register (n = 0)
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPISR3 HSTPIPISR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPISR4

Host Pipe Status Register (n = 0)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPISR4 HSTPIPISR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTIMR[1]

Device Endpoint Mask Register (n = 0)
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIMR[1] DEVEPTIMR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


HSTPIPICR0_INTPIPES

Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0

HSTPIPICR0_INTPIPES HSTPIPICR0_INTPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC UNDERFIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPICR0_ISOPIPES

Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0

HSTPIPICR0_ISOPIPES HSTPIPICR0_ISOPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC UNDERFIC NAKEDIC OVERFIC CRCERRIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

CRCERRIC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPICR0

Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPICR0 HSTPIPICR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPICR1

Host Pipe Clear Register (n = 0)
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPICR1 HSTPIPICR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPICR2

Host Pipe Clear Register (n = 0)
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPICR2 HSTPIPICR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPICR3

Host Pipe Clear Register (n = 0)
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPICR3 HSTPIPICR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPICR4

Host Pipe Clear Register (n = 0)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPICR4 HSTPIPICR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTICR[2]

Device Endpoint Clear Register (n = 0)
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTICR[2] DEVEPTICR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPIFR0_INTPIPES

Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0

HSTPIPIFR0_INTPIPES HSTPIPIFR0_INTPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS UNDERFIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIFR0_ISOPIPES

Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0

HSTPIPIFR0_ISOPIPES HSTPIPIFR0_ISOPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS UNDERFIS PERRIS NAKEDIS OVERFIS CRCERRIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

CRCERRIS : CRC Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIFR0

Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIFR0 HSTPIPIFR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIFR1

Host Pipe Set Register (n = 0)
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIFR1 HSTPIPIFR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIFR2

Host Pipe Set Register (n = 0)
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIFR2 HSTPIPIFR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIFR3

Host Pipe Set Register (n = 0)
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIFR3 HSTPIPIFR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIFR4

Host Pipe Set Register (n = 0)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIFR4 HSTPIPIFR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIMR0_INTPIPES

Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0

HSTPIPIMR0_INTPIPES HSTPIPIMR0_INTPIPES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE UNDERFIE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

UNDERFIE : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIMR0_ISOPIPES

Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0

HSTPIPIMR0_ISOPIPES HSTPIPIMR0_ISOPIPES read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE UNDERFIE PERRE NAKEDE OVERFIE CRCERRE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

UNDERFIE : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

CRCERRE : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIMR0

Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPIMR0 HSTPIPIMR0 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIMR1

Host Pipe Mask Register (n = 0)
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPIMR1 HSTPIPIMR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIMR2

Host Pipe Mask Register (n = 0)
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPIMR2 HSTPIPIMR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIMR3

Host Pipe Mask Register (n = 0)
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPIMR3 HSTPIPIMR3 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


HSTPIPIMR4

Host Pipe Mask Register (n = 0)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0

HSTPIPIMR4 HSTPIPIMR4 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


DEVEPTIER[1]

Device Endpoint Enable Register (n = 0)
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIER[1] DEVEPTIER[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPIER0_INTPIPES

Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0

HSTPIPIER0_INTPIPES HSTPIPIER0_INTPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES UNDERFIES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIER0_ISOPIPES

Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0

HSTPIPIER0_ISOPIPES HSTPIPIER0_ISOPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES UNDERFIES PERRES NAKEDES OVERFIES CRCERRES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

CRCERRES : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIER0

Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIER0 HSTPIPIER0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIER1

Host Pipe Enable Register (n = 0)
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIER1 HSTPIPIER1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIER2

Host Pipe Enable Register (n = 0)
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIER2 HSTPIPIER2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIER3

Host Pipe Enable Register (n = 0)
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIER3 HSTPIPIER3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


HSTPIPIER4

Host Pipe Enable Register (n = 0)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIER4 HSTPIPIER4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


DEVEPTISR[3]

Device Endpoint Status Register (n = 0)
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTISR[3] DEVEPTISR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTPIPIDR0_INTPIPES

Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0

HSTPIPIDR0_INTPIPES HSTPIPIDR0_INTPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC UNDERFIEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIEC : Underflow Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPIDR0_ISOPIPES

Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0

HSTPIPIDR0_ISOPIPES HSTPIPIDR0_ISOPIPES write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC UNDERFIEC PERREC NAKEDEC OVERFIEC CRCERREC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

UNDERFIEC : Underflow Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

CRCERREC : CRC Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPIDR0

Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIDR0 HSTPIPIDR0 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPIDR1

Host Pipe Disable Register (n = 0)
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIDR1 HSTPIPIDR1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


DEVEPTCFG[4]

Device Endpoint Configuration Register (n = 0)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEVEPTCFG[4] DEVEPTCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC EPBK EPSIZE EPDIR AUTOSW EPTYPE

ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank endpoint

0x1 : 2_BANK

Double-bank endpoint

0x2 : 3_BANK

Triple-bank endpoint

End of enumeration elements list.

EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : OUT

The endpoint direction is OUT.

1 : IN

The endpoint direction is IN (nor for control endpoints).

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write

EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.


HSTPIPIDR2

Host Pipe Disable Register (n = 0)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIDR2 HSTPIPIDR2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPIDR3

Host Pipe Disable Register (n = 0)
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIDR3 HSTPIPIDR3 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPIDR4

Host Pipe Disable Register (n = 0)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0

HSTPIPIDR4 HSTPIPIDR4 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


DEVEPTIFR[2]

Device Endpoint Set Register (n = 0)
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIFR[2] DEVEPTIFR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPINRQ0

Host Pipe IN Request Register (n = 0)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPINRQ0 HSTPIPINRQ0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


HSTPIPINRQ1

Host Pipe IN Request Register (n = 0)
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPINRQ1 HSTPIPINRQ1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


HSTPIPINRQ2

Host Pipe IN Request Register (n = 0)
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPINRQ2 HSTPIPINRQ2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


HSTPIPINRQ3

Host Pipe IN Request Register (n = 0)
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPINRQ3 HSTPIPINRQ3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


HSTPIPINRQ4

Host Pipe IN Request Register (n = 0)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPINRQ4 HSTPIPINRQ4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


DEVEPTIDR[1]

Device Endpoint Disable Register (n = 0)
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIDR[1] DEVEPTIDR[1] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPERR0

Host Pipe Error Register (n = 0)
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPERR0 HSTPIPERR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPERR1

Host Pipe Error Register (n = 0)
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPERR1 HSTPIPERR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPERR2

Host Pipe Error Register (n = 0)
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPERR2 HSTPIPERR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPERR3

Host Pipe Error Register (n = 0)
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPERR3 HSTPIPERR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPERR4

Host Pipe Error Register (n = 0)
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

HSTPIPERR4 HSTPIPERR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


DEVEPTICR[3]

Device Endpoint Clear Register (n = 0)
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTICR[3] DEVEPTICR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTIMR[2]

Device Endpoint Mask Register (n = 0)
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIMR[2] DEVEPTIMR[2] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


HSTDMANXTDSC1

Host DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMANXTDSC1 HSTDMANXTDSC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMAADDRESS1

Host DMA Channel Address Register (n = 1)
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMAADDRESS1 HSTDMAADDRESS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMACONTROL1

Host DMA Channel Control Register (n = 1)
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMACONTROL1 HSTDMACONTROL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


HSTDMASTATUS1

Host DMA Channel Status Register (n = 1)
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMASTATUS1 HSTDMASTATUS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


HSTDMANXTDSC2

Host DMA Channel Next Descriptor Address Register (n = 2)
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMANXTDSC2 HSTDMANXTDSC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMAADDRESS2

Host DMA Channel Address Register (n = 2)
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMAADDRESS2 HSTDMAADDRESS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMACONTROL2

Host DMA Channel Control Register (n = 2)
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMACONTROL2 HSTDMACONTROL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


HSTDMASTATUS2

Host DMA Channel Status Register (n = 2)
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMASTATUS2 HSTDMASTATUS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


HSTDMANXTDSC3

Host DMA Channel Next Descriptor Address Register (n = 3)
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMANXTDSC3 HSTDMANXTDSC3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMAADDRESS3

Host DMA Channel Address Register (n = 3)
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMAADDRESS3 HSTDMAADDRESS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMACONTROL3

Host DMA Channel Control Register (n = 3)
address_offset : 0x738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMACONTROL3 HSTDMACONTROL3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


HSTDMASTATUS3

Host DMA Channel Status Register (n = 3)
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMASTATUS3 HSTDMASTATUS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


HSTDMANXTDSC4

Host DMA Channel Next Descriptor Address Register (n = 4)
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMANXTDSC4 HSTDMANXTDSC4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NXT_DSC_ADD

NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write


HSTDMAADDRESS4

Host DMA Channel Address Register (n = 4)
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMAADDRESS4 HSTDMAADDRESS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUFF_ADD

BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write


DEVEPTISR[4]

Device Endpoint Status Register (n = 0)
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTISR[4] DEVEPTISR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINI RXOUTI RXSTPI NAKOUTI NAKINI OVERFI STALLEDI SHORTPACKET DTSEQ NBUSYBK CURRBK RWALL CTRLDIR CFGOK BYCT

TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only


HSTDMACONTROL4

Host DMA Channel Control Register (n = 4)
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMACONTROL4 HSTDMACONTROL4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB LDNXT_DSC END_TR_EN END_B_EN END_TR_IT END_BUFFIT DESC_LD_IT BURST_LCK BUFF_LENGTH

CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write

LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write

END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write

END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write

END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write

BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write


HSTDMASTATUS4

Host DMA Channel Status Register (n = 4)
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTDMASTATUS4 HSTDMASTATUS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHANN_ENB CHANN_ACT END_TR_ST END_BF_ST DESC_LDST BUFF_COUNT

CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write

CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write

END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write

END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write

DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write

BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write


DEVEPTIER[2]

Device Endpoint Enable Register (n = 0)
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIER[2] DEVEPTIER[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIFR[3]

Device Endpoint Set Register (n = 0)
address_offset : 0x7E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIFR[3] DEVEPTIFR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVICR

Device Global Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVICR DEVICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPC SOFC EORSTC WAKEUPC EORSMC UPRSMC

SUSPC : Suspend Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

SOFC : Start of Frame Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

EORSTC : End of Reset Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPC : Wake-Up Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

EORSMC : End of Resume Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

UPRSMC : Upstream Resume Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only


CTRL

General Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDTE VBUSTE SRPE VBERRE BCERRE ROLEEXE HNPERRE STOE VBUSHWC SRPSEL SRPREQ HNPREQ OTGPADE VBUSPO FRZCLK USBE TIMVALUE TIMPAGE UNLOCK UIDE UIMOD

IDTE : ID Transition Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write

VBUSTE : VBus Transition Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write

SRPE : SRP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write

VBERRE : VBus Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write

BCERRE : B-Connection Error Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write

ROLEEXE : Role Exchange Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write

HNPERRE : HNP Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write

STOE : Suspend Time-Out Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write

VBUSHWC : VBus Hardware Control
bits : 8 - 8 (1 bit)
access : read-write

SRPSEL : SRP Selection
bits : 9 - 9 (1 bit)
access : read-write

SRPREQ : SRP Request
bits : 10 - 10 (1 bit)
access : read-write

HNPREQ : HNP Request
bits : 11 - 11 (1 bit)
access : read-write

OTGPADE : OTG Pad Enable
bits : 12 - 12 (1 bit)
access : read-write

VBUSPO : VBus Polarity Off
bits : 13 - 13 (1 bit)
access : read-write

FRZCLK : Freeze USB Clock
bits : 14 - 14 (1 bit)
access : read-write

USBE : UOTGHS Enable
bits : 15 - 15 (1 bit)
access : read-write

TIMVALUE : Timer Value
bits : 16 - 17 (2 bit)
access : read-write

TIMPAGE : Timer Page
bits : 20 - 21 (2 bit)
access : read-write

UNLOCK : Timer Access Unlock
bits : 22 - 22 (1 bit)
access : read-write

UIDE : UOTGID Pin Enable
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

0 : UIMOD

The USB mode (device/host) is selected from the UIMOD bit.

1 : UOTGID

The USB mode (device/host) is selected from the UOTGID input pin.

End of enumeration elements list.

UIMOD : UOTGHS Mode
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

0 : HOST

The module is in USB host mode.

1 : DEVICE

The module is in USB device mode.

End of enumeration elements list.


SR

General Status Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDTI VBUSTI SRPI VBERRI BCERRI ROLEEXI HNPERRI STOI VBUSRQ ID VBUS SPEED

IDTI : ID Transition Interrupt
bits : 0 - 0 (1 bit)
access : read-only

VBUSTI : VBus Transition Interrupt
bits : 1 - 1 (1 bit)
access : read-only

SRPI : SRP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

VBERRI : VBus Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

BCERRI : B-Connection Error Interrupt
bits : 4 - 4 (1 bit)
access : read-only

ROLEEXI : Role Exchange Interrupt
bits : 5 - 5 (1 bit)
access : read-only

HNPERRI : HNP Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only

STOI : Suspend Time-Out Interrupt
bits : 7 - 7 (1 bit)
access : read-only

VBUSRQ : VBus Request
bits : 9 - 9 (1 bit)
access : read-only

ID : UOTGID Pin State
bits : 10 - 10 (1 bit)
access : read-only

VBUS : VBus Level
bits : 11 - 11 (1 bit)
access : read-only

SPEED : Speed Status
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : FULL_SPEED

Full-Speed mode

0x2 : LOW_SPEED

Low-Speed mode

End of enumeration elements list.


SCR

General Status Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDTIC VBUSTIC SRPIC VBERRIC BCERRIC ROLEEXIC HNPERRIC STOIC VBUSRQC

IDTIC : ID Transition Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

VBUSTIC : VBus Transition Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

SRPIC : SRP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

VBERRIC : VBus Error Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

BCERRIC : B-Connection Error Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

ROLEEXIC : Role Exchange Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

HNPERRIC : HNP Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

STOIC : Suspend Time-Out Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

VBUSRQC : VBus Request Clear
bits : 9 - 9 (1 bit)
access : write-only


SFR

General Status Set Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SFR SFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDTIS VBUSTIS SRPIS VBERRIS BCERRIS ROLEEXIS HNPERRIS STOIS VBUSRQS

IDTIS : ID Transition Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

VBUSTIS : VBus Transition Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

SRPIS : SRP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

VBERRIS : VBus Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

BCERRIS : B-Connection Error Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

ROLEEXIS : Role Exchange Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

HNPERRIS : HNP Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

STOIS : Suspend Time-Out Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

VBUSRQS : VBus Request Set
bits : 9 - 9 (1 bit)
access : write-only


FSM

General Finite State Machine Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

FSM FSM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRDSTATE

DRDSTATE : Dual Role Device State
bits : 0 - 3 (4 bit)
access : read-only

Enumeration:

0x0 : A_IDLESTATE

This is the start state for A-devices (when the ID pin is 0)

0x1 : A_WAIT_VRISE

In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).

0x2 : A_WAIT_BCON

In this state, the A-device waits for the B-device to signal a connection.

0x3 : A_HOST

In this state, the A-device that operates in Host mode is operational.

0x4 : A_SUSPEND

The A-device operating as a host is in the suspend mode.

0x5 : A_PERIPHERAL

The A-device operates as a peripheral.

0x6 : A_WAIT_VFALL

In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).

0x7 : A_VBUS_ERR

In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.

0x8 : A_WAIT_DISCHARGE

In this state, the A-device waits for the data USB line to discharge (100 us).

0x9 : B_IDLE

This is the start state for B-device (when the ID pin is 1).

0xA : B_PERIPHERAL

In this state, the B-device acts as the peripheral.

0xB : B_WAIT_BEGIN_HNP

In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.

0xC : B_WAIT_DISCHARGE

In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host.

0xD : B_WAIT_ACON

In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.

0xE : B_HOST

In this state, the B-device acts as the Host.

0xF : B_SRP_INIT

In this state, the B-device attempts to start a session using the SRP protocol.

End of enumeration elements list.


DEVEPTICR[4]

Device Endpoint Clear Register (n = 0)
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTICR[4] DEVEPTICR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIC RXOUTIC RXSTPIC NAKOUTIC NAKINIC OVERFIC STALLEDIC SHORTPACKETC

TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


DEVEPTIDR[2]

Device Endpoint Disable Register (n = 0)
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIDR[2] DEVEPTIDR[2] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


DEVEPTIMR[3]

Device Endpoint Mask Register (n = 0)
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIMR[3] DEVEPTIMR[3] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


DEVEPTIFR[4]

Device Endpoint Set Register (n = 0)
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIFR[4] DEVEPTIFR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINIS RXOUTIS RXSTPIS NAKOUTIS NAKINIS OVERFIS STALLEDIS SHORTPACKETS NBUSYBKS

TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only


DEVEPTIER[3]

Device Endpoint Enable Register (n = 0)
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIER[3] DEVEPTIER[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPCFG[0]

Host Pipe Configuration Register (n = 0)
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPCFG[0] HSTPIPCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPISR[0]

Host Pipe Status Register (n = 0)
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPISR[0] HSTPIPISR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only


DEVEPTIMR[4]

Device Endpoint Mask Register (n = 0)
address_offset : 0xAA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIMR[4] DEVEPTIMR[4] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINE RXOUTE RXSTPE NAKOUTE NAKINE OVERFE STALLEDE SHORTPACKETE NBUSYBKE KILLBK FIFOCON EPDISHDMA RSTDT STALLRQ

TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only

KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only

STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only


DEVEPTIDR[3]

Device Endpoint Disable Register (n = 0)
address_offset : 0xAB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIDR[3] DEVEPTIDR[3] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPICR[0]

Host Pipe Clear Register (n = 0)
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPICR[0] HSTPIPICR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIC TXOUTIC TXSTPIC NAKEDIC OVERFIC RXSTALLDIC SHORTPACKETIC

RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only


HSTPIPIFR[0]

Host Pipe Set Register (n = 0)
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIFR[0] HSTPIPIFR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINIS TXOUTIS TXSTPIS PERRIS NAKEDIS OVERFIS RXSTALLDIS SHORTPACKETIS NBUSYBKS

RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only

TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only


HSTPIPIMR[0]

Host Pipe Mask Register (n = 0)
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIMR[0] HSTPIPIMR[0] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINE TXOUTE TXSTPE PERRE NAKEDE OVERFIE RXSTALLDE SHORTPACKETIE NBUSYBKE FIFOCON PDISHDMA PFREEZE RSTDT

RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only

TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only

TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only

PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only

NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only

OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only

NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only

FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only

PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only

PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only

RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only


DEVEPTIER[4]

Device Endpoint Enable Register (n = 0)
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIER[4] DEVEPTIER[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINES RXOUTES RXSTPES NAKOUTES NAKINES OVERFES STALLEDES SHORTPACKETES NBUSYBKES KILLBKS FIFOCONS EPDISHDMAS RSTDTS STALLRQS

TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only

KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only

FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only

STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPIER[0]

Host Pipe Enable Register (n = 0)
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIER[0] HSTPIPIER[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINES TXOUTES TXSTPES PERRES NAKEDES OVERFIES RXSTALLDES SHORTPACKETIES NBUSYBKES PDISHDMAS PFREEZES RSTDTS

RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only

PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only

RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only


DEVIFR

Device Global Interrupt Set Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVIFR DEVIFR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUSPS SOFS EORSTS WAKEUPS EORSMS UPRSMS DMA_1 DMA_2 DMA_3 DMA_4

SUSPS : Suspend Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only

SOFS : Start of Frame Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only

EORSTS : End of Reset Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only

WAKEUPS : Wake-Up Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only

EORSMS : End of Resume Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only

UPRSMS : Upstream Resume Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only

DMA_1 : DMA Channel 1 Interrupt Set
bits : 25 - 25 (1 bit)
access : write-only

DMA_2 : DMA Channel 2 Interrupt Set
bits : 26 - 26 (1 bit)
access : write-only

DMA_3 : DMA Channel 3 Interrupt Set
bits : 27 - 27 (1 bit)
access : write-only

DMA_4 : DMA Channel 4 Interrupt Set
bits : 28 - 28 (1 bit)
access : write-only


HSTPIPIDR[0]

Host Pipe Disable Register (n = 0)
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPIDR[0] HSTPIPIDR[0] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINEC TXOUTEC TXSTPEC PERREC NAKEDEC OVERFIEC RXSTALLDEC SHORTPACKETIEC NBUSYBKEC FIFOCONC PDISHDMAC PFREEZEC

RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only

PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only

PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only


HSTPIPINRQ[0]

Host Pipe IN Request Register (n = 0)
address_offset : 0xCA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPINRQ[0] HSTPIPINRQ[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INRQ INMODE

INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write

INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write


DEVEPTIDR[4]

Device Endpoint Disable Register (n = 0)
address_offset : 0xCE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

DEVEPTIDR[4] DEVEPTIDR[4] write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXINEC RXOUTEC RXSTPEC NAKOUTEC NAKINEC OVERFEC STALLEDEC SHORTPACKETEC NBUSYBKEC FIFOCONC EPDISHDMAC STALLRQC

TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only

RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only

RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only

NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only

NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only

OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only

STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only

SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only

NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only

FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only

EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only

STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only


HSTPIPERR[0]

Host Pipe Error Register (n = 0)
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPERR[0] HSTPIPERR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATATGL DATAPID PID TIMEOUT CRC16 COUNTER

DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write

DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write

PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write

TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write

CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write

COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write


HSTPIPCFG[1]

Host Pipe Configuration Register (n = 0)
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSTPIPCFG[1] HSTPIPCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALLOC PBK PSIZE PTOKEN AUTOSW PTYPE PEPNUM INTFRQ

ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write

PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write

Enumeration:

0x0 : 1_BANK

Single-bank pipe

0x1 : 2_BANK

Double-bank pipe

0x2 : 3_BANK

Triple-bank pipe

End of enumeration elements list.

PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

0x0 : 8_BYTE

8 bytes

0x1 : 16_BYTE

16 bytes

0x2 : 32_BYTE

32 bytes

0x3 : 64_BYTE

64 bytes

0x4 : 128_BYTE

128 bytes

0x5 : 256_BYTE

256 bytes

0x6 : 512_BYTE

512 bytes

0x7 : 1024_BYTE

1024 bytes

End of enumeration elements list.

PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

0x0 : SETUP

SETUP

0x1 : IN

IN

0x2 : OUT

OUT

End of enumeration elements list.

AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write

PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0x0 : CTRL

Control

0x1 : ISO

Isochronous

0x2 : BLK

Bulk

0x3 : INTRPT

Interrupt

End of enumeration elements list.

PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write

INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write


HSTPIPISR[1]

Host Pipe Status Register (n = 0)
address_offset : 0xF94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

HSTPIPISR[1] HSTPIPISR[1] read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXINI TXOUTI TXSTPI PERRI NAKEDI OVERFI RXSTALLDI SHORTPACKETI DTSEQ NBUSYBK CURRBK RWALL CFGOK PBYCT

RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only

TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only

TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only

PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only

NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only

OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only

RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only

SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only

DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only

Enumeration:

0 : DATA0

Data0 toggle sequence

1 : DATA1

Data1 toggle sequence

End of enumeration elements list.

NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only

Enumeration:

0x0 : 0_BUSY

0 busy bank (all banks free)

0x1 : 1_BUSY

1 busy bank

0x2 : 2_BUSY

2 busy banks

0x3 : 3_BUSY

3 busy banks

End of enumeration elements list.

CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only

Enumeration:

0x0 : BANK0

Current bank is bank0

0x1 : BANK1

Current bank is bank1

0x2 : BANK2

Current bank is bank2

End of enumeration elements list.

RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only

CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only

PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only



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