\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Device General Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UADD : USB Address
bits : 0 - 6 (7 bit)
access : read-write
ADDEN : Address Enable
bits : 7 - 7 (1 bit)
access : read-write
DETACH : Detach
bits : 8 - 8 (1 bit)
access : read-write
RMWKUP : Remote Wake-Up
bits : 9 - 9 (1 bit)
access : read-write
LS : Low-Speed Mode Force
bits : 12 - 12 (1 bit)
access : read-write
Device Global Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSPE : Suspend Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
SOFE : Start of Frame Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
EORSTE : End of Reset Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
WAKEUPE : Wake-Up Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
EORSME : End of Resume Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
UPRSME : Upstream Resume Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
PEP_0 : Endpoint 0 Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
PEP_1 : Endpoint 1 Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
PEP_2 : Endpoint 2 Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
PEP_3 : Endpoint 3 Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
PEP_4 : Endpoint 4 Interrupt Mask
bits : 16 - 16 (1 bit)
access : read-only
DMA_1 : DMA Channel 1 Interrupt Mask
bits : 25 - 25 (1 bit)
access : read-only
DMA_2 : DMA Channel 2 Interrupt Mask
bits : 26 - 26 (1 bit)
access : read-only
DMA_3 : DMA Channel 3 Interrupt Mask
bits : 27 - 27 (1 bit)
access : read-only
DMA_4 : DMA Channel 4 Interrupt Mask
bits : 28 - 28 (1 bit)
access : read-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Host Pipe Clear Register (n = 0)
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0)
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Host Pipe Set Register (n = 0)
address_offset : 0x10B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Device Endpoint Configuration Register (n = 0)
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Host Pipe Mask Register (n = 0)
address_offset : 0x1144 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Enable Register (n = 0)
address_offset : 0x11D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x1264 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe IN Request Register (n = 0)
address_offset : 0x12F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Device Endpoint Status Register (n = 0)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
CRCERRI : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Status Register (n = 0)
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Status Register (n = 0)
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Status Register (n = 0)
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Error Register (n = 0)
address_offset : 0x1384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Device Endpoint Status Register (n = 0)
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Global Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPEC : Suspend Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
SOFEC : Start of Frame Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
EORSTEC : End of Reset Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPEC : Wake-Up Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
EORSMEC : End of Resume Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
UPRSMEC : Upstream Resume Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
PEP_0 : Endpoint 0 Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
PEP_1 : Endpoint 1 Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
PEP_2 : Endpoint 2 Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
PEP_3 : Endpoint 3 Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
PEP_4 : Endpoint 4 Interrupt Disable
bits : 16 - 16 (1 bit)
access : write-only
DMA_1 : DMA Channel 1 Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
DMA_2 : DMA Channel 2 Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
DMA_3 : DMA Channel 3 Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
DMA_4 : DMA Channel 4 Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
Device Endpoint Status Register (n = 0)
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Configuration Register (n = 0)
address_offset : 0x140C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Status Register (n = 0)
address_offset : 0x14CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Clear Register (n = 0)
address_offset : 0x158C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Mask Register (n = 0)
address_offset : 0x170C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Enable Register (n = 0)
address_offset : 0x17CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Device Global Interrupt Enable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPES : Suspend Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
SOFES : Start of Frame Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
EORSTES : End of Reset Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPES : Wake-Up Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
EORSMES : End of Resume Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
UPRSMES : Upstream Resume Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
PEP_0 : Endpoint 0 Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
PEP_1 : Endpoint 1 Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
PEP_2 : Endpoint 2 Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
PEP_3 : Endpoint 3 Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
PEP_4 : Endpoint 4 Interrupt Enable
bits : 16 - 16 (1 bit)
access : write-only
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x188C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIS : CRC Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Configuration Register (n = 0)
address_offset : 0x1918 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Device Endpoint Set Register (n = 0)
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe IN Request Register (n = 0)
address_offset : 0x194C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Device Endpoint Set Register (n = 0)
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Status Register (n = 0)
address_offset : 0x1A08 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Error Register (n = 0)
address_offset : 0x1A0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Clear Register (n = 0)
address_offset : 0x1AF8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x1BE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEN0 : Endpoint 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
EPEN1 : Endpoint 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
EPEN2 : Endpoint 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
EPEN3 : Endpoint 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
EPEN4 : Endpoint 4 Enable
bits : 4 - 4 (1 bit)
access : read-write
EPEN5 : Endpoint 5 Enable
bits : 5 - 5 (1 bit)
access : read-write
EPEN6 : Endpoint 6 Enable
bits : 6 - 6 (1 bit)
access : read-write
EPEN7 : Endpoint 7 Enable
bits : 7 - 7 (1 bit)
access : read-write
EPEN8 : Endpoint 8 Enable
bits : 8 - 8 (1 bit)
access : read-write
EPRST0 : Endpoint 0 Reset
bits : 16 - 16 (1 bit)
access : read-write
EPRST1 : Endpoint 1 Reset
bits : 17 - 17 (1 bit)
access : read-write
EPRST2 : Endpoint 2 Reset
bits : 18 - 18 (1 bit)
access : read-write
EPRST3 : Endpoint 3 Reset
bits : 19 - 19 (1 bit)
access : read-write
EPRST4 : Endpoint 4 Reset
bits : 20 - 20 (1 bit)
access : read-write
EPRST5 : Endpoint 5 Reset
bits : 21 - 21 (1 bit)
access : read-write
EPRST6 : Endpoint 6 Reset
bits : 22 - 22 (1 bit)
access : read-write
EPRST7 : Endpoint 7 Reset
bits : 23 - 23 (1 bit)
access : read-write
EPRST8 : Endpoint 8 Reset
bits : 24 - 24 (1 bit)
access : read-write
Device Endpoint Mask Register (n = 0)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFE : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
CRCERRE : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x1CD8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Host Pipe Enable Register (n = 0)
address_offset : 0x1DC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Configuration Register (n = 0)
address_offset : 0x1E28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Disable Register (n = 0)
address_offset : 0x1EB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
CRCERRES : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Status Register (n = 0)
address_offset : 0x1F48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe IN Request Register (n = 0)
address_offset : 0x1FA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Device Endpoint Enable Register (n = 0)
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Device Frame Number Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-only
FNCERR : Frame Number CRC Error
bits : 15 - 15 (1 bit)
access : read-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Device Endpoint Enable Register (n = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x2068 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Error Register (n = 0)
address_offset : 0x2098 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Set Register (n = 0)
address_offset : 0x2188 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOENPT
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFEC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
CRCERREC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Mask Register (n = 0)
address_offset : 0x22A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x23C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x24E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Device Endpoint Status Register (n = 0)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe IN Request Register (n = 0)
address_offset : 0x2608 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Host Pipe Error Register (n = 0)
address_offset : 0x2728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Device Endpoint Clear Register (n = 0)
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Device DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 1)
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 1)
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 1)
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device Endpoint Set Register (n = 0)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device DMA Channel Next Descriptor Address Register (n = 2)
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 2)
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 2)
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 2)
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 3)
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 3)
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 3)
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 3)
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Next Descriptor Address Register (n = 4)
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Address Register (n = 4)
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device DMA Channel Control Register (n = 4)
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable Control
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Device DMA Channel Status Register (n = 4)
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device Endpoint Mask Register (n = 0)
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Device Endpoint Status Register (n = 0)
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Device Global Interrupt Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
SUSP : Suspend Interrupt
bits : 0 - 0 (1 bit)
access : read-only
SOF : Start of Frame Interrupt
bits : 2 - 2 (1 bit)
access : read-only
EORST : End of Reset Interrupt
bits : 3 - 3 (1 bit)
access : read-only
WAKEUP : Wake-Up Interrupt
bits : 4 - 4 (1 bit)
access : read-only
EORSM : End of Resume Interrupt
bits : 5 - 5 (1 bit)
access : read-only
UPRSM : Upstream Resume Interrupt
bits : 6 - 6 (1 bit)
access : read-only
PEP_0 : Endpoint 0 Interrupt
bits : 12 - 12 (1 bit)
access : read-only
PEP_1 : Endpoint 1 Interrupt
bits : 13 - 13 (1 bit)
access : read-only
PEP_2 : Endpoint 2 Interrupt
bits : 14 - 14 (1 bit)
access : read-only
PEP_3 : Endpoint 3 Interrupt
bits : 15 - 15 (1 bit)
access : read-only
PEP_4 : Endpoint 4 Interrupt
bits : 16 - 16 (1 bit)
access : read-only
DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-only
DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
access : read-only
DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
access : read-only
DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
access : read-only
Host General Control Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SOFE : Start of Frame Generation Enable
bits : 8 - 8 (1 bit)
access : read-write
RESET : Send USB Reset
bits : 9 - 9 (1 bit)
access : read-write
RESUME : Send USB Resume
bits : 10 - 10 (1 bit)
access : read-write
Host Global Interrupt Status Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCONNI : Device Connection Interrupt
bits : 0 - 0 (1 bit)
access : read-only
DDISCI : Device Disconnection Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RSTI : USB Reset Sent Interrupt
bits : 2 - 2 (1 bit)
access : read-only
RSMEDI : Downstream Resume Sent Interrupt
bits : 3 - 3 (1 bit)
access : read-only
RXRSMI : Upstream Resume Received Interrupt
bits : 4 - 4 (1 bit)
access : read-only
HSOFI : Host Start of Frame Interrupt
bits : 5 - 5 (1 bit)
access : read-only
HWUPI : Host Wake-Up Interrupt
bits : 6 - 6 (1 bit)
access : read-only
PEP_0 : Pipe 0 Interrupt
bits : 8 - 8 (1 bit)
access : read-only
PEP_1 : Pipe 1 Interrupt
bits : 9 - 9 (1 bit)
access : read-only
PEP_2 : Pipe 2 Interrupt
bits : 10 - 10 (1 bit)
access : read-only
PEP_3 : Pipe 3 Interrupt
bits : 11 - 11 (1 bit)
access : read-only
PEP_4 : Pipe 4 Interrupt
bits : 12 - 12 (1 bit)
access : read-only
DMA_1 : DMA Channel 1 Interrupt
bits : 25 - 25 (1 bit)
access : read-only
DMA_2 : DMA Channel 2 Interrupt
bits : 26 - 26 (1 bit)
access : read-only
DMA_3 : DMA Channel 3 Interrupt
bits : 27 - 27 (1 bit)
access : read-only
DMA_4 : DMA Channel 4 Interrupt
bits : 28 - 28 (1 bit)
access : read-only
Host Global Interrupt Clear Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIC : Device Connection Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
DDISCIC : Device Disconnection Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RSTIC : USB Reset Sent Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIC : Downstream Resume Sent Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIC : Upstream Resume Received Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
HSOFIC : Host Start of Frame Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
HWUPIC : Host Wake-Up Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Host Global Interrupt Set Register
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIS : Device Connection Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
DDISCIS : Device Disconnection Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RSTIS : USB Reset Sent Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIS : Downstream Resume Sent Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIS : Upstream Resume Received Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
HSOFIS : Host Start of Frame Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
HWUPIS : Host Wake-Up Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
DMA_1 : DMA Channel 1 Interrupt Set
bits : 25 - 25 (1 bit)
access : write-only
DMA_2 : DMA Channel 2 Interrupt Set
bits : 26 - 26 (1 bit)
access : write-only
DMA_3 : DMA Channel 3 Interrupt Set
bits : 27 - 27 (1 bit)
access : write-only
DMA_4 : DMA Channel 4 Interrupt Set
bits : 28 - 28 (1 bit)
access : write-only
Host Global Interrupt Mask Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIE : Device Connection Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
DDISCIE : Device Disconnection Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
RSTIE : USB Reset Sent Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
RSMEDIE : Downstream Resume Sent Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
RXRSMIE : Upstream Resume Received Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
HSOFIE : Host Start of Frame Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
HWUPIE : Host Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
PEP_0 : Pipe 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-only
PEP_1 : Pipe 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-only
PEP_2 : Pipe 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-only
PEP_3 : Pipe 3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-only
PEP_4 : Pipe 4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : read-only
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : read-only
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : read-only
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : read-only
Host Global Interrupt Disable Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIEC : Device Connection Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
DDISCIEC : Device Disconnection Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
RSTIEC : USB Reset Sent Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIEC : Downstream Resume Sent Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIEC : Upstream Resume Received Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
HSOFIEC : Host Start of Frame Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
HWUPIEC : Host Wake-Up Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
PEP_0 : Pipe 0 Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
PEP_1 : Pipe 1 Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
PEP_2 : Pipe 2 Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
PEP_3 : Pipe 3 Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
PEP_4 : Pipe 4 Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
DMA_1 : DMA Channel 1 Interrupt Disable
bits : 25 - 25 (1 bit)
access : write-only
DMA_2 : DMA Channel 2 Interrupt Disable
bits : 26 - 26 (1 bit)
access : write-only
DMA_3 : DMA Channel 3 Interrupt Disable
bits : 27 - 27 (1 bit)
access : write-only
DMA_4 : DMA Channel 4 Interrupt Disable
bits : 28 - 28 (1 bit)
access : write-only
Host Global Interrupt Enable Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DCONNIES : Device Connection Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
DDISCIES : Device Disconnection Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RSTIES : USB Reset Sent Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
RSMEDIES : Downstream Resume Sent Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
RXRSMIES : Upstream Resume Received Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
HSOFIES : Host Start of Frame Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
HWUPIES : Host Wake-Up Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
PEP_0 : Pipe 0 Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
PEP_1 : Pipe 1 Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
PEP_2 : Pipe 2 Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
PEP_3 : Pipe 3 Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
PEP_4 : Pipe 4 Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
DMA_1 : DMA Channel 1 Interrupt Enable
bits : 25 - 25 (1 bit)
access : write-only
DMA_2 : DMA Channel 2 Interrupt Enable
bits : 26 - 26 (1 bit)
access : write-only
DMA_3 : DMA Channel 3 Interrupt Enable
bits : 27 - 27 (1 bit)
access : write-only
DMA_4 : DMA Channel 4 Interrupt Enable
bits : 28 - 28 (1 bit)
access : write-only
Host Pipe Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PEN0 : Pipe 0 Enable
bits : 0 - 0 (1 bit)
access : read-write
PEN1 : Pipe 1 Enable
bits : 1 - 1 (1 bit)
access : read-write
PEN2 : Pipe 2 Enable
bits : 2 - 2 (1 bit)
access : read-write
PEN3 : Pipe 3 Enable
bits : 3 - 3 (1 bit)
access : read-write
PEN4 : Pipe 4 Enable
bits : 4 - 4 (1 bit)
access : read-write
PEN5 : Pipe 5 Enable
bits : 5 - 5 (1 bit)
access : read-write
PEN6 : Pipe 6 Enable
bits : 6 - 6 (1 bit)
access : read-write
PEN7 : Pipe 7 Enable
bits : 7 - 7 (1 bit)
access : read-write
PEN8 : Pipe 8 Enable
bits : 8 - 8 (1 bit)
access : read-write
PRST0 : Pipe 0 Reset
bits : 16 - 16 (1 bit)
access : read-write
PRST1 : Pipe 1 Reset
bits : 17 - 17 (1 bit)
access : read-write
PRST2 : Pipe 2 Reset
bits : 18 - 18 (1 bit)
access : read-write
PRST3 : Pipe 3 Reset
bits : 19 - 19 (1 bit)
access : read-write
PRST4 : Pipe 4 Reset
bits : 20 - 20 (1 bit)
access : read-write
PRST5 : Pipe 5 Reset
bits : 21 - 21 (1 bit)
access : read-write
PRST6 : Pipe 6 Reset
bits : 22 - 22 (1 bit)
access : read-write
PRST7 : Pipe 7 Reset
bits : 23 - 23 (1 bit)
access : read-write
PRST8 : Pipe 8 Reset
bits : 24 - 24 (1 bit)
access : read-write
Host Frame Number Register
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FNUM : Frame Number
bits : 3 - 13 (11 bit)
access : read-write
FLENHIGH : Frame Length
bits : 16 - 23 (8 bit)
access : read-write
Device Endpoint Clear Register (n = 0)
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Address 1 Register
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTADDRP0 : USB Host Address
bits : 0 - 6 (7 bit)
access : read-write
HSTADDRP1 : USB Host Address
bits : 8 - 14 (7 bit)
access : read-write
HSTADDRP2 : USB Host Address
bits : 16 - 22 (7 bit)
access : read-write
HSTADDRP3 : USB Host Address
bits : 24 - 30 (7 bit)
access : read-write
Host Address 2 Register
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTADDRP4 : USB Host Address
bits : 0 - 6 (7 bit)
access : read-write
HSTADDRP5 : USB Host Address
bits : 8 - 14 (7 bit)
access : read-write
HSTADDRP6 : USB Host Address
bits : 16 - 22 (7 bit)
access : read-write
HSTADDRP7 : USB Host Address
bits : 24 - 30 (7 bit)
access : read-write
Host Address 3 Register
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HSTADDRP8 : USB Host Address
bits : 0 - 6 (7 bit)
access : read-write
HSTADDRP9 : USB Host Address
bits : 8 - 14 (7 bit)
access : read-write
Device Endpoint Disable Register (n = 0)
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Status Register (n = 0)
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Configuration Register (n = 0)
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Configuration Register (n = 0)
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Configuration Register (n = 0)
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Configuration Register (n = 0)
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Configuration Register (n = 0)
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Device Endpoint Configuration Register (n = 0)
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
UNDERFI : Underflow Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
CRCERRI : CRC Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Status Register (n = 0)
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x544 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIC : Underflow Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIC : CRC Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x560 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x564 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x568 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x56C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0x570 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Clear Register (n = 0)
address_offset : 0x58C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIS : Underflow Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
CRCERRIS : CRC Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x594 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x598 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x59C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0x5A0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
UNDERFIE : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
UNDERFIE : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
CRCERRE : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5C4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5C8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5CC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Host Pipe Mask Register (n = 0)
address_offset : 0x5D0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x5D4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIES : Underflow Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
CRCERRES : CRC Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5F0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5F4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x5FC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Device Endpoint Status Register (n = 0)
address_offset : 0x608 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : INTPIPES
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIEC : Underflow Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
alternate_register : ISOPIPES
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
UNDERFIEC : Underflow Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
CRCERREC : CRC Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x620 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x624 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Device Endpoint Configuration Register (n = 0)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Endpoint Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
EPBK : Endpoint Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank endpoint
0x1 : 2_BANK
Double-bank endpoint
0x2 : 3_BANK
Triple-bank endpoint
End of enumeration elements list.
EPSIZE : Endpoint Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
EPDIR : Endpoint Direction
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : OUT
The endpoint direction is OUT.
1 : IN
The endpoint direction is IN (nor for control endpoints).
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 9 - 9 (1 bit)
access : read-write
EPTYPE : Endpoint Type
bits : 11 - 12 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
Host Pipe Disable Register (n = 0)
address_offset : 0x628 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x62C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0x630 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x64C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe IN Request Register (n = 0)
address_offset : 0x650 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Host Pipe IN Request Register (n = 0)
address_offset : 0x654 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Host Pipe IN Request Register (n = 0)
address_offset : 0x658 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Host Pipe IN Request Register (n = 0)
address_offset : 0x65C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Host Pipe IN Request Register (n = 0)
address_offset : 0x660 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Device Endpoint Disable Register (n = 0)
address_offset : 0x664 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Error Register (n = 0)
address_offset : 0x680 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Error Register (n = 0)
address_offset : 0x684 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Error Register (n = 0)
address_offset : 0x688 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Error Register (n = 0)
address_offset : 0x68C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Error Register (n = 0)
address_offset : 0x690 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Device Endpoint Clear Register (n = 0)
address_offset : 0x6F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Host DMA Channel Next Descriptor Address Register (n = 1)
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 1)
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 1)
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 1)
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 2)
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 2)
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 2)
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 2)
address_offset : 0x72C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 3)
address_offset : 0x730 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 3)
address_offset : 0x734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Control Register (n = 3)
address_offset : 0x738 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 3)
address_offset : 0x73C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Next Descriptor Address Register (n = 4)
address_offset : 0x740 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NXT_DSC_ADD : Next Descriptor Address
bits : 0 - 31 (32 bit)
access : read-write
Host DMA Channel Address Register (n = 4)
address_offset : 0x744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUFF_ADD : Buffer Address
bits : 0 - 31 (32 bit)
access : read-write
Device Endpoint Status Register (n = 0)
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINI : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTI : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPI : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTI : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINI : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDI : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKET : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CTRLDIR : Control Direction
bits : 17 - 17 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
BYCT : Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Host DMA Channel Control Register (n = 4)
address_offset : 0x748 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Command
bits : 0 - 0 (1 bit)
access : read-write
LDNXT_DSC : Load Next Channel Transfer Descriptor Enable Command
bits : 1 - 1 (1 bit)
access : read-write
END_TR_EN : End of Transfer Enable (Control)
bits : 2 - 2 (1 bit)
access : read-write
END_B_EN : End of Buffer Enable Control
bits : 3 - 3 (1 bit)
access : read-write
END_TR_IT : End of Transfer Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
END_BUFFIT : End of Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
DESC_LD_IT : Descriptor Loaded Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
BURST_LCK : Burst Lock Enable
bits : 7 - 7 (1 bit)
access : read-write
BUFF_LENGTH : Buffer Byte Length (Write-only)
bits : 16 - 31 (16 bit)
access : read-write
Host DMA Channel Status Register (n = 4)
address_offset : 0x74C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHANN_ENB : Channel Enable Status
bits : 0 - 0 (1 bit)
access : read-write
CHANN_ACT : Channel Active Status
bits : 1 - 1 (1 bit)
access : read-write
END_TR_ST : End of Channel Transfer Status
bits : 4 - 4 (1 bit)
access : read-write
END_BF_ST : End of Channel Buffer Status
bits : 5 - 5 (1 bit)
access : read-write
DESC_LDST : Descriptor Loaded Status
bits : 6 - 6 (1 bit)
access : read-write
BUFF_COUNT : Buffer Byte Count
bits : 16 - 31 (16 bit)
access : read-write
Device Endpoint Enable Register (n = 0)
address_offset : 0x7CC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Set Register (n = 0)
address_offset : 0x7E8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Global Interrupt Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPC : Suspend Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
SOFC : Start of Frame Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
EORSTC : End of Reset Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPC : Wake-Up Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
EORSMC : End of Resume Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
UPRSMC : Upstream Resume Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
General Control Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDTE : ID Transition Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-write
VBUSTE : VBus Transition Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-write
SRPE : SRP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-write
VBERRE : VBus Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-write
BCERRE : B-Connection Error Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-write
ROLEEXE : Role Exchange Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-write
HNPERRE : HNP Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-write
STOE : Suspend Time-Out Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-write
VBUSHWC : VBus Hardware Control
bits : 8 - 8 (1 bit)
access : read-write
SRPSEL : SRP Selection
bits : 9 - 9 (1 bit)
access : read-write
SRPREQ : SRP Request
bits : 10 - 10 (1 bit)
access : read-write
HNPREQ : HNP Request
bits : 11 - 11 (1 bit)
access : read-write
OTGPADE : OTG Pad Enable
bits : 12 - 12 (1 bit)
access : read-write
VBUSPO : VBus Polarity Off
bits : 13 - 13 (1 bit)
access : read-write
FRZCLK : Freeze USB Clock
bits : 14 - 14 (1 bit)
access : read-write
USBE : UOTGHS Enable
bits : 15 - 15 (1 bit)
access : read-write
TIMVALUE : Timer Value
bits : 16 - 17 (2 bit)
access : read-write
TIMPAGE : Timer Page
bits : 20 - 21 (2 bit)
access : read-write
UNLOCK : Timer Access Unlock
bits : 22 - 22 (1 bit)
access : read-write
UIDE : UOTGID Pin Enable
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : UIMOD
The USB mode (device/host) is selected from the UIMOD bit.
1 : UOTGID
The USB mode (device/host) is selected from the UOTGID input pin.
End of enumeration elements list.
UIMOD : UOTGHS Mode
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : HOST
The module is in USB host mode.
1 : DEVICE
The module is in USB device mode.
End of enumeration elements list.
General Status Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDTI : ID Transition Interrupt
bits : 0 - 0 (1 bit)
access : read-only
VBUSTI : VBus Transition Interrupt
bits : 1 - 1 (1 bit)
access : read-only
SRPI : SRP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
VBERRI : VBus Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
BCERRI : B-Connection Error Interrupt
bits : 4 - 4 (1 bit)
access : read-only
ROLEEXI : Role Exchange Interrupt
bits : 5 - 5 (1 bit)
access : read-only
HNPERRI : HNP Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
STOI : Suspend Time-Out Interrupt
bits : 7 - 7 (1 bit)
access : read-only
VBUSRQ : VBus Request
bits : 9 - 9 (1 bit)
access : read-only
ID : UOTGID Pin State
bits : 10 - 10 (1 bit)
access : read-only
VBUS : VBus Level
bits : 11 - 11 (1 bit)
access : read-only
SPEED : Speed Status
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : FULL_SPEED
Full-Speed mode
0x2 : LOW_SPEED
Low-Speed mode
End of enumeration elements list.
General Status Clear Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDTIC : ID Transition Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
VBUSTIC : VBus Transition Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
SRPIC : SRP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
VBERRIC : VBus Error Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
BCERRIC : B-Connection Error Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
ROLEEXIC : Role Exchange Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
HNPERRIC : HNP Error Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
STOIC : Suspend Time-Out Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
VBUSRQC : VBus Request Clear
bits : 9 - 9 (1 bit)
access : write-only
General Status Set Register
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDTIS : ID Transition Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
VBUSTIS : VBus Transition Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
SRPIS : SRP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
VBERRIS : VBus Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
BCERRIS : B-Connection Error Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
ROLEEXIS : Role Exchange Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
HNPERRIS : HNP Error Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
STOIS : Suspend Time-Out Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
VBUSRQS : VBus Request Set
bits : 9 - 9 (1 bit)
access : write-only
General Finite State Machine Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DRDSTATE : Dual Role Device State
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0x0 : A_IDLESTATE
This is the start state for A-devices (when the ID pin is 0)
0x1 : A_WAIT_VRISE
In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V).
0x2 : A_WAIT_BCON
In this state, the A-device waits for the B-device to signal a connection.
0x3 : A_HOST
In this state, the A-device that operates in Host mode is operational.
0x4 : A_SUSPEND
The A-device operating as a host is in the suspend mode.
0x5 : A_PERIPHERAL
The A-device operates as a peripheral.
0x6 : A_WAIT_VFALL
In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V).
0x7 : A_VBUS_ERR
In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state.
0x8 : A_WAIT_DISCHARGE
In this state, the A-device waits for the data USB line to discharge (100 us).
0x9 : B_IDLE
This is the start state for B-device (when the ID pin is 1).
0xA : B_PERIPHERAL
In this state, the B-device acts as the peripheral.
0xB : B_WAIT_BEGIN_HNP
In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested.
0xC : B_WAIT_DISCHARGE
In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host.
0xD : B_WAIT_ACON
In this state, the B-device waits for the A-device to signal a connect before becoming B-Host.
0xE : B_HOST
In this state, the B-device acts as the Host.
0xF : B_SRP_INIT
In this state, the B-device attempts to start a session using the SRP protocol.
End of enumeration elements list.
Device Endpoint Clear Register (n = 0)
address_offset : 0x868 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIC : Transmitted IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINIC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Device Endpoint Disable Register (n = 0)
address_offset : 0x88C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Device Endpoint Mask Register (n = 0)
address_offset : 0x8D8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Device Endpoint Set Register (n = 0)
address_offset : 0x988 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINIS : Transmitted IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
RXOUTIS : Received OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
RXSTPIS : Received SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTIS : NAKed OUT Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKINIS : NAKed IN Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
STALLEDIS : STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Interrupt Set
bits : 12 - 12 (1 bit)
access : write-only
Device Endpoint Enable Register (n = 0)
address_offset : 0x9C8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Configuration Register (n = 0)
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Status Register (n = 0)
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
Device Endpoint Mask Register (n = 0)
address_offset : 0xAA8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXINE : Transmitted IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
RXOUTE : Received OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
RXSTPE : Received SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
NAKOUTE : NAKed OUT Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKINE : NAKed IN Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFE : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
STALLEDE : STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETE : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt
bits : 12 - 12 (1 bit)
access : read-only
KILLBK : Kill IN Bank
bits : 13 - 13 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
EPDISHDMA : Endpoint Interrupts Disable HDMA Request
bits : 16 - 16 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
STALLRQ : STALL Request
bits : 19 - 19 (1 bit)
access : read-only
Device Endpoint Disable Register (n = 0)
address_offset : 0xAB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Clear Register (n = 0)
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIC : Received IN Data Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIC : Transmitted OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIC : Transmitted SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKEDIC : NAKed Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFIC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIC : Received STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIC : Short Packet Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
Host Pipe Set Register (n = 0)
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINIS : Received IN Data Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
TXOUTIS : Transmitted OUT Data Interrupt Set
bits : 1 - 1 (1 bit)
access : write-only
TXSTPIS : Transmitted SETUP Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
PERRIS : Pipe Error Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
NAKEDIS : NAKed Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
OVERFIS : Overflow Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDIS : Received STALLed Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIS : Short Packet Interrupt Set
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKS : Number of Busy Banks Set
bits : 12 - 12 (1 bit)
access : write-only
Host Pipe Mask Register (n = 0)
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINE : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : read-only
TXOUTE : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : read-only
TXSTPE : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : read-only
PERRE : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : read-only
NAKEDE : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : read-only
OVERFIE : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDE : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETIE : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : read-only
NBUSYBKE : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-only
FIFOCON : FIFO Control
bits : 14 - 14 (1 bit)
access : read-only
PDISHDMA : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : read-only
PFREEZE : Pipe Freeze
bits : 17 - 17 (1 bit)
access : read-only
RSTDT : Reset Data Toggle
bits : 18 - 18 (1 bit)
access : read-only
Device Endpoint Enable Register (n = 0)
address_offset : 0xBC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINES : Transmitted IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXOUTES : Received OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
RXSTPES : Received SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTES : NAKed OUT Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKINES : NAKed IN Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
STALLEDES : STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
KILLBKS : Kill IN Bank
bits : 13 - 13 (1 bit)
access : write-only
FIFOCONS : FIFO Control
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAS : Endpoint Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
STALLRQS : STALL Request Enable
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Enable Register (n = 0)
address_offset : 0xBE0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINES : Received IN Data Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTES : Transmitted OUT Data Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPES : Transmitted SETUP Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
PERRES : Pipe Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDES : NAKed Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIES : Overflow Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDES : Received STALLed Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIES : Short Packet Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKES : Number of Busy Banks Enable
bits : 12 - 12 (1 bit)
access : write-only
PDISHDMAS : Pipe Interrupts Disable HDMA Request Enable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZES : Pipe Freeze Enable
bits : 17 - 17 (1 bit)
access : write-only
RSTDTS : Reset Data Toggle Enable
bits : 18 - 18 (1 bit)
access : write-only
Device Global Interrupt Set Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SUSPS : Suspend Interrupt Set
bits : 0 - 0 (1 bit)
access : write-only
SOFS : Start of Frame Interrupt Set
bits : 2 - 2 (1 bit)
access : write-only
EORSTS : End of Reset Interrupt Set
bits : 3 - 3 (1 bit)
access : write-only
WAKEUPS : Wake-Up Interrupt Set
bits : 4 - 4 (1 bit)
access : write-only
EORSMS : End of Resume Interrupt Set
bits : 5 - 5 (1 bit)
access : write-only
UPRSMS : Upstream Resume Interrupt Set
bits : 6 - 6 (1 bit)
access : write-only
DMA_1 : DMA Channel 1 Interrupt Set
bits : 25 - 25 (1 bit)
access : write-only
DMA_2 : DMA Channel 2 Interrupt Set
bits : 26 - 26 (1 bit)
access : write-only
DMA_3 : DMA Channel 3 Interrupt Set
bits : 27 - 27 (1 bit)
access : write-only
DMA_4 : DMA Channel 4 Interrupt Set
bits : 28 - 28 (1 bit)
access : write-only
Host Pipe Disable Register (n = 0)
address_offset : 0xC40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXINEC : Received IN Data Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
TXOUTEC : Transmitted OUT Data Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXSTPEC : Transmitted SETUP Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
PERREC : Pipe Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
NAKEDEC : NAKed Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
OVERFIEC : Overflow Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
RXSTALLDEC : Received STALLed Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETIEC : Short Packet Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Disable
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Disable
bits : 14 - 14 (1 bit)
access : write-only
PDISHDMAC : Pipe Interrupts Disable HDMA Request Disable
bits : 16 - 16 (1 bit)
access : write-only
PFREEZEC : Pipe Freeze Disable
bits : 17 - 17 (1 bit)
access : write-only
Host Pipe IN Request Register (n = 0)
address_offset : 0xCA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INRQ : IN Request Number before Freeze
bits : 0 - 7 (8 bit)
access : read-write
INMODE : IN Request Mode
bits : 8 - 8 (1 bit)
access : read-write
Device Endpoint Disable Register (n = 0)
address_offset : 0xCE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXINEC : Transmitted IN Interrupt Clear
bits : 0 - 0 (1 bit)
access : write-only
RXOUTEC : Received OUT Data Interrupt Clear
bits : 1 - 1 (1 bit)
access : write-only
RXSTPEC : Received SETUP Interrupt Clear
bits : 2 - 2 (1 bit)
access : write-only
NAKOUTEC : NAKed OUT Interrupt Clear
bits : 3 - 3 (1 bit)
access : write-only
NAKINEC : NAKed IN Interrupt Clear
bits : 4 - 4 (1 bit)
access : write-only
OVERFEC : Overflow Interrupt Clear
bits : 5 - 5 (1 bit)
access : write-only
STALLEDEC : STALLed Interrupt Clear
bits : 6 - 6 (1 bit)
access : write-only
SHORTPACKETEC : Shortpacket Interrupt Clear
bits : 7 - 7 (1 bit)
access : write-only
NBUSYBKEC : Number of Busy Banks Interrupt Clear
bits : 12 - 12 (1 bit)
access : write-only
FIFOCONC : FIFO Control Clear
bits : 14 - 14 (1 bit)
access : write-only
EPDISHDMAC : Endpoint Interrupts Disable HDMA Request Clear
bits : 16 - 16 (1 bit)
access : write-only
STALLRQC : STALL Request Clear
bits : 19 - 19 (1 bit)
access : write-only
Host Pipe Error Register (n = 0)
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATATGL : Data Toggle Error
bits : 0 - 0 (1 bit)
access : read-write
DATAPID : Data PID Error
bits : 1 - 1 (1 bit)
access : read-write
PID : PID Error
bits : 2 - 2 (1 bit)
access : read-write
TIMEOUT : Time-Out Error
bits : 3 - 3 (1 bit)
access : read-write
CRC16 : CRC16 Error
bits : 4 - 4 (1 bit)
access : read-write
COUNTER : Error Counter
bits : 5 - 6 (2 bit)
access : read-write
Host Pipe Configuration Register (n = 0)
address_offset : 0xF04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALLOC : Pipe Memory Allocate
bits : 1 - 1 (1 bit)
access : read-write
PBK : Pipe Banks
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : 1_BANK
Single-bank pipe
0x1 : 2_BANK
Double-bank pipe
0x2 : 3_BANK
Triple-bank pipe
End of enumeration elements list.
PSIZE : Pipe Size
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0x0 : 8_BYTE
8 bytes
0x1 : 16_BYTE
16 bytes
0x2 : 32_BYTE
32 bytes
0x3 : 64_BYTE
64 bytes
0x4 : 128_BYTE
128 bytes
0x5 : 256_BYTE
256 bytes
0x6 : 512_BYTE
512 bytes
0x7 : 1024_BYTE
1024 bytes
End of enumeration elements list.
PTOKEN : Pipe Token
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : SETUP
SETUP
0x1 : IN
IN
0x2 : OUT
OUT
End of enumeration elements list.
AUTOSW : Automatic Switch
bits : 10 - 10 (1 bit)
access : read-write
PTYPE : Pipe Type
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0x0 : CTRL
Control
0x1 : ISO
Isochronous
0x2 : BLK
Bulk
0x3 : INTRPT
Interrupt
End of enumeration elements list.
PEPNUM : Pipe Endpoint Number
bits : 16 - 19 (4 bit)
access : read-write
INTFRQ : Pipe Interrupt Request Frequency
bits : 24 - 31 (8 bit)
access : read-write
Host Pipe Status Register (n = 0)
address_offset : 0xF94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXINI : Received IN Data Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXOUTI : Transmitted OUT Data Interrupt
bits : 1 - 1 (1 bit)
access : read-only
TXSTPI : Transmitted SETUP Interrupt
bits : 2 - 2 (1 bit)
access : read-only
PERRI : Pipe Error Interrupt
bits : 3 - 3 (1 bit)
access : read-only
NAKEDI : NAKed Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVERFI : Overflow Interrupt
bits : 5 - 5 (1 bit)
access : read-only
RXSTALLDI : Received STALLed Interrupt
bits : 6 - 6 (1 bit)
access : read-only
SHORTPACKETI : Short Packet Interrupt
bits : 7 - 7 (1 bit)
access : read-only
DTSEQ : Data Toggle Sequence
bits : 8 - 9 (2 bit)
access : read-only
Enumeration:
0 : DATA0
Data0 toggle sequence
1 : DATA1
Data1 toggle sequence
End of enumeration elements list.
NBUSYBK : Number of Busy Banks
bits : 12 - 13 (2 bit)
access : read-only
Enumeration:
0x0 : 0_BUSY
0 busy bank (all banks free)
0x1 : 1_BUSY
1 busy bank
0x2 : 2_BUSY
2 busy banks
0x3 : 3_BUSY
3 busy banks
End of enumeration elements list.
CURRBK : Current Bank
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0x0 : BANK0
Current bank is bank0
0x1 : BANK1
Current bank is bank1
0x2 : BANK2
Current bank is bank2
End of enumeration elements list.
RWALL : Read-write Allowed
bits : 16 - 16 (1 bit)
access : read-only
CFGOK : Configuration OK Status
bits : 18 - 18 (1 bit)
access : read-only
PBYCT : Pipe Byte Count
bits : 20 - 30 (11 bit)
access : read-only
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