\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
System I/O Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSIO0 : PB0 or TDI Assignment
bits : 0 - 0 (1 bit)
access : read-write
SYSIO1 : PB1 or TDO/TRACESWO Assignment
bits : 1 - 1 (1 bit)
access : read-write
SYSIO2 : PB2 or TMS/SWDIO Assignment
bits : 2 - 2 (1 bit)
access : read-write
SYSIO3 : PB3 or TCK/SWCLK Assignment
bits : 3 - 3 (1 bit)
access : read-write
SYSIO9 : PC9 or ERASE Assignment
bits : 9 - 9 (1 bit)
access : read-write
SYSIO10 : PD0 or DDM Assignment
bits : 10 - 10 (1 bit)
access : read-write
SYSIO11 : PD1 or DDP Assignment
bits : 11 - 11 (1 bit)
access : read-write
SMC Nand Flash Chip Select Configuration Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMC_NFCS0 : SMC NAND Flash Chip Select 0 Assignment
bits : 0 - 0 (1 bit)
access : read-write
SMC_NFCS1 : SMC NAND Flash Chip Select 1 Assignment
bits : 1 - 1 (1 bit)
access : read-write
SMC_NFCS2 : SMC NAND Flash Chip Select 2 Assignment
bits : 2 - 2 (1 bit)
access : read-write
SMC_NFCS3 : SMC NAND Flash Chip Select 3 Assignment
bits : 3 - 3 (1 bit)
access : read-write
SMC_SEL : SMC Selection for EBI pins
bits : 31 - 31 (1 bit)
access : read-write
Core Debug Configuration Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CROSS_TRG1 :
bits : 1 - 1 (1 bit)
access : read-write
CROSS_TRG0 :
bits : 2 - 2 (1 bit)
access : read-write
Master Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Write Protection Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x4D4154 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only
Slave Configuration Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Slave Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Master Configuration Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 6
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 7
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Priority Register A for Slave 8
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write
M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write
M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write
M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write
M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write
M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write
M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write
M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write
Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write
DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write
FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.