\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Send a START Condition
bits : 0 - 0 (1 bit)
access : write-only
STOP : Send a STOP Condition
bits : 1 - 1 (1 bit)
access : write-only
MSEN : TWI Master Mode Enabled
bits : 2 - 2 (1 bit)
access : write-only
MSDIS : TWI Master Mode Disabled
bits : 3 - 3 (1 bit)
access : write-only
SVEN : TWI Slave Mode Enabled
bits : 4 - 4 (1 bit)
access : write-only
SVDIS : TWI Slave Mode Disabled
bits : 5 - 5 (1 bit)
access : write-only
QUICK : SMBUS Quick Command
bits : 6 - 6 (1 bit)
access : write-only
SWRST : Software Reset
bits : 7 - 7 (1 bit)
access : write-only
Clock Waveform Generator Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLDIV : Clock Low Divider
bits : 0 - 7 (8 bit)
access : read-write
CHDIV : Clock High Divider
bits : 8 - 15 (8 bit)
access : read-write
CKDIV : Clock Divider
bits : 16 - 18 (3 bit)
access : read-write
Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed (automatically set / reset)
bits : 0 - 0 (1 bit)
access : read-only
RXRDY : Receive Holding Register Ready (automatically set / reset)
bits : 1 - 1 (1 bit)
access : read-only
TXRDY : Transmit Holding Register Ready (automatically set / reset)
bits : 2 - 2 (1 bit)
access : read-only
SVREAD : Slave Read (automatically set / reset)
bits : 3 - 3 (1 bit)
access : read-only
SVACC : Slave Access (automatically set / reset)
bits : 4 - 4 (1 bit)
access : read-only
GACC : General Call Access (clear on read)
bits : 5 - 5 (1 bit)
access : read-only
OVRE : Overrun Error (clear on read)
bits : 6 - 6 (1 bit)
access : read-only
NACK : Not Acknowledged (clear on read)
bits : 8 - 8 (1 bit)
access : read-only
ARBLST : Arbitration Lost (clear on read)
bits : 9 - 9 (1 bit)
access : read-only
SCLWS : Clock Wait State (automatically set / reset)
bits : 10 - 10 (1 bit)
access : read-only
EOSACC : End Of Slave Access (clear on read)
bits : 11 - 11 (1 bit)
access : read-only
ENDRX : End of RX buffer
bits : 12 - 12 (1 bit)
access : read-only
ENDTX : End of TX buffer
bits : 13 - 13 (1 bit)
access : read-only
RXBUFF : RX Buffer Full
bits : 14 - 14 (1 bit)
access : read-only
TXBUFE : TX Buffer Empty
bits : 15 - 15 (1 bit)
access : read-only
Interrupt Enable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
RXRDY : Receive Holding Register Ready Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
TXRDY : Transmit Holding Register Ready Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
SVACC : Slave Access Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
GACC : General Call Access Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only
NACK : Not Acknowledge Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
ARBLST : Arbitration Lost Interrupt Enable
bits : 9 - 9 (1 bit)
access : write-only
SCL_WS : Clock Wait State Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only
EOSACC : End Of Slave Access Interrupt Enable
bits : 11 - 11 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Enable
bits : 12 - 12 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Enable
bits : 13 - 13 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Enable
bits : 14 - 14 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 15 - 15 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
RXRDY : Receive Holding Register Ready Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
TXRDY : Transmit Holding Register Ready Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
SVACC : Slave Access Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
GACC : General Call Access Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only
OVRE : Overrun Error Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only
NACK : Not Acknowledge Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
ARBLST : Arbitration Lost Interrupt Disable
bits : 9 - 9 (1 bit)
access : write-only
SCL_WS : Clock Wait State Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only
EOSACC : End Of Slave Access Interrupt Disable
bits : 11 - 11 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Disable
bits : 12 - 12 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Disable
bits : 13 - 13 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Disable
bits : 14 - 14 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 15 - 15 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXCOMP : Transmission Completed Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
RXRDY : Receive Holding Register Ready Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
TXRDY : Transmit Holding Register Ready Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
SVACC : Slave Access Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
GACC : General Call Access Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only
OVRE : Overrun Error Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only
NACK : Not Acknowledge Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
ARBLST : Arbitration Lost Interrupt Mask
bits : 9 - 9 (1 bit)
access : read-only
SCL_WS : Clock Wait State Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only
EOSACC : End Of Slave Access Interrupt Mask
bits : 11 - 11 (1 bit)
access : read-only
ENDRX : End of Receive Buffer Interrupt Mask
bits : 12 - 12 (1 bit)
access : read-only
ENDTX : End of Transmit Buffer Interrupt Mask
bits : 13 - 13 (1 bit)
access : read-only
RXBUFF : Receive Buffer Full Interrupt Mask
bits : 14 - 14 (1 bit)
access : read-only
TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 15 - 15 (1 bit)
access : read-only
Receive Holding Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXDATA : Master or Slave Receive Holding Data
bits : 0 - 7 (8 bit)
access : read-only
Transmit Holding Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXDATA : Master or Slave Transmit Holding Data
bits : 0 - 7 (8 bit)
access : write-only
Master Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IADRSZ : Internal Device Address Size
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
No internal device address
0x1 : 1_BYTE
One-byte internal device address
0x2 : 2_BYTE
Two-byte internal device address
0x3 : 3_BYTE
Three-byte internal device address
End of enumeration elements list.
MREAD : Master Read Direction
bits : 12 - 12 (1 bit)
access : read-write
DADR : Device Address
bits : 16 - 22 (7 bit)
access : read-write
Slave Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SADR : Slave Address
bits : 16 - 22 (7 bit)
access : read-write
Internal Address Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IADR : Internal Address
bits : 0 - 23 (24 bit)
access : read-write
Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x545749 : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0
End of enumeration elements list.
Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 31 (24 bit)
access : read-only
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