\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
SLCDC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
LCDEN : Enable the LCDC
bits : 0 - 0 (1 bit)
access : write-only
LCDDIS : Disable LCDC
bits : 1 - 1 (1 bit)
access : write-only
SWRST : Software Reset
bits : 3 - 3 (1 bit)
access : write-only
SLCDC Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENA : Enable Status (Automatically Set/Reset)
bits : 0 - 0 (1 bit)
access : read-only
SLCDC Interrupt Enable Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ENDFRAME : End of Frame Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
DIS : Disable Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
SLCDC LSB Memory Register (com = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIXEL : LSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC MSB Memory Register (com = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPIXEL : MSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC LSB Memory Register (com = 1)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIXEL : LSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC MSB Memory Register (com = 1)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPIXEL : MSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC LSB Memory Register (com = 2)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIXEL : LSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC MSB Memory Register (com = 2)
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPIXEL : MSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC LSB Memory Register (com = 3)
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIXEL : LSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC MSB Memory Register (com = 3)
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPIXEL : MSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC LSB Memory Register (com = 4)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIXEL : LSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC MSB Memory Register (com = 4)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPIXEL : MSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC LSB Memory Register (com = 5)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPIXEL : LSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC MSB Memory Register (com = 5)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPIXEL : MSB Pixels pattern associated to COMx terminal
bits : 0 - 31 (32 bit)
access : read-write
SLCDC Interrupt Disable Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ENDFRAME : End of Frame Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
DIS : Disable Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
SLCDC Interrupt Mask Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
ENDFRAME : End of Frame Interrupt Mask
bits : 0 - 0 (1 bit)
access : write-only
DIS : Disable Interrupt Mask
bits : 2 - 2 (1 bit)
access : write-only
SLCDC Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ENDFRAME : End of Frame Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
DIS : Disable Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
SLCDC Segment Map Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD0 : LCD Segment Mapped on SEGx I/O pin
bits : 0 - 0 (1 bit)
access : read-write
LCD1 : LCD Segment Mapped on SEGx I/O pin
bits : 1 - 1 (1 bit)
access : read-write
LCD2 : LCD Segment Mapped on SEGx I/O pin
bits : 2 - 2 (1 bit)
access : read-write
LCD3 : LCD Segment Mapped on SEGx I/O pin
bits : 3 - 3 (1 bit)
access : read-write
LCD4 : LCD Segment Mapped on SEGx I/O pin
bits : 4 - 4 (1 bit)
access : read-write
LCD5 : LCD Segment Mapped on SEGx I/O pin
bits : 5 - 5 (1 bit)
access : read-write
LCD6 : LCD Segment Mapped on SEGx I/O pin
bits : 6 - 6 (1 bit)
access : read-write
LCD7 : LCD Segment Mapped on SEGx I/O pin
bits : 7 - 7 (1 bit)
access : read-write
LCD8 : LCD Segment Mapped on SEGx I/O pin
bits : 8 - 8 (1 bit)
access : read-write
LCD9 : LCD Segment Mapped on SEGx I/O pin
bits : 9 - 9 (1 bit)
access : read-write
LCD10 : LCD Segment Mapped on SEGx I/O pin
bits : 10 - 10 (1 bit)
access : read-write
LCD11 : LCD Segment Mapped on SEGx I/O pin
bits : 11 - 11 (1 bit)
access : read-write
LCD12 : LCD Segment Mapped on SEGx I/O pin
bits : 12 - 12 (1 bit)
access : read-write
LCD13 : LCD Segment Mapped on SEGx I/O pin
bits : 13 - 13 (1 bit)
access : read-write
LCD14 : LCD Segment Mapped on SEGx I/O pin
bits : 14 - 14 (1 bit)
access : read-write
LCD15 : LCD Segment Mapped on SEGx I/O pin
bits : 15 - 15 (1 bit)
access : read-write
LCD16 : LCD Segment Mapped on SEGx I/O pin
bits : 16 - 16 (1 bit)
access : read-write
LCD17 : LCD Segment Mapped on SEGx I/O pin
bits : 17 - 17 (1 bit)
access : read-write
LCD18 : LCD Segment Mapped on SEGx I/O pin
bits : 18 - 18 (1 bit)
access : read-write
LCD19 : LCD Segment Mapped on SEGx I/O pin
bits : 19 - 19 (1 bit)
access : read-write
LCD20 : LCD Segment Mapped on SEGx I/O pin
bits : 20 - 20 (1 bit)
access : read-write
LCD21 : LCD Segment Mapped on SEGx I/O pin
bits : 21 - 21 (1 bit)
access : read-write
LCD22 : LCD Segment Mapped on SEGx I/O pin
bits : 22 - 22 (1 bit)
access : read-write
LCD23 : LCD Segment Mapped on SEGx I/O pin
bits : 23 - 23 (1 bit)
access : read-write
LCD24 : LCD Segment Mapped on SEGx I/O pin
bits : 24 - 24 (1 bit)
access : read-write
LCD25 : LCD Segment Mapped on SEGx I/O pin
bits : 25 - 25 (1 bit)
access : read-write
LCD26 : LCD Segment Mapped on SEGx I/O pin
bits : 26 - 26 (1 bit)
access : read-write
LCD27 : LCD Segment Mapped on SEGx I/O pin
bits : 27 - 27 (1 bit)
access : read-write
LCD28 : LCD Segment Mapped on SEGx I/O pin
bits : 28 - 28 (1 bit)
access : read-write
LCD29 : LCD Segment Mapped on SEGx I/O pin
bits : 29 - 29 (1 bit)
access : read-write
LCD30 : LCD Segment Mapped on SEGx I/O pin
bits : 30 - 30 (1 bit)
access : read-write
LCD31 : LCD Segment Mapped on SEGx I/O pin
bits : 31 - 31 (1 bit)
access : read-write
SLCDC Segment Map Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD32 : LCD Segment Mapped on SEGx I/O pin
bits : 0 - 0 (1 bit)
access : read-write
LCD33 : LCD Segment Mapped on SEGx I/O pin
bits : 1 - 1 (1 bit)
access : read-write
LCD34 : LCD Segment Mapped on SEGx I/O pin
bits : 2 - 2 (1 bit)
access : read-write
LCD35 : LCD Segment Mapped on SEGx I/O pin
bits : 3 - 3 (1 bit)
access : read-write
LCD36 : LCD Segment Mapped on SEGx I/O pin
bits : 4 - 4 (1 bit)
access : read-write
LCD37 : LCD Segment Mapped on SEGx I/O pin
bits : 5 - 5 (1 bit)
access : read-write
LCD38 : LCD Segment Mapped on SEGx I/O pin
bits : 6 - 6 (1 bit)
access : read-write
LCD39 : LCD Segment Mapped on SEGx I/O pin
bits : 7 - 7 (1 bit)
access : read-write
LCD40 : LCD Segment Mapped on SEGx I/O pin
bits : 8 - 8 (1 bit)
access : read-write
LCD41 : LCD Segment Mapped on SEGx I/O pin
bits : 9 - 9 (1 bit)
access : read-write
LCD42 : LCD Segment Mapped on SEGx I/O pin
bits : 10 - 10 (1 bit)
access : read-write
LCD43 : LCD Segment Mapped on SEGx I/O pin
bits : 11 - 11 (1 bit)
access : read-write
LCD44 : LCD Segment Mapped on SEGx I/O pin
bits : 12 - 12 (1 bit)
access : read-write
LCD45 : LCD Segment Mapped on SEGx I/O pin
bits : 13 - 13 (1 bit)
access : read-write
LCD46 : LCD Segment Mapped on SEGx I/O pin
bits : 14 - 14 (1 bit)
access : read-write
LCD47 : LCD Segment Mapped on SEGx I/O pin
bits : 15 - 15 (1 bit)
access : read-write
LCD48 : LCD Segment Mapped on SEGx I/O pin
bits : 16 - 16 (1 bit)
access : read-write
LCD49 : LCD Segment Mapped on SEGx I/O pin
bits : 17 - 17 (1 bit)
access : read-write
SLCDC Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COMSEL : Selection of the Number of Commons
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : COM_0
COM0 is driven by SLCDC, COM1:5 are driven by digital function
0x1 : COM_0TO1
COM0:1 are driven by SLCDC, COM2:5 are driven by digital function
0x2 : COM_0TO2
COM0:2 are driven by SLCDC, COM3:5 are driven by digital function
0x3 : COM_0TO3
COM0:3 are driven by SLCDC, COM4:5 are driven by digital function
0x4 : COM_0TO4
COM0:4 are driven by SLCDC, COM5 is driven by digital function
0x5 : COM_0TO5
COM0:5 are driven by SLCDC, No COM pin driven by digital function
End of enumeration elements list.
SEGSEL : Selection of the Number of Segments
bits : 8 - 13 (6 bit)
access : read-write
BUFTIME : Buffer On-Time
bits : 16 - 19 (4 bit)
access : read-write
Enumeration:
0x0 : OFF
Nominal drive time is 0% of SCLK period
0x1 : X2_SCLK_PERIOD
Nominal drive time is 2 periods of SCLK clock
0x2 : X4_SCLK_PERIOD
Nominal drive time is 4 periods of SCLK clock
0x3 : X8_SCLK_PERIOD
Nominal drive time is 8 periods of SCLK clock
0x4 : X16_SCLK_PERIOD
Nominal drive time is 16 periods of SCLK clock
0x5 : X32_SCLK_PERIOD
Nominal drive time is 32 periods of SCLK clock
0x6 : X64_SCLK_PERIOD
Nominal drive time is 64 periods of SCLK clock
0x7 : X128_SCLK_PERIOD
Nominal drive time is 128 periods of SCLK clock
0x8 : PERCENT_50
Nominal drive time is 50% of SCLK period
0x9 : PERCENT_100
Nominal drive time is 100% of SCLK period
End of enumeration elements list.
BIAS : LCD Display Configuration
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : STATIC
static
0x1 : BIAS_1_2
bias 1/2
0x2 : BIAS_1_3
bias 1/3
End of enumeration elements list.
LPMODE : Low Power Mode (Taken into account from the next begin of frame.)
bits : 24 - 24 (1 bit)
access : read-write
SLCDC Frame Rate Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESC : Clock Prescaler
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : SCLK_DIV8
slow clock is divided by 8
0x1 : SCLK_DIV16
slow clock is divided by 16
0x2 : SCLK_DIV32
slow clock is divided by 32
0x3 : SCLK_DIV64
slow clock is divided by 64
0x4 : SCLK_DIV128
slow clock is divided by 128
0x5 : SCLK_DIV256
slow clock is divided by 256
0x6 : SCLK_DIV512
slow clock is divided by 512
0x7 : SCLK_DIV1024
slow clock is divided by 1024
End of enumeration elements list.
DIV : Clock Division
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : PRESC_CLK_DIV1
clock output from prescaler is divided by 1
0x1 : PRESC_CLK_DIV2
clock output from prescaler is divided by 2
0x2 : PRESC_CLK_DIV3
clock output from prescaler is divided by 3
0x3 : PRESC_CLK_DIV4
clock output from prescaler is divided by 4
0x4 : PRESC_CLK_DIV5
clock output from prescaler is divided by 5
0x5 : PRESC_CLK_DIV6
clock output from prescaler is divided by 6
0x6 : PRESC_CLK_DIV7
clock output from prescaler is divided by 7
0x7 : PRESC_CLK_DIV8
clock output from prescaler is divided by 8
End of enumeration elements list.
SLCDC Display Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISPMODE : Display Mode Register
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal Mode: Latched data are displayed.
0x1 : FORCE_OFF
Force Off Mode: All pixels are invisible. (The SLCDC memory is unchanged.)
0x2 : FORCE_ON
Force On Mode All pixels are visible. (The SLCDC memory is unchanged.)
0x3 : BLINKING
Blinking Mode: All pixels are alternately turned off to the predefined state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
0x4 : INVERTED
Inverted Mode: All pixels are set in the inverted state as defined in SLCDC memory. (The SLCDC memory is unchanged.)
0x5 : INVERTED_BLINK
Inverted Blinking Mode: All pixels are alternately turned off to the predefined opposite state in SLCDC memory at LCDBLKFREQ frequency. (The SLCDC memory is unchanged.)
0x6 : USER_BUFFER_LOAD
User Buffer Only Load Mode: Blocks the automatic transfer from User Buffer to Display Buffer.
0x7 : BUFFERS_SWAP
Buffer Swap Mode: All pixels are alternatively assigned to the state defined in the User Buffer, then to the state defined in the Display Buffer at LCDBLKFREQ frequency.
End of enumeration elements list.
LCDBLKFREQ : LCD Blinking Frequency Selection
bits : 8 - 15 (8 bit)
access : read-write
SLCDC Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
SLCDC Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WPVS : Write Protect Violation Status
bits : 0 - 0 (1 bit)
access : read-only
WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only
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