Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Supply Controller Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
VROFF : Voltage Regulator Off
bits : 2 - 2 (1 bit)
access : write-only
Enumeration:
0 : NO_EFFECT
No effect.
1 : STOP_VREG
If KEY is correct, asserts the system reset signal and stops the voltage regulator.
End of enumeration elements list.
XTALSEL : Crystal Oscillator Select
bits : 3 - 3 (1 bit)
access : write-only
Enumeration:
0 : NO_EFFECT
No effect.
1 : CRYSTAL_SEL
If KEY is correct, switches the slow clock on the crystal oscillator output.
End of enumeration elements list.
KEY : Password
bits : 24 - 31 (8 bit)
access : write-only
Enumeration:
0xA5 : PASSWD
Writing any other value in this field aborts the write operation.
End of enumeration elements list.
Supply Controller Wake-up Inputs Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPEN0 : WKUPx Input Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN1 : WKUPx Input Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN2 : WKUPx Input Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN3 : WKUPx Input Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN4 : WKUPx Input Enable
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN5 : WKUPx Input Enable
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN6 : WKUPx Input Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN7 : WKUPx Input Enable
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN8 : WKUPx Input Enable
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN9 : WKUPx Input Enable
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN10 : WKUPx Input Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN11 : WKUPx Input Enable
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN12 : WKUPx Input Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN13 : WKUPx Input Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN14 : WKUPx Input Enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPEN15 : WKUPx Input Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : DISABLE
The corresponding wake-up input has no wake-up effect.
1 : ENABLE
The corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT0 : WKUPx Input Type
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT1 : WKUPx Input Type
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT2 : WKUPx Input Type
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT3 : WKUPx Input Type
bits : 19 - 19 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT4 : WKUPx Input Type
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT5 : WKUPx Input Type
bits : 21 - 21 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT6 : WKUPx Input Type
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT7 : WKUPx Input Type
bits : 23 - 23 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT8 : WKUPx Input Type
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT9 : WKUPx Input Type
bits : 25 - 25 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT10 : WKUPx Input Type
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT11 : WKUPx Input Type
bits : 27 - 27 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
WKUPT12 : WKUPx Input Type
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : LOW
A low level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
1 : HIGH
A high level for a period defined by WKUPDBC on the corresponding wake-up input forces a system wake-up.
End of enumeration elements list.
Supply Controller Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FWUPS : FWUP Wake-up Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0 : NO
No wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR.
End of enumeration elements list.
WKUPS : WKUP Wake-up Status
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
0 : NO
No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR.
End of enumeration elements list.
SMWS : Supply Monitor Detection Wake-up Status
bits : 2 - 2 (1 bit)
access : read-only
Enumeration:
0 : NO
No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR.
End of enumeration elements list.
BODRSTS : Brownout Detector Reset Status
bits : 3 - 3 (1 bit)
access : read-only
Enumeration:
0 : NO
No core brownout rising edge event has been detected since the last read of SUPC_SR.
1 : PRESENT
At least one brownout output rising edge event has been detected since the last read of SUPC_SR.
End of enumeration elements list.
SMRSTS : Supply Monitor Reset Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0 : NO
No supply monitor detection has generated a system reset since the last read of the SUPC_SR.
1 : PRESENT
At least one supply monitor detection has generated a system reset since the last read of the SUPC_SR.
End of enumeration elements list.
SMS : Supply Monitor Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0 : NO
No supply monitor detection since the last read of SUPC_SR.
1 : PRESENT
At least one supply monitor detection since the last read of SUPC_SR.
End of enumeration elements list.
SMOS : Supply Monitor Output Status
bits : 6 - 6 (1 bit)
access : read-only
Enumeration:
0 : HIGH
The supply monitor detected VDDIO higher than its threshold at its last measurement.
1 : LOW
The supply monitor detected VDDIO lower than its threshold at its last measurement.
End of enumeration elements list.
OSCSEL : 32 kHz Oscillator Selection Status
bits : 7 - 7 (1 bit)
access : read-only
Enumeration:
0 : RC
The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator.
1 : CRYST
The slow clock, SLCK, is generated by the 32 kHz crystal oscillator.
End of enumeration elements list.
LCDS : LCD Status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0 : DISABLED
LCD controller is disabled.
1 : ENABLED
LCD controller is enabled.
End of enumeration elements list.
FWUPIS : FWUP Input Status
bits : 12 - 12 (1 bit)
access : read-only
Enumeration:
0 : LOW
FWUP input is tied low.
1 : HIGH
FWUP input is tied high.
End of enumeration elements list.
LPDBCS0 : Low Power Debouncer Wake-up Status on WKUP0/TMP0
bits : 13 - 13 (1 bit)
access : read-only
Enumeration:
0 : NO
No tamper detection or wake-up due to the assertion of the WKUP0/TMP0 pin has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one tamper detection and wake-up (if enabled by WKUPEN0) due to the assertion of the WKUP0/TMP0 pin has occurred since the last read of SUPC_SR. The SUPC interrupt line is asserted while LPDBCS0 is 1.
End of enumeration elements list.
LPDBCS1 : Low Power Debouncer Wake-up Status on WKUP10/TMP1
bits : 14 - 14 (1 bit)
access : read-only
Enumeration:
0 : NO
No tamper detection or wake-up due to the assertion of the WKUP10 pin has occurred since the last read of SUPC_SR.
1 : PRESENT
At least one tamper detection and wake-up (if enabled by WKUPEN10) due to the assertion of the WKUP10/TMP1 pin has occurred since the last read of SUPC_SR. The SUPC interrupt line is asserted while LPDBCS1 is 1.
End of enumeration elements list.
BUPPORS : Backup Area Power-On Reset Status
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
0 : BUPPOR_DISABLED
Backup POR is disabled.
1 : BUPPOR_ENABLED
Backup POR is enabled.
End of enumeration elements list.
WKUPIS0 : WKUPx Input Status
bits : 16 - 16 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS1 : WKUPx Input Status
bits : 17 - 17 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS2 : WKUPx Input Status
bits : 18 - 18 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS3 : WKUPx Input Status
bits : 19 - 19 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS4 : WKUPx Input Status
bits : 20 - 20 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS5 : WKUPx Input Status
bits : 21 - 21 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS6 : WKUPx Input Status
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS7 : WKUPx Input Status
bits : 23 - 23 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS8 : WKUPx Input Status
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS9 : WKUPx Input Status
bits : 25 - 25 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS10 : WKUPx Input Status
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS11 : WKUPx Input Status
bits : 27 - 27 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
WKUPIS12 : WKUPx Input Status
bits : 28 - 28 (1 bit)
access : read-only
Enumeration:
0 : DIS
The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event.
1 : EN
The corresponding wake-up input was active at the time the debouncer triggered a wake-up event.
End of enumeration elements list.
Supply Controller Supply Monitor Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMTH : Supply Monitor Threshold
bits : 0 - 3 (4 bit)
access : read-write
SMSMPL : Supply Monitor Sampling Period
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : SMD
Supply Monitor disabled
0x1 : CSM
Continuous Supply Monitor
0x2 : 32SLCK
Supply Monitor enabled one SLCK period every 32 SLCK periods
0x3 : 256SLCK
Supply Monitor enabled one SLCK period every 256 SLCK periods
0x4 : 2048SLCK
Supply Monitor enabled one SLCK period every 2,048 SLCK periods
End of enumeration elements list.
SMRSTEN : Supply Monitor Reset Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The system reset signal is not affected when a supply monitor detection occurs.
1 : ENABLE
The system reset signal is asserted when a supply monitor detection occurs.
End of enumeration elements list.
SMIEN : Supply Monitor Interrupt Enable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The SUPC interrupt signal is not affected when a supply monitor detection occurs.
1 : ENABLE
The SUPC interrupt signal is asserted when a supply monitor detection occurs.
End of enumeration elements list.
Supply Controller Mode Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCDVROUT : LCD Voltage Regulator Output
bits : 0 - 3 (4 bit)
access : read-write
LCDMODE : LCD Controller Mode of Operation
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : LCDOFF
The internal supply source and the external supply source are both deselected (OFF Mode).
0x2 : LCDON_EXTVR
The external supply source for LCD (VDDLCD) is selected (the LCD voltage regulator is in Hi-Z Mode).
0x3 : LCDON_INVR
The internal supply source for LCD (the LCD Voltage Regulator) is selected (Active Mode).
End of enumeration elements list.
BODRSTEN : Brownout Detector Reset Enable
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The system reset signal is not affected when a brownout detection occurs.
1 : ENABLE
The system reset signal is asserted when a brownout detection occurs.
End of enumeration elements list.
BODDIS : Brownout Detector Disable
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
0 : ENABLE
The core brownout detector is enabled.
1 : DISABLE
The core brownout detector is disabled.
End of enumeration elements list.
ONREG : Voltage Regulator enable
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0 : ONREG_UNUSED
Internal voltage regulator is not used (external power supply is used).
1 : ONREG_USED
Internal voltage regulator is used.
End of enumeration elements list.
BUPPOREN : Backup Area Power-On Reset Enable
bits : 15 - 15 (1 bit)
access : read-write
Enumeration:
0 : BUPPOR_DISABLE
Disables the backup POR.
1 : BUPPOR_ENABLE
Enables the backup POR.
End of enumeration elements list.
OSCBYPASS : Oscillator Bypass
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0 : NO_EFFECT
No effect. Clock selection depends on XTALSEL value.
1 : BYPASS
The 32 kHz crystal oscillator is selected and put in bypass mode.
End of enumeration elements list.
KEY : Password Key
bits : 24 - 31 (8 bit)
access : read-write
Enumeration:
0xA5 : PASSWD
Writing any other value in this field aborts the write operation.
End of enumeration elements list.
Supply Controller Wake-up Mode Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FWUPEN : Force Wake-up Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The force wake-up pin has no wake-up effect.
1 : ENABLE
The force wake-up pin low forces a system wake-up.
End of enumeration elements list.
SMEN : Supply Monitor Wake-up Enable
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The supply monitor detection has no wake-up effect.
1 : ENABLE
The supply monitor detection forces a system wake-up.
End of enumeration elements list.
RTTEN : Real-time Timer Wake-up Enable
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The RTT alarm signal has no wake-up effect.
1 : ENABLE
The RTT alarm signal forces a system wake-up.
End of enumeration elements list.
RTCEN : Real-time Clock Wake-up Enable
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The RTC alarm signal has no wake-up effect.
1 : ENABLE
The RTC alarm signal forces a system wake-up.
End of enumeration elements list.
LPDBCEN0 : Low-Power Debouncer Enable WKUP0/TMP0
bits : 5 - 5 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The WKUP0/TMP0 input pin is not connected to the low-power debouncer.
1 : ENABLE
The WKUP0/TMP0 input pin is connected to the low-power debouncer and can force a system wake-up.
End of enumeration elements list.
LPDBCEN1 : Low-Power Debouncer Enable WKUP10/TMP1
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
The WKUP10/TMP1 input pin is not connected to the low-power debouncer.
1 : ENABLE
The WKUP10/TMP1 input pin is connected to the low-power debouncer and can force a system wake-up.
End of enumeration elements list.
LPDBCCLR : Low-Power Debouncer Clear
bits : 7 - 7 (1 bit)
access : read-write
Enumeration:
0 : NOT_ENABLE
A low-power debounce event does not create an immediate clear on the first half of GPBR registers.
1 : ENABLE
A low-power debounce event on WKUP0/TMP0 or WKUP10TMP1(if DISTMPCLR1 is cleared) generates an immediate clear on the first half of GPBR registers.
End of enumeration elements list.
FWUPDBC : Force Wake-up Debouncer Period
bits : 8 - 10 (3 bit)
access : read-write
Enumeration:
0x0 : IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x1 : 3_SCLK
FWUP shall be low for at least 3 SLCK periods
0x2 : 32_SCLK
FWUP shall be low for at least 32 SLCK periods
0x3 : 512_SCLK
FWUP shall be low for at least 512 SLCK periods
0x4 : 4096_SCLK
FWUP shall be low for at least 4,096 SLCK periods
0x5 : 32768_SCLK
FWUP shall be low for at least 32,768 SLCK periods
End of enumeration elements list.
WKUPDBC : Wake-up Inputs Debouncer Period
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : IMMEDIATE
Immediate, no debouncing, detected active at least on one Slow Clock edge.
0x1 : 3_SCLK
WKUPx shall be in its active state for at least 3 SLCK periods
0x2 : 32_SCLK
WKUPx shall be in its active state for at least 32 SLCK periods
0x3 : 512_SCLK
WKUPx shall be in its active state for at least 512 SLCK periods
0x4 : 4096_SCLK
WKUPx shall be in its active state for at least 4,096 SLCK periods
0x5 : 32768_SCLK
WKUPx shall be in its active state for at least 32,768 SLCK periods
End of enumeration elements list.
LPDBC : Low Power Debouncer Period
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : DISABLE
Disable the low-power debouncers.
0x1 : 2_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 2 RTCOUT0 periods
0x2 : 3_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 3 RTCOUT0 periods
0x3 : 4_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 4 RTCOUT0 periods
0x4 : 5_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 5 RTCOUT0 periods
0x5 : 6_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 6 RTCOUT0 periods
0x6 : 7_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 7 RTCOUT0 periods
0x7 : 8_RTCOUT0
WKUP0/10TMP0/1 in active state for at least 8 RTCOUT0 periods
End of enumeration elements list.
DISTMPCLR1 : Disable GPBR Clear Command from WKUP10/TMP1 pin
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
0 : ENABLE
The WKUP10/TMP1 input pin can clear the GPBR (if LPDBCCLR is enabled) when tamper is detected.
1 : DISABLE
The WKUP10/TMP1 input pin has no effect on the GPBR value (no clear on tamper detection).
End of enumeration elements list.
DISTSTMP1 : Disable Timestamp from WKUP10/TMP1 Pin
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
0 : ENABLE
A tamper detection on WKUP10/TMP1 pin generates a timestamp.
1 : DISABLE
A tamper detection on WKUP10/TMP1 does NOT generate a report in timestamp register.
End of enumeration elements list.
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