\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
PWM Mode Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVA : CLKA, CLKB Divide Factor
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
0 : CLK_OFF
CLKA, CLKB clock is turned off
1 : CLK_DIV1
CLKA, CLKB clock is clock selected by PREA, PREB
End of enumeration elements list.
PREA :
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock
0x1 : MCKDIV2
Master Clock divided by 2
0x2 : MCKDIV4
Master Clock divided by 4
0x3 : MCKDIV8
Master Clock divided by 8
0x4 : MCKDIV16
Master Clock divided by 16
0x5 : MCKDIV32
Master Clock divided by 32
0x6 : MCKDIV64
Master Clock divided by 64
0x7 : MCKDIV128
Master Clock divided by 128
0x8 : MCKDIV256
Master Clock divided by 256
0x9 : MCKDIV512
Master Clock divided by 512
0xA : MCKDIV1024
Master Clock divided by 1024
End of enumeration elements list.
DIVB : CLKA, CLKB Divide Factor
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
0 : CLK_OFF
CLKA, CLKB clock is turned off
1 : CLK_DIV1
CLKA, CLKB clock is clock selected by PREA, PREB
End of enumeration elements list.
PREB :
bits : 24 - 27 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock
0x1 : MCKDIV2
Master Clock divided by 2
0x2 : MCKDIV4
Master Clock divided by 4
0x3 : MCKDIV8
Master Clock divided by 8
0x4 : MCKDIV16
Master Clock divided by 16
0x5 : MCKDIV32
Master Clock divided by 32
0x6 : MCKDIV64
Master Clock divided by 64
0x7 : MCKDIV128
Master Clock divided by 128
0x8 : MCKDIV256
Master Clock divided by 256
0x9 : MCKDIV512
Master Clock divided by 512
0xA : MCKDIV1024
Master Clock divided by 1024
End of enumeration elements list.
PWM Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID.
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID.
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID.
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID.
bits : 3 - 3 (1 bit)
access : write-only
PWM Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID.
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID.
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID.
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID.
bits : 3 - 3 (1 bit)
access : write-only
PWM Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID.
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Channel ID.
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Channel ID.
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Channel ID.
bits : 3 - 3 (1 bit)
access : read-only
PWM Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only
PWM Channel Mode Register (ch_num = 0)
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock
0x1 : MCKDIV2
Master Clock divided by 2
0x2 : MCKDIV4
Master Clock divided by 4
0x3 : MCKDIV8
Master Clock divided by 8
0x4 : MCKDIV16
Master Clock divided by 16
0x5 : MCKDIV32
Master Clock divided by 32
0x6 : MCKDIV64
Master Clock divided by 64
0x7 : MCKDIV128
Master Clock divided by 128
0x8 : MCKDIV256
Master Clock divided by 256
0x9 : MCKDIV512
Master Clock divided by 512
0xA : MCKDIV1024
Master Clock divided by 1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 0)
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Period Register (ch_num = 0)
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Counter Register (ch_num = 0)
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only
PWM Channel Update Register (ch_num = 0)
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CUPD :
bits : 0 - 31 (32 bit)
access : write-only
PWM Channel Mode Register (ch_num = 1)
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock
0x1 : MCKDIV2
Master Clock divided by 2
0x2 : MCKDIV4
Master Clock divided by 4
0x3 : MCKDIV8
Master Clock divided by 8
0x4 : MCKDIV16
Master Clock divided by 16
0x5 : MCKDIV32
Master Clock divided by 32
0x6 : MCKDIV64
Master Clock divided by 64
0x7 : MCKDIV128
Master Clock divided by 128
0x8 : MCKDIV256
Master Clock divided by 256
0x9 : MCKDIV512
Master Clock divided by 512
0xA : MCKDIV1024
Master Clock divided by 1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 1)
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Period Register (ch_num = 1)
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Counter Register (ch_num = 1)
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only
PWM Channel Update Register (ch_num = 1)
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CUPD :
bits : 0 - 31 (32 bit)
access : write-only
PWM Channel Mode Register (ch_num = 2)
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock
0x1 : MCKDIV2
Master Clock divided by 2
0x2 : MCKDIV4
Master Clock divided by 4
0x3 : MCKDIV8
Master Clock divided by 8
0x4 : MCKDIV16
Master Clock divided by 16
0x5 : MCKDIV32
Master Clock divided by 32
0x6 : MCKDIV64
Master Clock divided by 64
0x7 : MCKDIV128
Master Clock divided by 128
0x8 : MCKDIV256
Master Clock divided by 256
0x9 : MCKDIV512
Master Clock divided by 512
0xA : MCKDIV1024
Master Clock divided by 1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 2)
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Period Register (ch_num = 2)
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Counter Register (ch_num = 2)
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only
PWM Channel Update Register (ch_num = 2)
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CUPD :
bits : 0 - 31 (32 bit)
access : write-only
PWM Channel Mode Register (ch_num = 3)
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRE : Channel Pre-scaler
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0x0 : MCK
Master Clock
0x1 : MCKDIV2
Master Clock divided by 2
0x2 : MCKDIV4
Master Clock divided by 4
0x3 : MCKDIV8
Master Clock divided by 8
0x4 : MCKDIV16
Master Clock divided by 16
0x5 : MCKDIV32
Master Clock divided by 32
0x6 : MCKDIV64
Master Clock divided by 64
0x7 : MCKDIV128
Master Clock divided by 128
0x8 : MCKDIV256
Master Clock divided by 256
0x9 : MCKDIV512
Master Clock divided by 512
0xA : MCKDIV1024
Master Clock divided by 1024
0xB : CLKA
Clock A
0xC : CLKB
Clock B
End of enumeration elements list.
CALG : Channel Alignment
bits : 8 - 8 (1 bit)
access : read-write
CPOL : Channel Polarity
bits : 9 - 9 (1 bit)
access : read-write
CPD : Channel Update Period
bits : 10 - 10 (1 bit)
access : read-write
PWM Channel Duty Cycle Register (ch_num = 3)
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CDTY : Channel Duty Cycle
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Period Register (ch_num = 3)
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPRD : Channel Period
bits : 0 - 31 (32 bit)
access : read-write
PWM Channel Counter Register (ch_num = 3)
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CNT : Channel Counter Register
bits : 0 - 31 (32 bit)
access : read-only
PWM Channel Update Register (ch_num = 3)
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CUPD :
bits : 0 - 31 (32 bit)
access : write-only
PWM Enable Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only
PWM Disable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : write-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : write-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : write-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : write-only
PWM Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CHID0 : Channel ID
bits : 0 - 0 (1 bit)
access : read-only
CHID1 : Channel ID
bits : 1 - 1 (1 bit)
access : read-only
CHID2 : Channel ID
bits : 2 - 2 (1 bit)
access : read-only
CHID3 : Channel ID
bits : 3 - 3 (1 bit)
access : read-only
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