\n

SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

SR

RPR

RCR

CSR[3]

TPR

TCR

RNPR

RNCR

TNPR

TNCR

PTCR

PTSR

IER

IDR

IMR

CSR0

CSR1

CSR2

CSR3

MR

CSR[0]

RDR

CSR[1]

TDR

CSR[2]

WPMR

WPSR


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

CR CR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPIEN SPIDIS SWRST LASTXFER

SPIEN : SPI Enable
bits : 0 - 0 (1 bit)
access : write-only

SPIDIS : SPI Disable
bits : 1 - 1 (1 bit)
access : write-only

SWRST : SPI Software Reset
bits : 7 - 7 (1 bit)
access : write-only

LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only


SR

Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES ENDRX ENDTX RXBUFF TXBUFE NSSR TXEMPTY UNDES SPIENS

RDRF : Receive Data Register Full (automatically set / cleared)
bits : 0 - 0 (1 bit)
access : read-only

TDRE : Transmit Data Register Empty (automatically set / cleared)
bits : 1 - 1 (1 bit)
access : read-only

MODF : Mode Fault Error (cleared on read)
bits : 2 - 2 (1 bit)
access : read-only

OVRES : Overrun Error Status (cleared on read)
bits : 3 - 3 (1 bit)
access : read-only

ENDRX : End of RX Buffer (automatically set / cleared)
bits : 4 - 4 (1 bit)
access : read-only

ENDTX : End of TX Buffer (automatically set / cleared)
bits : 5 - 5 (1 bit)
access : read-only

RXBUFF : RX Buffer Full (automatically set / cleared)
bits : 6 - 6 (1 bit)
access : read-only

TXBUFE : TX Buffer Empty (automatically set / cleared)
bits : 7 - 7 (1 bit)
access : read-only

NSSR : NSS Rising (cleared on read)
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmission Registers Empty (automatically set / cleared)
bits : 9 - 9 (1 bit)
access : read-only

UNDES : Underrun Error Status (Slave mode only) (cleared on read)
bits : 10 - 10 (1 bit)
access : read-only

SPIENS : SPI Enable Status
bits : 16 - 16 (1 bit)
access : read-only


RPR

Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RPR RPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXPTR

RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write


RCR

Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR RCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCTR

RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write


CSR[3]

Chip Select Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR[3] CSR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


TPR

Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TPR TPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXPTR

TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write


TCR

Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCR TCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCTR

TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write


RNPR

Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNPR RNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNPTR

RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


RNCR

Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RNCR RNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNCTR

RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write


TNPR

Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNPR TNPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNPTR

TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write


TNCR

Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TNCR TNCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXNCTR

TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write


PTCR

Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

PTCR PTCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN RXTDIS TXTEN TXTDIS

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only

RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only

TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only


PTSR

Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PTSR PTSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXTEN TXTEN

RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only

TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only


IER

Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES ENDRX ENDTX RXBUFF TXBUFE NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only

TDRE : SPI Transmit Data Register Empty Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only

MODF : Mode Fault Error Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only

OVRES : Overrun Error Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Enable
bits : 5 - 5 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Enable
bits : 6 - 6 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 7 - 7 (1 bit)
access : write-only

NSSR : NSS Rising Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : Transmission Registers Empty Enable
bits : 9 - 9 (1 bit)
access : write-only

UNDES : Underrun Error Interrupt Enable
bits : 10 - 10 (1 bit)
access : write-only


IDR

Interrupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES ENDRX ENDTX RXBUFF TXBUFE NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only

TDRE : SPI Transmit Data Register Empty Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only

MODF : Mode Fault Error Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only

OVRES : Overrun Error Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only

ENDRX : End of Receive Buffer Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only

ENDTX : End of Transmit Buffer Interrupt Disable
bits : 5 - 5 (1 bit)
access : write-only

RXBUFF : Receive Buffer Full Interrupt Disable
bits : 6 - 6 (1 bit)
access : write-only

TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 7 - 7 (1 bit)
access : write-only

NSSR : NSS Rising Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only

TXEMPTY : Transmission Registers Empty Disable
bits : 9 - 9 (1 bit)
access : write-only

UNDES : Underrun Error Interrupt Disable
bits : 10 - 10 (1 bit)
access : write-only


IMR

Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRF TDRE MODF OVRES ENDRX ENDTX RXBUFF TXBUFE NSSR TXEMPTY UNDES

RDRF : Receive Data Register Full Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only

TDRE : SPI Transmit Data Register Empty Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only

MODF : Mode Fault Error Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only

OVRES : Overrun Error Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only

ENDRX : End of Receive Buffer Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only

ENDTX : End of Transmit Buffer Interrupt Mask
bits : 5 - 5 (1 bit)
access : read-only

RXBUFF : Receive Buffer Full Interrupt Mask
bits : 6 - 6 (1 bit)
access : read-only

TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 7 - 7 (1 bit)
access : read-only

NSSR : NSS Rising Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only

TXEMPTY : Transmission Registers Empty Mask
bits : 9 - 9 (1 bit)
access : read-only

UNDES : Underrun Error Interrupt Mask
bits : 10 - 10 (1 bit)
access : read-only


CSR0

Chip Select Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR0 CSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


CSR1

Chip Select Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR1 CSR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


CSR2

Chip Select Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR2 CSR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


CSR3

Chip Select Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

CSR3 CSR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


MR

Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MR MR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSTR PS PCSDEC MODFDIS WDRBT LLB PCS DLYBCS

MSTR : Master/Slave Mode
bits : 0 - 0 (1 bit)
access : read-write

PS : Peripheral Select
bits : 1 - 1 (1 bit)
access : read-write

PCSDEC : Chip Select Decode
bits : 2 - 2 (1 bit)
access : read-write

MODFDIS : Mode Fault Detection
bits : 4 - 4 (1 bit)
access : read-write

WDRBT : Wait Data Read Before Transfer
bits : 5 - 5 (1 bit)
access : read-write

LLB : Local Loopback Enable
bits : 7 - 7 (1 bit)
access : read-write

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-write

DLYBCS : Delay Between Chip Selects
bits : 24 - 31 (8 bit)
access : read-write


CSR[0]

Chip Select Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR[0] CSR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


RDR

Receive Data Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RDR RDR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD PCS

RD : Receive Data
bits : 0 - 15 (16 bit)
access : read-only

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : read-only


CSR[1]

Chip Select Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR[1] CSR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


TDR

Transmit Data Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

TDR TDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TD PCS LASTXFER

TD : Transmit Data
bits : 0 - 15 (16 bit)
access : write-only

PCS : Peripheral Chip Select
bits : 16 - 19 (4 bit)
access : write-only

LASTXFER : Last Transfer
bits : 24 - 24 (1 bit)
access : write-only


CSR[2]

Chip Select Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CSR[2] CSR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPOL NCPHA CSNAAT CSAAT BITS SCBR DLYBS DLYBCT

CPOL : Clock Polarity
bits : 0 - 0 (1 bit)
access : read-write

NCPHA : Clock Phase
bits : 1 - 1 (1 bit)
access : read-write

CSNAAT : Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
bits : 2 - 2 (1 bit)
access : read-write

CSAAT : Chip Select Active After Transfer
bits : 3 - 3 (1 bit)
access : read-write

BITS : Bits Per Transfer
bits : 4 - 7 (4 bit)
access : read-write

Enumeration:

0x0 : 8_BIT

8 bits for transfer

0x1 : 9_BIT

9 bits for transfer

0x2 : 10_BIT

10 bits for transfer

0x3 : 11_BIT

11 bits for transfer

0x4 : 12_BIT

12 bits for transfer

0x5 : 13_BIT

13 bits for transfer

0x6 : 14_BIT

14 bits for transfer

0x7 : 15_BIT

15 bits for transfer

0x8 : 16_BIT

16 bits for transfer

End of enumeration elements list.

SCBR : Serial Clock Baud Rate
bits : 8 - 15 (8 bit)
access : read-write

DLYBS : Delay Before SPCK
bits : 16 - 23 (8 bit)
access : read-write

DLYBCT : Delay Between Consecutive Transfers
bits : 24 - 31 (8 bit)
access : read-write


WPMR

Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protection Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protection Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x535049 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 15 (8 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.