\n
address_offset : 0x0 Bytes (0x0)
size : 0x140 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RSTRX : Reset Receiver
bits : 2 - 2 (1 bit)
access : write-only
RSTTX : Reset Transmitter
bits : 3 - 3 (1 bit)
access : write-only
RXEN : Receiver Enable
bits : 4 - 4 (1 bit)
access : write-only
RXDIS : Receiver Disable
bits : 5 - 5 (1 bit)
access : write-only
TXEN : Transmitter Enable
bits : 6 - 6 (1 bit)
access : write-only
TXDIS : Transmitter Disable
bits : 7 - 7 (1 bit)
access : write-only
RSTSTA : Reset Status
bits : 8 - 8 (1 bit)
access : write-only
Interrupt Mask Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Mask RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : read-only
ENDRX : Mask End of Receive Transfer Interrupt
bits : 3 - 3 (1 bit)
access : read-only
ENDTX : Mask End of Transmit Interrupt
bits : 4 - 4 (1 bit)
access : read-only
OVRE : Mask Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Mask Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : read-only
PARE : Mask Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : read-only
TXEMPTY : Mask TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : read-only
TXBUFE : Mask TXBUFE Interrupt
bits : 11 - 11 (1 bit)
access : read-only
RXBUFF : Mask RXBUFF Interrupt
bits : 12 - 12 (1 bit)
access : read-only
Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write
Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
Status Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Receiver Ready
bits : 0 - 0 (1 bit)
access : read-only
TXRDY : Transmitter Ready
bits : 1 - 1 (1 bit)
access : read-only
ENDRX : End of Receiver Transfer
bits : 3 - 3 (1 bit)
access : read-only
ENDTX : End of Transmitter Transfer
bits : 4 - 4 (1 bit)
access : read-only
OVRE : Overrun Error
bits : 5 - 5 (1 bit)
access : read-only
FRAME : Framing Error
bits : 6 - 6 (1 bit)
access : read-only
PARE : Parity Error
bits : 7 - 7 (1 bit)
access : read-only
TXEMPTY : Transmitter Empty
bits : 9 - 9 (1 bit)
access : read-only
TXBUFE : Transmission Buffer Empty
bits : 11 - 11 (1 bit)
access : read-only
RXBUFF : Receive Buffer Full
bits : 12 - 12 (1 bit)
access : read-only
Receive Holding Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXCHR : Received Character
bits : 0 - 7 (8 bit)
access : read-only
Transmit Holding Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXCHR : Character to be Transmitted
bits : 0 - 7 (8 bit)
access : write-only
Baud Rate Generator Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD : Clock Divisor
bits : 0 - 15 (16 bit)
access : read-write
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OPT_EN : UART Optical Interface Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The UART transmitter data is not inverted before modulation.
1 : ENABLED
The UART transmitter data is inverted before modulation.
End of enumeration elements list.
OPT_RXINV : UART Receive Data Inverted
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The comparator data output is not inverted before entering UART.
1 : ENABLED
The comparator data output is inverted before entering UART.
End of enumeration elements list.
OPT_MDINV : UART Modulated Data Inverted
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
The output of the modulator is not inverted.
1 : ENABLED
The output of the modulator is inverted.
End of enumeration elements list.
FILTER : Receiver Digital Filter
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0 : DISABLED
UART does not filter the receive line.
1 : ENABLED
UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority).
End of enumeration elements list.
PAR : Parity Type
bits : 9 - 11 (3 bit)
access : read-write
Enumeration:
0x0 : EVEN
Even Parity
0x1 : ODD
Odd Parity
0x2 : SPACE
Space: parity forced to 0
0x3 : MARK
Mark: parity forced to 1
0x4 : NO
No parity
End of enumeration elements list.
CHMODE : Channel Mode
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0x0 : NORMAL
Normal mode
0x1 : AUTOMATIC
Automatic echo
0x2 : LOCAL_LOOPBACK
Local loopback
0x3 : REMOTE_LOOPBACK
Remote loopback
End of enumeration elements list.
OPT_CLKDIV : Optical Link Clock Divider
bits : 16 - 20 (5 bit)
access : read-write
OPT_DUTY : Optical Link Modulation Clock Duty Cycle
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : DUTY_50
Modulation clock duty cycle Is 50%.
0x1 : DUTY_43P75
Modulation clock duty cycle Is 43.75%.
0x2 : DUTY_37P5
Modulation clock duty cycle Is 37.5%.
0x3 : DUTY_31P25
Modulation clock duty cycle Is 31.75%.
0x4 : DUTY_25
Modulation clock duty cycle Is 25%.
0x5 : DUTY_18P75
Modulation clock duty cycle Is 18.75%.
0x6 : DUTY_12P5
Modulation clock duty cycle Is 12.5%.
0x7 : DUTY_6P25
Modulation clock duty cycle Is 6.25%.
End of enumeration elements list.
OPT_CMPTH : Receive Path Comparator Threshold
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
0x0 : VDDIO_DIV2
Comparator threshold is VDDIO/2 volts.
0x1 : VDDIO_DIV2P5
Comparator threshold is VDDIO/2.5 volts.
0x2 : VDDIO_DIV3P3
Comparator threshold is VDDIO/3.3 volts.
0x3 : VDDIO_DIV5
Comparator threshold is VDDIO/5 volts.
0x4 : VDDIO_DIV10
Comparator threshold is VDDIO/10 volts.
End of enumeration elements list.
Interrupt Enable Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Enable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : Enable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only
ENDRX : Enable End of Receive Transfer Interrupt
bits : 3 - 3 (1 bit)
access : write-only
ENDTX : Enable End of Transmit Interrupt
bits : 4 - 4 (1 bit)
access : write-only
OVRE : Enable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Enable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only
PARE : Enable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only
TXEMPTY : Enable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only
TXBUFE : Enable Buffer Empty Interrupt
bits : 11 - 11 (1 bit)
access : write-only
RXBUFF : Enable Buffer Full Interrupt
bits : 12 - 12 (1 bit)
access : write-only
Interrupt Disable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXRDY : Disable RXRDY Interrupt
bits : 0 - 0 (1 bit)
access : write-only
TXRDY : Disable TXRDY Interrupt
bits : 1 - 1 (1 bit)
access : write-only
ENDRX : Disable End of Receive Transfer Interrupt
bits : 3 - 3 (1 bit)
access : write-only
ENDTX : Disable End of Transmit Interrupt
bits : 4 - 4 (1 bit)
access : write-only
OVRE : Disable Overrun Error Interrupt
bits : 5 - 5 (1 bit)
access : write-only
FRAME : Disable Framing Error Interrupt
bits : 6 - 6 (1 bit)
access : write-only
PARE : Disable Parity Error Interrupt
bits : 7 - 7 (1 bit)
access : write-only
TXEMPTY : Disable TXEMPTY Interrupt
bits : 9 - 9 (1 bit)
access : write-only
TXBUFE : Disable Buffer Empty Interrupt
bits : 11 - 11 (1 bit)
access : write-only
RXBUFF : Disable Buffer Full Interrupt
bits : 12 - 12 (1 bit)
access : write-only
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