\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
WDRSTT : Watchdog Restart
bits : 0 - 0 (1 bit)
access : write-only
KEY : Password
bits : 24 - 31 (8 bit)
access : write-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDV : Watchdog Counter Value
bits : 0 - 11 (12 bit)
access : read-write
WDFIEN : Watchdog Fault Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write
WDRSTEN : Watchdog Reset Enable
bits : 13 - 13 (1 bit)
access : read-write
WDRPROC : Watchdog Reset Processor
bits : 14 - 14 (1 bit)
access : read-write
WDDIS : Watchdog Disable
bits : 15 - 15 (1 bit)
access : read-write
WDD : Watchdog Delta Value
bits : 16 - 27 (12 bit)
access : read-write
WDDBGHLT : Watchdog Debug Halt
bits : 28 - 28 (1 bit)
access : read-write
WDIDLEHLT : Watchdog Idle Halt
bits : 29 - 29 (1 bit)
access : read-write
Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
WDUNF : Watchdog Underflow
bits : 0 - 0 (1 bit)
access : read-only
WDERR : Watchdog Error
bits : 1 - 1 (1 bit)
access : read-only
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