\n

SMC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SETUP0

SETUP1

PULSE1

CYCLE1

MODE1

SETUP2

PULSE2

CYCLE2

MODE2

SETUP3

PULSE3

CYCLE3

MODE3

PULSE0

CYCLE0

OCMS

KEY1

KEY2

MODE0

WPMR

WPSR


SETUP0

SMC Setup Register (CS_number = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP0 SETUP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


SETUP1

SMC Setup Register (CS_number = 1)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP1 SETUP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE1

SMC Pulse Register (CS_number = 1)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE1 PULSE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE1

SMC Cycle Register (CS_number = 1)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE1 CYCLE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE1

SMC Mode Register (CS_number = 1)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE1 MODE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x2 : FROZEN

Frozen Mode

0x3 : READY

Ready Mode

End of enumeration elements list.

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : BYTE_SELECT

Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.

1 : BYTE_WRITE

Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.

End of enumeration elements list.

DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : 8_BIT

8-bit Data Bus

1 : 16_BIT

16-bit Data Bus

End of enumeration elements list.

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 4_BYTE

4-byte page

0x1 : 8_BYTE

8-byte page

0x2 : 16_BYTE

16-byte page

0x3 : 32_BYTE

32-byte page

End of enumeration elements list.


SETUP2

SMC Setup Register (CS_number = 2)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP2 SETUP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE2

SMC Pulse Register (CS_number = 2)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE2 PULSE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE2

SMC Cycle Register (CS_number = 2)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE2 CYCLE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE2

SMC Mode Register (CS_number = 2)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE2 MODE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x2 : FROZEN

Frozen Mode

0x3 : READY

Ready Mode

End of enumeration elements list.

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : BYTE_SELECT

Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.

1 : BYTE_WRITE

Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.

End of enumeration elements list.

DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : 8_BIT

8-bit Data Bus

1 : 16_BIT

16-bit Data Bus

End of enumeration elements list.

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 4_BYTE

4-byte page

0x1 : 8_BYTE

8-byte page

0x2 : 16_BYTE

16-byte page

0x3 : 32_BYTE

32-byte page

End of enumeration elements list.


SETUP3

SMC Setup Register (CS_number = 3)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SETUP3 SETUP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_SETUP NCS_WR_SETUP NRD_SETUP NCS_RD_SETUP

NWE_SETUP : NWE Setup Length
bits : 0 - 5 (6 bit)
access : read-write

NCS_WR_SETUP : NCS Setup Length in WRITE Access
bits : 8 - 13 (6 bit)
access : read-write

NRD_SETUP : NRD Setup Length
bits : 16 - 21 (6 bit)
access : read-write

NCS_RD_SETUP : NCS Setup Length in READ Access
bits : 24 - 29 (6 bit)
access : read-write


PULSE3

SMC Pulse Register (CS_number = 3)
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE3 PULSE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE3

SMC Cycle Register (CS_number = 3)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE3 CYCLE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


MODE3

SMC Mode Register (CS_number = 3)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE3 MODE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x2 : FROZEN

Frozen Mode

0x3 : READY

Ready Mode

End of enumeration elements list.

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : BYTE_SELECT

Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.

1 : BYTE_WRITE

Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.

End of enumeration elements list.

DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : 8_BIT

8-bit Data Bus

1 : 16_BIT

16-bit Data Bus

End of enumeration elements list.

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 4_BYTE

4-byte page

0x1 : 8_BYTE

8-byte page

0x2 : 16_BYTE

16-byte page

0x3 : 32_BYTE

32-byte page

End of enumeration elements list.


PULSE0

SMC Pulse Register (CS_number = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PULSE0 PULSE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_PULSE NCS_WR_PULSE NRD_PULSE NCS_RD_PULSE

NWE_PULSE : NWE Pulse Length
bits : 0 - 6 (7 bit)
access : read-write

NCS_WR_PULSE : NCS Pulse Length in WRITE Access
bits : 8 - 14 (7 bit)
access : read-write

NRD_PULSE : NRD Pulse Length
bits : 16 - 22 (7 bit)
access : read-write

NCS_RD_PULSE : NCS Pulse Length in READ Access
bits : 24 - 30 (7 bit)
access : read-write


CYCLE0

SMC Cycle Register (CS_number = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CYCLE0 CYCLE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NWE_CYCLE NRD_CYCLE

NWE_CYCLE : Total Write Cycle Length
bits : 0 - 8 (9 bit)
access : read-write

NRD_CYCLE : Total Read Cycle Length
bits : 16 - 24 (9 bit)
access : read-write


OCMS

SMC OCMS MODE Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OCMS OCMS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMSE CS0SE CS1SE CS2SE CS3SE

SMSE : Static Memory Controller Scrambling EnableSAM4C0x00030003CS0SECS1SECS1SECS2SECS3SE
bits : 0 - 0 (1 bit)
access : read-write

CS0SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 16 - 16 (1 bit)
access : read-write

CS1SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 17 - 17 (1 bit)
access : read-write

CS2SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 18 - 18 (1 bit)
access : read-write

CS3SE : Chip Select (x = 0 to 3) Scrambling Enable
bits : 19 - 19 (1 bit)
access : read-write


KEY1

SMC OCMS KEY1 Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY1 KEY1 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY1

KEY1 : Off Chip Memory Scrambling (OCMS) Key Part 1
bits : 0 - 31 (32 bit)
access : write-only


KEY2

SMC OCMS KEY2 Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEY2 KEY2 write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEY2

KEY2 : Off Chip Memory Scrambling (OCMS) Key Part 2
bits : 0 - 31 (32 bit)
access : write-only


MODE0

SMC Mode Register (CS_number = 0)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE0 MODE0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_MODE WRITE_MODE EXNW_MODE BAT DBW TDF_CYCLES TDF_MODE PMEN PS

READ_MODE : Read Mode
bits : 0 - 0 (1 bit)
access : read-write

WRITE_MODE : Write Mode
bits : 1 - 1 (1 bit)
access : read-write

EXNW_MODE : NWAIT Mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0x0 : DISABLED

Disabled

0x2 : FROZEN

Frozen Mode

0x3 : READY

Ready Mode

End of enumeration elements list.

BAT : Byte Access Type
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : BYTE_SELECT

Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1.

1 : BYTE_WRITE

Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD.

End of enumeration elements list.

DBW : Data Bus Width
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0 : 8_BIT

8-bit Data Bus

1 : 16_BIT

16-bit Data Bus

End of enumeration elements list.

TDF_CYCLES : Data Float Time
bits : 16 - 19 (4 bit)
access : read-write

TDF_MODE : TDF Optimization
bits : 20 - 20 (1 bit)
access : read-write

PMEN : Page Mode Enabled
bits : 24 - 24 (1 bit)
access : read-write

PS : Page Size
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0x0 : 4_BYTE

4-byte page

0x1 : 8_BYTE

8-byte page

0x2 : 16_BYTE

16-byte page

0x3 : 32_BYTE

32-byte page

End of enumeration elements list.


WPMR

SMC Write Protect Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write


WPSR

SMC Write Protect Status Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protect Violation Source
bits : 8 - 23 (16 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.