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MATRIX

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MCFG[0]

MCFG0

MCFG4

SCFG[2]

SYSIO

SMCNFCS

CORE_DEBUG

MCFG5

SCFG[3]

MCFG[3]

MCFG6

SCFG[4]

WPMR

WPSR

SCFG[5]

SCFG[6]

MCFG[4]

SCFG[7]

MCFG[5]

MCFG[1]

MCFG1

SCFG0

SCFG1

SCFG2

SCFG3

SCFG4

MCFG[6]

SCFG5

SCFG6

SCFG7

MCFG2

SCFG[0]

PRAS0

PRAS1

PRAS2

PRAS3

PRAS4

PRAS5

PRAS6

PRAS7

MCFG[2]

MCFG3

SCFG[1]


MCFG[0]

Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[0] MCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


MCFG0

Master Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG0 MCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


MCFG4

Master Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG4 MCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG[2]

Slave Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[2] SCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SYSIO

System I/O Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYSIO SYSIO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSIO0 SYSIO1 SYSIO2 SYSIO3 SYSIO9

SYSIO0 : PB0 or TDI Assignment
bits : 0 - 0 (1 bit)
access : read-write

SYSIO1 : PB1 or TDO/TRACESWO Assignment
bits : 1 - 1 (1 bit)
access : read-write

SYSIO2 : PB2 or TMS/SWDIO Assignment
bits : 2 - 2 (1 bit)
access : read-write

SYSIO3 : PB3 or TCK/SWCLK Assignment
bits : 3 - 3 (1 bit)
access : read-write

SYSIO9 : PC9 or ERASE Assignment
bits : 9 - 9 (1 bit)
access : read-write


SMCNFCS

SMC Nand Flash Chip Select Configuration Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SMCNFCS SMCNFCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMC_NFCS0 SMC_NFCS1 SMC_NFCS2 SMC_NFCS3 SMC_SEL

SMC_NFCS0 : SMC NAND Flash Chip Select 0 Assignment
bits : 0 - 0 (1 bit)
access : read-write

SMC_NFCS1 : SMC NAND Flash Chip Select 1 Assignment
bits : 1 - 1 (1 bit)
access : read-write

SMC_NFCS2 : SMC NAND Flash Chip Select 2 Assignment
bits : 2 - 2 (1 bit)
access : read-write

SMC_NFCS3 : SMC NAND Flash Chip Select 3 Assignment
bits : 3 - 3 (1 bit)
access : read-write

SMC_SEL : SMC Selection for EBI pins
bits : 31 - 31 (1 bit)
access : read-write


CORE_DEBUG

Core Debug Configuration Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORE_DEBUG CORE_DEBUG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CROSS_TRG1 CROSS_TRG0

CROSS_TRG1 :
bits : 1 - 1 (1 bit)
access : read-write

CROSS_TRG0 :
bits : 2 - 2 (1 bit)
access : read-write


MCFG5

Master Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG5 MCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG[3]

Slave Configuration Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[3] SCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[3]

Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[3] MCFG[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


MCFG6

Master Configuration Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG6 MCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG[4]

Slave Configuration Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[4] SCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


WPMR

Write Protection Mode Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WPMR WPMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPEN WPKEY

WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write

WPKEY : Write Protect Key
bits : 8 - 31 (24 bit)
access : read-write

Enumeration:

0x4D4154 : PASSWD

Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.

End of enumeration elements list.


WPSR

Write Protection Status Register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPSR WPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WPVS WPVSRC

WPVS : Write Protection Violation Status
bits : 0 - 0 (1 bit)
access : read-only

WPVSRC : Write Protection Violation Source
bits : 8 - 23 (16 bit)
access : read-only


SCFG[5]

Slave Configuration Register
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[5] SCFG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG[6]

Slave Configuration Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[6] SCFG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[4]

Master Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[4] MCFG[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG[7]

Slave Configuration Register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[7] SCFG[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[5]

Master Configuration Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[5] MCFG[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


MCFG[1]

Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[1] MCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


MCFG1

Master Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG1 MCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG0

Slave Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG0 SCFG0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG1

Slave Configuration Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG1 SCFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG2

Slave Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG2 SCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG3

Slave Configuration Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG3 SCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG4

Slave Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG4 SCFG4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG[6]

Master Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[6] MCFG[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG5

Slave Configuration Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG5 SCFG5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG6

Slave Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG6 SCFG6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


SCFG7

Slave Configuration Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

SCFG7 SCFG7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


MCFG2

Master Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG2 MCFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG[0]

Slave Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[0] SCFG[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write


PRAS0

Priority Register A for Slave 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS0 PRAS0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS1

Priority Register A for Slave 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS1 PRAS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS2

Priority Register A for Slave 2
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS2 PRAS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS3

Priority Register A for Slave 3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS3 PRAS3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS4

Priority Register A for Slave 4
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS4 PRAS4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS5

Priority Register A for Slave 5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS5 PRAS5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS6

Priority Register A for Slave 6
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS6 PRAS6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


PRAS7

Priority Register A for Slave 7
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRAS7 PRAS7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0PR M1PR M2PR M3PR M4PR M5PR M6PR M7PR

M0PR : Master 0 Priority
bits : 0 - 1 (2 bit)
access : read-write

M1PR : Master 1 Priority
bits : 4 - 5 (2 bit)
access : read-write

M2PR : Master 2 Priority
bits : 8 - 9 (2 bit)
access : read-write

M3PR : Master 3 Priority
bits : 12 - 13 (2 bit)
access : read-write

M4PR : Master 4 Priority
bits : 16 - 17 (2 bit)
access : read-write

M5PR : Master 5 Priority
bits : 20 - 21 (2 bit)
access : read-write

M6PR : Master 6 Priority
bits : 24 - 25 (2 bit)
access : read-write

M7PR : Master 7 Priority
bits : 28 - 29 (2 bit)
access : read-write


MCFG[2]

Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MCFG[2] MCFG[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


MCFG3

Master Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0

MCFG3 MCFG3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ULBT

ULBT : Undefined Length Burst Type
bits : 0 - 2 (3 bit)
access : read-write


SCFG[1]

Slave Configuration Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCFG[1] SCFG[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLOT_CYCLE DEFMSTR_TYPE FIXED_DEFMSTR

SLOT_CYCLE : Maximum Bus Grant Duration for Masters
bits : 0 - 8 (9 bit)
access : read-write

DEFMSTR_TYPE : Default Master Type
bits : 16 - 17 (2 bit)
access : read-write

FIXED_DEFMSTR : Fixed Default Master
bits : 18 - 21 (4 bit)
access : read-write



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