\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
START : Start Processing
bits : 0 - 0 (1 bit)
access : write-only
SWRST : Software Reset
bits : 8 - 8 (1 bit)
access : write-only
Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Enable
bits : 0 - 0 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Enable
bits : 1 - 1 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Enable
bits : 2 - 2 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Enable
bits : 3 - 3 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Enable
bits : 4 - 4 (1 bit)
access : write-only
URAD : Unspecified Register Access Detection Interrupt Enable
bits : 8 - 8 (1 bit)
access : write-only
Receive Pointer Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPTR : Receive Pointer Register
bits : 0 - 31 (32 bit)
access : read-write
Receive Counter Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTR : Receive Counter Register
bits : 0 - 15 (16 bit)
access : read-write
Transmit Pointer Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPTR : Transmit Counter Register
bits : 0 - 31 (32 bit)
access : read-write
Input Data Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
Transmit Counter Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCTR : Transmit Counter Register
bits : 0 - 15 (16 bit)
access : read-write
GCM Authentication Tag Word Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
Receive Next Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNPTR : Receive Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Receive Next Counter Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXNCTR : Receive Next Counter
bits : 0 - 15 (16 bit)
access : read-write
Transmit Next Pointer Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNPTR : Transmit Next Pointer
bits : 0 - 31 (32 bit)
access : read-write
Key Word Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Transmit Next Counter Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXNCTR : Transmit Counter Next
bits : 0 - 15 (16 bit)
access : read-write
Transfer Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : write-only
RXTDIS : Receiver Transfer Disable
bits : 1 - 1 (1 bit)
access : write-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : write-only
TXTDIS : Transmitter Transfer Disable
bits : 9 - 9 (1 bit)
access : write-only
Initialization Vector Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Transfer Status Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RXTEN : Receiver Transfer Enable
bits : 0 - 0 (1 bit)
access : read-only
TXTEN : Transmitter Transfer Enable
bits : 8 - 8 (1 bit)
access : read-only
GCM H World Register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Disable
bits : 0 - 0 (1 bit)
access : write-only
ENDRX : End of Receive Buffer Interrupt Disable
bits : 1 - 1 (1 bit)
access : write-only
ENDTX : End of Transmit Buffer Interrupt Disable
bits : 2 - 2 (1 bit)
access : write-only
RXBUFF : Receive Buffer Full Interrupt Disable
bits : 3 - 3 (1 bit)
access : write-only
TXBUFE : Transmit Buffer Empty Interrupt Disable
bits : 4 - 4 (1 bit)
access : write-only
URAD : Unspecified Register Access Detection Interrupt Disable
bits : 8 - 8 (1 bit)
access : write-only
Output Data Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
Key Word Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Intermediate Hash Word Register
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready Interrupt Mask
bits : 0 - 0 (1 bit)
access : read-only
ENDRX : End of Receive Buffer Interrupt Mask
bits : 1 - 1 (1 bit)
access : read-only
ENDTX : End of Transmit Buffer Interrupt Mask
bits : 2 - 2 (1 bit)
access : read-only
RXBUFF : Receive Buffer Full Interrupt Mask
bits : 3 - 3 (1 bit)
access : read-only
TXBUFE : Transmit Buffer Empty Interrupt Mask
bits : 4 - 4 (1 bit)
access : read-only
URAD : Unspecified Register Access Detection Interrupt Mask
bits : 8 - 8 (1 bit)
access : read-only
Initialization Vector Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Authentication Tag Word Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
Output Data Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
DATRDY : Data Ready
bits : 0 - 0 (1 bit)
access : read-only
ENDRX : End of RX Buffer
bits : 1 - 1 (1 bit)
access : read-only
ENDTX : End of TX Buffer
bits : 2 - 2 (1 bit)
access : read-only
RXBUFF : RX Buffer Full
bits : 3 - 3 (1 bit)
access : read-only
TXBUFE : TX Buffer Empty
bits : 4 - 4 (1 bit)
access : read-only
URAD : Unspecified Register Access Detection Status
bits : 8 - 8 (1 bit)
access : read-only
URAT : Unspecified Register Access:
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0x0 : IDR_WR_PROCESSING
Input Data Register written during the data processing when SMOD = 0x2 mode.
0x1 : ODR_RD_PROCESSING
Output Data Register read during the data processing.
0x2 : MR_WR_PROCESSING
Mode Register written during the data processing.
0x3 : ODR_RD_SUBKGEN
Output Data Register read during the sub-keys generation.
0x4 : MR_WR_SUBKGEN
Mode Register written during the sub-keys generation.
0x5 : WOR_RD_ACCESS
Write-only register read access.
End of enumeration elements list.
TAGRDY : GCM Tag Ready
bits : 16 - 16 (1 bit)
access : read-only
GCM H World Register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
GCM Intermediate Hash Word Register
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
Initialization Vector Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Authentication Tag Word Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
Key Word Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Intermediate Hash Word Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
GCM H World Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
Key Word Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Authentication Tag Word Register
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
Key Word Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM H World Register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
Key Word Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Mode Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CIPHER : Processing Mode
bits : 0 - 0 (1 bit)
access : read-write
GTAGEN : GCM Automatic Tag Generation Enable
bits : 1 - 1 (1 bit)
access : read-write
DUALBUFF : Dual Input Buffer
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0x0 : INACTIVE
AES_IDATARx cannot be written during processing of previous block.
0x1 : ACTIVE
AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files.
End of enumeration elements list.
PROCDLY : Processing Delay
bits : 4 - 7 (4 bit)
access : read-write
SMOD : Start Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : MANUAL_START
Manual Mode
0x1 : AUTO_START
Auto Mode
0x2 : IDATAR0_START
AES_IDATAR0 access only Auto Mode
End of enumeration elements list.
KEYSIZE : Key Size
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : AES128
AES Key Size is 128 bits
0x1 : AES192
AES Key Size is 192 bits
0x2 : AES256
AES Key Size is 256 bits
End of enumeration elements list.
OPMOD : Operation Mode
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
0x0 : ECB
ECB: Electronic Code Book mode
0x1 : CBC
CBC: Cipher Block Chaining mode
0x2 : OFB
OFB: Output Feedback mode
0x3 : CFB
CFB: Cipher Feedback mode
0x4 : CTR
CTR: Counter mode (16-bit internal counter)
0x5 : GCM
GCM: Galois Counter mode
End of enumeration elements list.
LOD : Last Output Data Mode
bits : 15 - 15 (1 bit)
access : read-write
CFBS : Cipher Feedback Data Size
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0x0 : SIZE_128BIT
128-bit
0x1 : SIZE_64BIT
64-bit
0x2 : SIZE_32BIT
32-bit
0x3 : SIZE_16BIT
16-bit
0x4 : SIZE_8BIT
8-bit
End of enumeration elements list.
CKEY : Key
bits : 20 - 23 (4 bit)
access : read-write
Enumeration:
0xE : PASSWD
This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0.
End of enumeration elements list.
Key Word Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
Output Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
Output Data Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
Output Data Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
Output Data Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
Initialization Vector Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Initialization Vector Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Initialization Vector Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Initialization Vector Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Additional Authenticated Data Length Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AADLEN : AAD Length
bits : 0 - 31 (32 bit)
access : read-write
Plaintext/Ciphertext Length Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLEN : Plaintext/Ciphertext Length
bits : 0 - 31 (32 bit)
access : read-write
GCM Intermediate Hash Word Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
GCM Intermediate Hash Word Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
Input Data Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Intermediate Hash Word Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
GCM Intermediate Hash Word Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
GCM Authentication Tag Word Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
Key Word Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Authentication Tag Word Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
GCM Authentication Tag Word Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
GCM Authentication Tag Word Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
TAG : GCM Authentication Tag x
bits : 0 - 31 (32 bit)
access : read-only
GCM Encryption Counter Value Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CTR : GCM Encryption Counter
bits : 0 - 31 (32 bit)
access : read-only
GCM H World Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
Output Data Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
GCM H World Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
GCM H World Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
GCM H World Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
H : GCM H word x
bits : 0 - 31 (32 bit)
access : read-write
Key Word Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
Initialization Vector Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IV : Initialization Vector
bits : 0 - 31 (32 bit)
access : write-only
Input Data Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDATA : Input Data Word
bits : 0 - 31 (32 bit)
access : write-only
Key Word Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
KEYW : Key Word
bits : 0 - 31 (32 bit)
access : write-only
GCM Intermediate Hash Word Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GHASH : Intermediate GCM Hash Word x
bits : 0 - 31 (32 bit)
access : read-write
Output Data Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ODATA : Output Data
bits : 0 - 31 (32 bit)
access : read-only
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