Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Channel Control Register (channel = 0)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
access : write-only
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
access : write-only
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
access : write-only
Counter Value (channel = 0)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
access : read-only
Register A (channel = 0)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
access : read-write
Register B (channel = 0)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
access : read-write
Register C (channel = 0)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
access : read-write
Status Register (channel = 0)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
access : read-only
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
access : read-only
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
access : read-only
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
access : read-only
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
access : read-only
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
access : read-only
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
access : read-only
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
access : read-only
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
access : read-only
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
access : read-only
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
access : read-only
Interrupt Enable Register (channel = 0)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only
Interrupt Disable Register (channel = 0)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only
Interrupt Mask Register (channel = 0)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : read-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : read-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : read-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : read-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : read-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : read-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : read-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : read-only
Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
access : read-write
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
access : read-write
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
access : read-write
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
access : read-write
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOA
0x2 : FALLING
Falling edge of TIOA
0x3 : EDGE
Each edge of TIOA
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOA
0x2 : FALLING
Falling edge of TIOA
0x3 : EDGE
Each edge of TIOA
End of enumeration elements list.
Channel Mode Register (channel = 0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WAVE_EQ_1
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
access : read-write
CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
access : read-write
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : TIOB
TIOB
0x1 : XC0
XC0
0x2 : XC1
XC1
0x3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
access : read-write
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : UP
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_RC
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write
ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
Channel Control Register (channel = 1)
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
access : write-only
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
access : write-only
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
access : write-only
Channel Mode Register (channel = 1)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
access : read-write
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
access : read-write
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
access : read-write
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
access : read-write
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOA
0x2 : FALLING
Falling edge of TIOA
0x3 : EDGE
Each edge of TIOA
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOA
0x2 : FALLING
Falling edge of TIOA
0x3 : EDGE
Each edge of TIOA
End of enumeration elements list.
Channel Mode Register (channel = 1)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WAVE_EQ_1
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
access : read-write
CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
access : read-write
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : TIOB
TIOB
0x1 : XC0
XC0
0x2 : XC1
XC1
0x3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
access : read-write
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : UP
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_RC
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write
ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
Stepper Motor Mode Register (channel = 1)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
access : read-write
DOWN : DOWN Count
bits : 1 - 1 (1 bit)
access : read-write
Counter Value (channel = 1)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
access : read-only
Register A (channel = 1)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
access : read-write
Register B (channel = 1)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
access : read-write
Register C (channel = 1)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
access : read-write
Status Register (channel = 1)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
access : read-only
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
access : read-only
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
access : read-only
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
access : read-only
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
access : read-only
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
access : read-only
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
access : read-only
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
access : read-only
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
access : read-only
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
access : read-only
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
access : read-only
Interrupt Enable Register (channel = 1)
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only
Interrupt Disable Register (channel = 1)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only
Interrupt Mask Register (channel = 1)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : read-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : read-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : read-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : read-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : read-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : read-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : read-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : read-only
Stepper Motor Mode Register (channel = 0)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
access : read-write
DOWN : DOWN Count
bits : 1 - 1 (1 bit)
access : read-write
Channel Control Register (channel = 2)
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CLKEN : Counter Clock Enable Command
bits : 0 - 0 (1 bit)
access : write-only
CLKDIS : Counter Clock Disable Command
bits : 1 - 1 (1 bit)
access : write-only
SWTRG : Software Trigger Command
bits : 2 - 2 (1 bit)
access : write-only
Channel Mode Register (channel = 2)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
LDBSTOP : Counter Clock Stopped with RB Loading
bits : 6 - 6 (1 bit)
access : read-write
LDBDIS : Counter Clock Disable with RB Loading
bits : 7 - 7 (1 bit)
access : read-write
ETRGEDG : External Trigger Edge Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
ABETRG : TIOA or TIOB External Trigger Selection
bits : 10 - 10 (1 bit)
access : read-write
CPCTRG : RC Compare Trigger Enable
bits : 14 - 14 (1 bit)
access : read-write
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write
LDRA : RA Loading Edge Selection
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOA
0x2 : FALLING
Falling edge of TIOA
0x3 : EDGE
Each edge of TIOA
End of enumeration elements list.
LDRB : RB Loading Edge Selection
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge of TIOA
0x2 : FALLING
Falling edge of TIOA
0x3 : EDGE
Each edge of TIOA
End of enumeration elements list.
Channel Mode Register (channel = 2)
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : WAVE_EQ_1
reset_Mask : 0x0
TCCLKS : Clock Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : TIMER_CLOCK1
Clock selected: internal TIMER_CLOCK1 clock signal (from PMC)
0x1 : TIMER_CLOCK2
Clock selected: internal TIMER_CLOCK2 clock signal (from PMC)
0x2 : TIMER_CLOCK3
Clock selected: internal TIMER_CLOCK3 clock signal (from PMC)
0x3 : TIMER_CLOCK4
Clock selected: internal TIMER_CLOCK4 clock signal (from PMC)
0x4 : TIMER_CLOCK5
Clock selected: internal TIMER_CLOCK5 clock signal (from PMC)
0x5 : XC0
Clock selected: XC0
0x6 : XC1
Clock selected: XC1
0x7 : XC2
Clock selected: XC2
End of enumeration elements list.
CLKI : Clock Invert
bits : 3 - 3 (1 bit)
access : read-write
BURST : Burst Signal Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
The clock is not gated by an external signal.
0x1 : XC0
XC0 is ANDed with the selected clock.
0x2 : XC1
XC1 is ANDed with the selected clock.
0x3 : XC2
XC2 is ANDed with the selected clock.
End of enumeration elements list.
CPCSTOP : Counter Clock Stopped with RC Compare
bits : 6 - 6 (1 bit)
access : read-write
CPCDIS : Counter Clock Disable with RC Compare
bits : 7 - 7 (1 bit)
access : read-write
EEVTEDG : External Event Edge Selection
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : RISING
Rising edge
0x2 : FALLING
Falling edge
0x3 : EDGE
Each edge
End of enumeration elements list.
EEVT : External Event Selection
bits : 10 - 11 (2 bit)
access : read-write
Enumeration:
0x0 : TIOB
TIOB
0x1 : XC0
XC0
0x2 : XC1
XC1
0x3 : XC2
XC2
End of enumeration elements list.
ENETRG : External Event Trigger Enable
bits : 12 - 12 (1 bit)
access : read-write
WAVSEL : Waveform Selection
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
0x0 : UP
UP mode without automatic trigger on RC Compare
0x1 : UPDOWN
UPDOWN mode without automatic trigger on RC Compare
0x2 : UP_RC
UP mode with automatic trigger on RC Compare
0x3 : UPDOWN_RC
UPDOWN mode with automatic trigger on RC Compare
End of enumeration elements list.
WAVE : Waveform Mode
bits : 15 - 15 (1 bit)
access : read-write
ACPA : RA Compare Effect on TIOA
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
ACPC : RC Compare Effect on TIOA
bits : 18 - 19 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
AEEVT : External Event Effect on TIOA
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
ASWTRG : Software Trigger Effect on TIOA
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BCPB : RB Compare Effect on TIOB
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BCPC : RC Compare Effect on TIOB
bits : 26 - 27 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BEEVT : External Event Effect on TIOB
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
BSWTRG : Software Trigger Effect on TIOB
bits : 30 - 31 (2 bit)
access : read-write
Enumeration:
0x0 : NONE
None
0x1 : SET
Set
0x2 : CLEAR
Clear
0x3 : TOGGLE
Toggle
End of enumeration elements list.
Stepper Motor Mode Register (channel = 2)
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GCEN : Gray Count Enable
bits : 0 - 0 (1 bit)
access : read-write
DOWN : DOWN Count
bits : 1 - 1 (1 bit)
access : read-write
Counter Value (channel = 2)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
CV : Counter Value
bits : 0 - 31 (32 bit)
access : read-only
Register A (channel = 2)
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RA : Register A
bits : 0 - 31 (32 bit)
access : read-write
Register B (channel = 2)
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB : Register B
bits : 0 - 31 (32 bit)
access : read-write
Register C (channel = 2)
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RC : Register C
bits : 0 - 31 (32 bit)
access : read-write
Status Register (channel = 2)
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow Status
bits : 0 - 0 (1 bit)
access : read-only
LOVRS : Load Overrun Status
bits : 1 - 1 (1 bit)
access : read-only
CPAS : RA Compare Status
bits : 2 - 2 (1 bit)
access : read-only
CPBS : RB Compare Status
bits : 3 - 3 (1 bit)
access : read-only
CPCS : RC Compare Status
bits : 4 - 4 (1 bit)
access : read-only
LDRAS : RA Loading Status
bits : 5 - 5 (1 bit)
access : read-only
LDRBS : RB Loading Status
bits : 6 - 6 (1 bit)
access : read-only
ETRGS : External Trigger Status
bits : 7 - 7 (1 bit)
access : read-only
CLKSTA : Clock Enabling Status
bits : 16 - 16 (1 bit)
access : read-only
MTIOA : TIOA Mirror
bits : 17 - 17 (1 bit)
access : read-only
MTIOB : TIOB Mirror
bits : 18 - 18 (1 bit)
access : read-only
Interrupt Enable Register (channel = 2)
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only
Interrupt Disable Register (channel = 2)
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : write-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : write-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : write-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : write-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : write-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : write-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : write-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : write-only
Interrupt Mask Register (channel = 2)
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
COVFS : Counter Overflow
bits : 0 - 0 (1 bit)
access : read-only
LOVRS : Load Overrun
bits : 1 - 1 (1 bit)
access : read-only
CPAS : RA Compare
bits : 2 - 2 (1 bit)
access : read-only
CPBS : RB Compare
bits : 3 - 3 (1 bit)
access : read-only
CPCS : RC Compare
bits : 4 - 4 (1 bit)
access : read-only
LDRAS : RA Loading
bits : 5 - 5 (1 bit)
access : read-only
LDRBS : RB Loading
bits : 6 - 6 (1 bit)
access : read-only
ETRGS : External Trigger
bits : 7 - 7 (1 bit)
access : read-only
Block Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
SYNC : Synchro Command
bits : 0 - 0 (1 bit)
access : write-only
Block Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TC0XC0S : External Clock Signal 0 Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : TCLK0
Signal connected to XC0: TCLK0
0x2 : TIOA1
Signal connected to XC0: TIOA1
0x3 : TIOA2
Signal connected to XC0: TIOA2
End of enumeration elements list.
TC1XC1S : External Clock Signal 1 Selection
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0x0 : TCLK1
Signal connected to XC1: TCLK1
0x2 : TIOA0
Signal connected to XC1: TIOA0
0x3 : TIOA2
Signal connected to XC1: TIOA2
End of enumeration elements list.
TC2XC2S : External Clock Signal 2 Selection
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : TCLK2
Signal connected to XC2: TCLK2
0x2 : TIOA0
Signal connected to XC2: TIOA0
0x3 : TIOA1
Signal connected to XC2: TIOA1
End of enumeration elements list.
QDEN : Quadrature Decoder ENabled
bits : 8 - 8 (1 bit)
access : read-write
POSEN : POSition ENabled
bits : 9 - 9 (1 bit)
access : read-write
SPEEDEN : SPEED ENabled
bits : 10 - 10 (1 bit)
access : read-write
QDTRANS : Quadrature Decoding TRANSparent
bits : 11 - 11 (1 bit)
access : read-write
EDGPHA : EDGe on PHA count mode
bits : 12 - 12 (1 bit)
access : read-write
INVA : INVerted phA
bits : 13 - 13 (1 bit)
access : read-write
INVB : INVerted phB
bits : 14 - 14 (1 bit)
access : read-write
INVIDX : INVerted InDeX
bits : 15 - 15 (1 bit)
access : read-write
SWAP : SWAP PHA and PHB
bits : 16 - 16 (1 bit)
access : read-write
IDXPHB : InDeX pin is PHB pin
bits : 17 - 17 (1 bit)
access : read-write
FILTER : Glitch Filter
bits : 19 - 19 (1 bit)
access : read-write
MAXFILT : MAXimum FILTer
bits : 20 - 25 (6 bit)
access : read-write
QDEC Interrupt Enable Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDX : InDeX
bits : 0 - 0 (1 bit)
access : write-only
DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : write-only
QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : write-only
QDEC Interrupt Disable Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
IDX : InDeX
bits : 0 - 0 (1 bit)
access : write-only
DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : write-only
QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : write-only
QDEC Interrupt Mask Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDX : InDeX
bits : 0 - 0 (1 bit)
access : read-only
DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : read-only
QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : read-only
QDEC Interrupt Status Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
IDX : InDeX
bits : 0 - 0 (1 bit)
access : read-only
DIRCHG : DIRection CHanGe
bits : 1 - 1 (1 bit)
access : read-only
QERR : Quadrature ERRor
bits : 2 - 2 (1 bit)
access : read-only
DIR : DIRection
bits : 8 - 8 (1 bit)
access : read-only
Write Protection Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WPEN : Write Protect Enable
bits : 0 - 0 (1 bit)
access : read-write
WPKEY : Write Protect KEY
bits : 8 - 31 (24 bit)
access : read-write
Enumeration:
0x54494D : PASSWD
Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0.
End of enumeration elements list.
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