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ABDACB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR

VCR1

IER

IDR

IMR

SR

SCR

PARAMETER

VERSION

SDR0

SDR1

VCR0


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN SWAP ALTUPR CMOC MONO SWRST DATAFORMAT FS

EN : Enable
bits : 0 - 0 (1 bit)

Enumeration: ENSelect

0x0 : 0

Audio DAC is disabled

0x1 : 1

Audio DAC is enabled

End of enumeration elements list.

SWAP : Swap Channels
bits : 1 - 1 (1 bit)

Enumeration: SWAPSelect

0x0 : 0

The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio DAC Sample Data Register (SDR)

0x1 : 1

The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio DAC Sample Data Register (SDR)

End of enumeration elements list.

ALTUPR : Alternative up-sampling ratio
bits : 3 - 3 (1 bit)

CMOC : Common mode offset control
bits : 4 - 4 (1 bit)

MONO : Mono mode
bits : 5 - 5 (1 bit)

SWRST : Software reset
bits : 7 - 7 (1 bit)

DATAFORMAT : Data word format
bits : 16 - 18 (3 bit)

FS : Sampling frequency
bits : 24 - 27 (4 bit)


VCR1

Volume Control Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCR1 VCR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOLUME MUTE

VOLUME : Volume Control
bits : 0 - 14 (15 bit)

MUTE : Mute
bits : 31 - 31 (1 bit)


IER

Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXUR

TXRDY : Transmit Ready Interrupt Enable
bits : 1 - 1 (1 bit)

Enumeration: TXRDYSelect

0x0 : 0

No effect

0x1 : 1

Enables the Audio DAC TX Ready interrupt

End of enumeration elements list.

TXUR : Transmit Underrun Interrupt Enable
bits : 2 - 2 (1 bit)

Enumeration: TXURSelect

0x0 : 0

No effect

0x1 : 1

Enables the Audio DAC Underrun interrupt

End of enumeration elements list.


IDR

Interupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXUR

TXRDY : Transmit Ready Interrupt Disable
bits : 1 - 1 (1 bit)

Enumeration: TXRDYSelect

0x0 : 0

No effect

0x1 : 1

Disable the Audio DAC TX Ready interrupt

End of enumeration elements list.

TXUR : Transmit Underrun Interrupt Disable
bits : 2 - 2 (1 bit)

Enumeration: TXURSelect

0x0 : 0

No effect

0x1 : 1

Disable the Audio DAC Underrun interrupt

End of enumeration elements list.


IMR

Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXUR

TXRDY : Transmit Ready Interrupt Mask
bits : 1 - 1 (1 bit)

Enumeration: TXRDYSelect

0x0 : 0

The Audio DAC TX Ready interrupt is disabled

0x1 : 1

The Audio DAC TX Ready interrupt is enabled

End of enumeration elements list.

TXUR : Transmit Underrun Interrupt Mask
bits : 2 - 2 (1 bit)

Enumeration: TXURSelect

0x0 : 0

The Audio DAC Underrun interrupt is disabled

0x1 : 1

The Audio DAC Underrun interrupt is enabled

End of enumeration elements list.


SR

Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY TXRDY TXUR

BUSY : ABDACB Busy
bits : 0 - 0 (1 bit)

TXRDY : Transmit Ready
bits : 1 - 1 (1 bit)

Enumeration: TXRDYSelect

0x0 : 0

No Audio DAC TX Ready has occured since the last time ISR was read or since reset

0x1 : 1

At least one Audio DAC TX Ready has occured since the last time ISR was read or since reset

End of enumeration elements list.

TXUR : Transmit Underrun
bits : 2 - 2 (1 bit)

Enumeration: TXURSelect

0x0 : 0

No Audio DAC Underrun has occured since the last time ISR was read or since reset

0x1 : 1

At least one Audio DAC Underrun has occured since the last time ISR was read or since reset

End of enumeration elements list.


SCR

Status Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXRDY TXUR

TXRDY : Transmit Ready Interrupt Clear
bits : 1 - 1 (1 bit)

Enumeration: TXRDYSelect

0x0 : 0

No effect

0x1 : 1

Clear the Audio DAC TX Ready interrupt

End of enumeration elements list.

TXUR : Transmit Underrun Interrupt Clear
bits : 2 - 2 (1 bit)

Enumeration: TXURSelect

0x0 : 0

No effect

0x1 : 1

Clear the Audio DAC Underrun interrupt

End of enumeration elements list.


PARAMETER

Parameter Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PARAMETER PARAMETER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

VERSION

Version Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)

VARIANT : Variant Number
bits : 16 - 19 (4 bit)


SDR0

Sample Data Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR0 SDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Sample Data
bits : 0 - 31 (32 bit)


SDR1

Sample Data Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDR1 SDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Sample Data
bits : 0 - 31 (32 bit)


VCR0

Volume Control Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VCR0 VCR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VOLUME MUTE

VOLUME : Volume Control
bits : 0 - 14 (15 bit)

MUTE : Mute
bits : 31 - 31 (1 bit)



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