\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
Enumeration: ENSelect
0x0 : 0
Audio DAC is disabled
0x1 : 1
Audio DAC is enabled
End of enumeration elements list.
SWAP : Swap Channels
bits : 1 - 1 (1 bit)
Enumeration: SWAPSelect
0x0 : 0
The CHANNEL0 and CHANNEL1 samples will not be swapped when writing the Audio DAC Sample Data Register (SDR)
0x1 : 1
The CHANNEL0 and CHANNEL1 samples will be swapped when writing the Audio DAC Sample Data Register (SDR)
End of enumeration elements list.
ALTUPR : Alternative up-sampling ratio
bits : 3 - 3 (1 bit)
CMOC : Common mode offset control
bits : 4 - 4 (1 bit)
MONO : Mono mode
bits : 5 - 5 (1 bit)
SWRST : Software reset
bits : 7 - 7 (1 bit)
DATAFORMAT : Data word format
bits : 16 - 18 (3 bit)
FS : Sampling frequency
bits : 24 - 27 (4 bit)
Volume Control Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VOLUME : Volume Control
bits : 0 - 14 (15 bit)
MUTE : Mute
bits : 31 - 31 (1 bit)
Interrupt Enable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Enable
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No effect
0x1 : 1
Enables the Audio DAC TX Ready interrupt
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Enable
bits : 2 - 2 (1 bit)
Enumeration: TXURSelect
0x0 : 0
No effect
0x1 : 1
Enables the Audio DAC Underrun interrupt
End of enumeration elements list.
Interupt Disable Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Disable
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No effect
0x1 : 1
Disable the Audio DAC TX Ready interrupt
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Disable
bits : 2 - 2 (1 bit)
Enumeration: TXURSelect
0x0 : 0
No effect
0x1 : 1
Disable the Audio DAC Underrun interrupt
End of enumeration elements list.
Interrupt Mask Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Mask
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
The Audio DAC TX Ready interrupt is disabled
0x1 : 1
The Audio DAC TX Ready interrupt is enabled
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Mask
bits : 2 - 2 (1 bit)
Enumeration: TXURSelect
0x0 : 0
The Audio DAC Underrun interrupt is disabled
0x1 : 1
The Audio DAC Underrun interrupt is enabled
End of enumeration elements list.
Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
BUSY : ABDACB Busy
bits : 0 - 0 (1 bit)
TXRDY : Transmit Ready
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No Audio DAC TX Ready has occured since the last time ISR was read or since reset
0x1 : 1
At least one Audio DAC TX Ready has occured since the last time ISR was read or since reset
End of enumeration elements list.
TXUR : Transmit Underrun
bits : 2 - 2 (1 bit)
Enumeration: TXURSelect
0x0 : 0
No Audio DAC Underrun has occured since the last time ISR was read or since reset
0x1 : 1
At least one Audio DAC Underrun has occured since the last time ISR was read or since reset
End of enumeration elements list.
Status Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
TXRDY : Transmit Ready Interrupt Clear
bits : 1 - 1 (1 bit)
Enumeration: TXRDYSelect
0x0 : 0
No effect
0x1 : 1
Clear the Audio DAC TX Ready interrupt
End of enumeration elements list.
TXUR : Transmit Underrun Interrupt Clear
bits : 2 - 2 (1 bit)
Enumeration: TXURSelect
0x0 : 0
No effect
0x1 : 1
Clear the Audio DAC Underrun interrupt
End of enumeration elements list.
Parameter Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Version Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VERSION : Version Number
bits : 0 - 11 (12 bit)
VARIANT : Variant Number
bits : 16 - 19 (4 bit)
Sample Data Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Sample Data
bits : 0 - 31 (32 bit)
Sample Data Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Sample Data
bits : 0 - 31 (32 bit)
Volume Control Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VOLUME : Volume Control
bits : 0 - 14 (15 bit)
MUTE : Mute
bits : 31 - 31 (1 bit)
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