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AST

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CR

IER

IDR

IMR

WER

AR0

AR1

PIR0

PIR1

CV

CLOCK

DTR

EVE

EVD

EVM

CALV

SR

SCR

PARAMETER

VERSION


CR

Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PCLR CAL CA0 CA1 PSEL

EN : Enable
bits : 0 - 0 (1 bit)

Enumeration: ENSelect

0x0 : 0

The AST is disabled.

0x1 : 1

The AST is enabled

End of enumeration elements list.

PCLR : Prescaler Clear
bits : 1 - 1 (1 bit)

CAL : Calendar mode
bits : 2 - 2 (1 bit)

CA0 : Clear on Alarm 0
bits : 8 - 8 (1 bit)

CA1 : Clear on Alarm 1
bits : 9 - 9 (1 bit)

PSEL : Prescaler Select
bits : 16 - 20 (5 bit)


IER

Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IER IER write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1 READY CLKRDY

OVF : Overflow
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: OVFSelect

0x0 : 0

No effect

0x1 : 1

Enable Interrupt.

End of enumeration elements list.

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : write-only

Enumeration: ALARM0Select

0x0 : 0

No effect

0x1 : 1

Enable interrupt

End of enumeration elements list.

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : write-only

Enumeration: ALARM1Select

0x0 : 0

No effect

0x1 : 1

Enable interrupt

End of enumeration elements list.

PER0 : Periodic 0
bits : 16 - 16 (1 bit)
access : write-only

Enumeration: PER0Select

0x0 : 0

No effect

0x1 : 1

Enable interrupt

End of enumeration elements list.

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : write-only

Enumeration: PER1Select

0x0 : 0

No effect

0x1 : 1

Enable interrupt

End of enumeration elements list.

READY : AST Ready
bits : 25 - 25 (1 bit)
access : write-only

Enumeration: READYSelect

0x0 : 0

No effect

0x1 : 1

Enable interrupt

End of enumeration elements list.

CLKRDY : Clock Ready
bits : 29 - 29 (1 bit)
access : write-only

Enumeration: CLKRDYSelect

0x0 : 0

No effect

0x1 : 1

Enable interrupt

End of enumeration elements list.


IDR

Interrupt Disable Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

IDR IDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1 READY CLKRDY

OVF : Overflow
bits : 0 - 0 (1 bit)
access : write-only

Enumeration: OVFSelect

0x0 : 0

No effect

0x1 : 1

Disable Interrupt.

End of enumeration elements list.

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : write-only

Enumeration: ALARM0Select

0x0 : 0

No effect

0x1 : 1

Disable interrupt

End of enumeration elements list.

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : write-only

Enumeration: ALARM1Select

0x0 : 0

No effect

0x1 : 1

Disable interrupt

End of enumeration elements list.

PER0 : Periodic 0
bits : 16 - 16 (1 bit)
access : write-only

Enumeration: PER0Select

0x0 : 0

No effet

0x1 : 1

Disalbe interrupt

End of enumeration elements list.

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : write-only

Enumeration: PER1Select

0x0 : 0

No effect

0x1 : 1

Disable interrupt

End of enumeration elements list.

READY : AST Ready
bits : 25 - 25 (1 bit)
access : write-only

Enumeration: READYSelect

0x0 : 0

No effect

0x1 : 1

Disable interrupt

End of enumeration elements list.

CLKRDY : Clock Ready
bits : 29 - 29 (1 bit)
access : write-only

Enumeration: CLKRDYSelect

0x0 : 0

No effect

0x1 : 1

Disable interrupt

End of enumeration elements list.


IMR

Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

IMR IMR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1 READY CLKRDY

OVF : Overflow
bits : 0 - 0 (1 bit)
access : read-only

Enumeration: OVFSelect

0x0 : 0

Interrupt is disabled

0x1 : 1

Interrupt is enabled.

End of enumeration elements list.

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : read-only

Enumeration: ALARM0Select

0x0 : 0

Interupt is disabled

0x1 : 1

Interrupt is enabled

End of enumeration elements list.

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : read-only

Enumeration: ALARM1Select

0x0 : 0

Interrupt is disabled

0x1 : 1

Interrupt is enabled

End of enumeration elements list.

PER0 : Periodic 0
bits : 16 - 16 (1 bit)
access : read-only

Enumeration: PER0Select

0x0 : 0

Interrupt is disabled

0x1 : 1

Interrupt is enabled

End of enumeration elements list.

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : read-only

Enumeration: PER1Select

0x0 : 0

Interrupt is disabled

0x1 : 1

Interrupt is enabled

End of enumeration elements list.

READY : AST Ready
bits : 25 - 25 (1 bit)
access : read-only

Enumeration: READYSelect

0x0 : 0

Interrupt is disabled

0x1 : 1

Interrupt is enabled

End of enumeration elements list.

CLKRDY : Clock Ready
bits : 29 - 29 (1 bit)
access : read-only

Enumeration: CLKRDYSelect

0x0 : 0

Interrupt is disabled

0x1 : 1

Interrupt is enabled

End of enumeration elements list.


WER

Wake Enable Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WER WER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1

OVF : Overflow
bits : 0 - 0 (1 bit)

Enumeration: OVFSelect

0x0 : 0

The corresponing event will not wake up the CPU from sleep mode

0x1 : 1

The corresponding event will wake up the CPU from sleep mode

End of enumeration elements list.

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)

Enumeration: ALARM0Select

0x0 : 0

The corresponing event will not wake up the CPU from sleep mode

0x1 : 1

The corresponding event will wake up the CPU from sleep mode

End of enumeration elements list.

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)

Enumeration: ALARM1Select

0x0 : 0

The corresponing event will not wake up the CPU from sleep mode

0x1 : 1

The corresponding event will wake up the CPU from sleep mode

End of enumeration elements list.

PER0 : Periodic 0
bits : 16 - 16 (1 bit)

Enumeration: PER0Select

0x0 : 0

The corresponing event will not wake up the CPU from sleep mode

0x1 : 1

The corresponding event will wake up the CPU from sleep mode

End of enumeration elements list.

PER1 : Periodic 1
bits : 17 - 17 (1 bit)

Enumeration: PER1Select

0x0 : 0

The corresponing event will not wake up the CPU from sleep mode

0x1 : 1

The corresponding event will wake up the CPU from sleep mode

End of enumeration elements list.


AR0

Alarm Register 0
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR0 AR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Alarm Value
bits : 0 - 31 (32 bit)


AR1

Alarm Register 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AR1 AR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Alarm Value
bits : 0 - 31 (32 bit)


PIR0

Periodic Interval Register 0
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIR0 PIR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSEL

INSEL : Interval Select
bits : 0 - 4 (5 bit)


PIR1

Periodic Interval Register 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIR1 PIR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INSEL

INSEL : Interval Select
bits : 0 - 4 (5 bit)


CV

Counter Value
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CV CV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : AST Value
bits : 0 - 31 (32 bit)


CLOCK

Clock Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCK CLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEN CSSEL

CEN : Clock Enable
bits : 0 - 0 (1 bit)

Enumeration: CENSelect

0x0 : 0

The clock is disabled

0x1 : 1

The clock is enabled

End of enumeration elements list.

CSSEL : Clock Source Selection
bits : 8 - 10 (3 bit)

Enumeration: CSSELSelect

0x0 : SLOWCLOCK

Slow clock

0x1 : 32KHZCLK

32 kHz clock

0x2 : PBCLOCK

PB clock

0x3 : GCLK

Generic clock

0x4 : 1KHZCLK

1kHz clock from 32 kHz oscillator

End of enumeration elements list.


DTR

Digital Tuner Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTR DTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXP ADD VALUE

EXP : EXP
bits : 0 - 4 (5 bit)

ADD : ADD
bits : 5 - 5 (1 bit)

VALUE : VALUE
bits : 8 - 15 (8 bit)


EVE

Event Enable Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EVE EVE write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1

OVF : Overflow
bits : 0 - 0 (1 bit)
access : write-only

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : write-only

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : write-only

PER0 : Perioidc 0
bits : 16 - 16 (1 bit)
access : write-only

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : write-only


EVD

Event Disable Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

EVD EVD write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1

OVF : Overflow
bits : 0 - 0 (1 bit)
access : write-only

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : write-only

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : write-only

PER0 : Perioidc 0
bits : 16 - 16 (1 bit)
access : write-only

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : write-only


EVM

Event Mask Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

EVM EVM read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1

OVF : Overflow
bits : 0 - 0 (1 bit)
access : read-only

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : read-only

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : read-only

PER0 : Perioidc 0
bits : 16 - 16 (1 bit)
access : read-only

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : read-only


CALV

Calendar Value
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CALV CALV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEC MIN HOUR DAY MONTH YEAR

SEC : Second
bits : 0 - 5 (6 bit)

MIN : Minute
bits : 6 - 11 (6 bit)

HOUR : Hour
bits : 12 - 16 (5 bit)

DAY : Day
bits : 17 - 21 (5 bit)

MONTH : Month
bits : 22 - 25 (4 bit)

YEAR : Year
bits : 26 - 31 (6 bit)


SR

Status Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

SR SR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1 BUSY READY CLKBUSY CLKRDY

OVF : Overflow
bits : 0 - 0 (1 bit)
access : read-only

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : read-only

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : read-only

PER0 : Periodic 0
bits : 16 - 16 (1 bit)
access : read-only

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : read-only

BUSY : AST Busy
bits : 24 - 24 (1 bit)
access : read-only

Enumeration: BUSYSelect

0x0 : 0

The AST accepts writes to CV, WER, DTR, SCR, AR, PIR and CR

0x1 : 1

The AST is busy and will discard writes to CV, WER, DTR, SCR, AR, PIR and CR

End of enumeration elements list.

READY : AST Ready
bits : 25 - 25 (1 bit)
access : read-only

CLKBUSY : Clock Busy
bits : 28 - 28 (1 bit)
access : read-only

Enumeration: CLKBUSYSelect

0x0 : 0

The clock is ready and can be changed

0x1 : 1

CEN has been written and the clock is busy

End of enumeration elements list.

CLKRDY : Clock Ready
bits : 29 - 29 (1 bit)
access : read-only


SCR

Status Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SCR SCR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF ALARM0 ALARM1 PER0 PER1 READY CLKRDY

OVF : Overflow
bits : 0 - 0 (1 bit)
access : write-only

ALARM0 : Alarm 0
bits : 8 - 8 (1 bit)
access : write-only

ALARM1 : Alarm 1
bits : 9 - 9 (1 bit)
access : write-only

PER0 : Periodic 0
bits : 16 - 16 (1 bit)
access : write-only

PER1 : Periodic 1
bits : 17 - 17 (1 bit)
access : write-only

READY : AST Ready
bits : 25 - 25 (1 bit)
access : write-only

CLKRDY : Clock Ready
bits : 29 - 29 (1 bit)
access : write-only


PARAMETER

Parameter Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

PARAMETER PARAMETER read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT DTEXPWA DTEXPVALUE NUMAR NUMPIR PIR0WA PIR1WA PER0VALUE PER1VALUE

DT : Digital Tuner
bits : 0 - 0 (1 bit)
access : read-only

Enumeration: DTSelect

0x0 : OFF

Digital tuner off

0x1 : ON

Digital tuner on

End of enumeration elements list.

DTEXPWA : Digital Tuner Exponent Writeable
bits : 1 - 1 (1 bit)
access : read-only

Enumeration: DTEXPWASelect

0x0 : 0

Digital tuner exponent is a constant value. Writes to EXP bitfield in DTR will be discarded.

0x1 : 1

Digital tuner exponent is chosen by writing to EXP bitfield in DTR

End of enumeration elements list.

DTEXPVALUE : Digital Tuner Exponent Value
bits : 2 - 6 (5 bit)
access : read-only

NUMAR : Number of alarm comparators
bits : 8 - 9 (2 bit)
access : read-only

Enumeration: NUMARSelect

0x0 : ZERO

No alarm comparators

0x1 : ONE

One alarm comparator

0x2 : TWO

Two alarm comparators

End of enumeration elements list.

NUMPIR : Number of periodic comparators
bits : 12 - 12 (1 bit)
access : read-only

Enumeration: NUMPIRSelect

0x0 : ONE

One periodic comparator

0x1 : TWO

Two periodic comparators

End of enumeration elements list.

PIR0WA : Periodic Interval 0 Writeable
bits : 14 - 14 (1 bit)
access : read-only

Enumeration: PIR0WASelect

0x0 : 0

Periodic alarm prescaler 0 tapping is a constant value. Writes to INSEL bitfield in PIR0 will be discarded.

0x1 : 1

Periodic alarm prescaler 0 tapping is chosen by writing to INSEL bitfield in PIR0

End of enumeration elements list.

PIR1WA : Periodic Interval 1 Writeable
bits : 15 - 15 (1 bit)
access : read-only

Enumeration: PIR1WASelect

0x0 : 0

Writes to PIR1 will be discarded

0x1 : 1

PIR1 can be written

End of enumeration elements list.

PER0VALUE : Periodic Interval 0 Value
bits : 16 - 20 (5 bit)
access : read-only

PER1VALUE : Periodic Interval 1 Value
bits : 24 - 28 (5 bit)
access : read-only


VERSION

Version Register
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VERSION VARIANT

VERSION : Version Number
bits : 0 - 11 (12 bit)
access : read-only

VARIANT : Variant Number
bits : 16 - 19 (4 bit)
access : read-only



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